URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
Subversion Repositories xucpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/xucpu/trunk/src
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/system/S2.vhdl
88,7 → 88,7
-- CPU specific connections |
I_CPU_IF => CPU_IF, |
I_CPU_INSTR_ADDR => CPU_INSTR_ADDR, |
I_CPU_INSTRUCTION => CPU_INSTRUCTION); |
O_CPU_INSTRUCTION => CPU_INSTRUCTION); |
|
DCC1 : S2DCC |
PORT MAP ( |
110,7 → 110,7
-- CPU specific connections |
I_CPU_RD => CPU_RD, |
I_CPU_WR => CPU_WR, |
I_CPU_DATA_ADDR => CPU_DATA_ADDRESS, |
I_CPU_DATA_ADDR => CPU_DATA_ADDR, |
I_CPU_DATA => CPU_DATA_OUT, |
O_CPU_DATA => CPU_DATA_IN); |
|
126,7 → 126,7
-- Data cache connections |
O_RD => CPU_RD, |
O_WR => CPU_WR, |
O_DATA_ADDR => CPU_DATA_ADDRESS, |
O_DATA_ADDR => CPU_DATA_ADDR, |
O_DATA => CPU_DATA_OUT, |
I_DATA => CPU_DATA_IN); |
|
/system/S2CPU.vhdl
20,8 → 20,30
|
ARCHITECTURE Structural OF S2CPU IS |
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SIGNAL PC : INTEGER RANGE 0 TO 32767 := 0; |
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BEGIN -- ARCHITECTURE Structural |
|
|
-- purpose: Let counter run to fetch instructions |
-- type : combinational |
-- inputs : CLK,RST |
-- outputs: O_INSTR_ADDR |
IF1: PROCESS (CLK,RST) IS |
BEGIN -- PROCESS IF1 |
IF rising_edge(CLK) THEN |
IF rst = '1' THEN |
PC <= 0; |
ELSE |
IF PC = 32767 THEN |
PC <= 0; |
ELSE |
PC <= PC + 1; |
END IF; |
END IF; |
END IF; |
END PROCESS IF1; |
|
O_IF <= '1'; |
O_INSTR_ADDR <= STD_LOGIC_VECTOR(to_unsigned(PC, 15)); |
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END ARCHITECTURE Structural; |
/system/S2LIB.vhdl
1,3 → 1,6
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
PACKAGE S2LIB IS |
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COMPONENT S2ARB IS |