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URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

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  • This comparison shows the changes necessary to convert path 
    /xucpu
    from Rev 38 to Rev 39
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  •

Rev 38 → Rev 39

/trunk/ss/arch/board.vhdl
67,29 → 67,41
END COMPONENT address_decoder;
 
COMPONENT bus_arbiter IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
rd_rq : IN STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
wr_rq : IN STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
master_ack : OUT STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0));
END COMPONENT bus_arbiter;
 
SIGNAL rd_rq : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
SIGNAL wr_rq : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
SIGNAL master_ack : STD_LOGIC_VECTOR(nr_of_masters - 1 DOWNTO 0);
 
-- Definition of master devices attached to the bus
COMPONENT icache IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
data_rd : OUT STD_LOGIC;
bus_wait : IN STD_LOGIC);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
data_rd : OUT STD_LOGIC;
bus_wait : IN STD_LOGIC;
master_ack : IN STD_LOGIC);
END COMPONENT icache;
 
COMPONENT dcache IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
data_rd : OUT STD_LOGIC;
data_wr : OUT STD_LOGIC;
bus_wait : IN STD_LOGIC);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
data_rd : OUT STD_LOGIC;
data_wr : OUT STD_LOGIC;
bus_wait : IN STD_LOGIC;
master_ack : IN STD_LOGIC);
END COMPONENT dcache;
 
-- Definition of io devices attached to the bus
123,6 → 135,13
BEGIN -- ARCHITECTURE Structural
 
-- Mapping of bus related components
bus_arbiter_1 : bus_arbiter
PORT MAP (
clk => clk,
rst => rst,
rd_rq => rd_rq,
wr_rq => wr_rq,
master_ack => master_ack);
 
-- Mapping of system devices
 
129,8 → 148,28
-- Main memory
 
-- Instruction cache
icache_1 : icache
PORT MAP (
clk => clk,
rst => rst,
data_in => data_bus,
addr_out => device_address_out(0),
data_rd => rd_rq(0),
bus_wait => bus_wait,
master_ack => master_ack(0));
 
-- Data cache
dcache_1 : dcache
PORT MAP (
clk => clk,
rst => rst,
data_in => data_bus,
data_out => device_data_out(1),
addr_out => device_address_out(1),
data_rd => rd_rq(1),
data_wr => wr_rq(1),
bus_wait => bus_wait,
master_ack => master_ack(0));
 
-- LED output device
led_out_1 : led_out
146,7 → 185,7
PORT MAP (
clk => clk,
rst => rst,
data_out => device_data_out(0)(7 DOWNTO 0),
data_out => device_data_out(3)(7 DOWNTO 0),
addr_in => address_bus,
port_in => button);
 
155,7 → 194,7
PORT MAP (
clk => clk,
rst => rst,
data_out => device_data_out(1)(7 DOWNTO 0),
data_out => device_data_out(4)(7 DOWNTO 0),
addr_in => address_bus,
port_in => switch);
 

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