URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
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- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/doc
- from Rev 20 to Rev 31
- ↔ Reverse comparison
Rev 20 → Rev 31
/wishbone.html
4,10 → 4,11
<TABLE align=center> |
<TR><TH>Wishbone Address</TH><TH align=center>Words</TH><TH align=left>Usage</TH></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0000_xxxx_xxxx</TT></TD><TH align=right>256</TH><TD>Undefined Memory (Bus Error)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_000x</TT></TD><TH align=right>1</TH><TD>(Reserved)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0010</TT></TD><TH align=right>1</TH><TD>Version</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0011</TT></TD><TH align=right>1</TH><TD>JTAG Accessible Interrupt Controller</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0100</TT></TD><TH align=right>1</TH><TD>Bus Error (Includes errors induced from JTAG-wishbone controller)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0000</TT></TD><TH align=right>1</TH><TD>(Reserved)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0001</TT></TD><TH align=right>1</TH><TD>Version</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0010</TT></TD><TH align=right>1</TH><TD>JTAG Accessible Interrupt Controller</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0011</TT></TD><TH align=right>1</TH><TD>Bus Error (Includes errors induced from JTAG-wishbone controller)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0100</TT></TD><TH align=right>1</TH><TD>ZipTimer</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0101</TT></TD><TH align=right>1</TH><TD>RTC Date</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0110</TT></TD><TH align=right>1</TH><TD>GPIO control</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0111</TT></TD><TH align=right>1</TH><TD>UART Control word</TD></TR> |
17,7 → 18,7
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_11xx</TT></TD><TH align=right>4</TH><TD>Flash Control Words</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_0xxx</TT></TD><TH align=right>8</TH><TD>RTC Clock</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_1yyx</TT></TD><TH align=right>2</TH><TD>Scope #Y (0..3)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>?</TH><TD>SD Card Control</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>?</TH><TD>SD Card Control (Not yet implemented)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_01xx_xxxx</TT></TD><TH align=right>32</TH><TD>(ICAPE Access -- not yet proven)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_001x_xxxx_xxxx_xxxx</TT></TD><TH align=right>8k</TH><TD>On Chip RAM</TD></TR> |
<TR><TD align=right><TT>0_0000_01xx_xxxx_xxxx_xxxx_xxxx</TT></TD><TH align=right>256k</TH><TD>1 MB SPI Flash (256kW)</TD></TR> |
44,6 → 45,10
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1111</TT></TD><TH align=right>1</TH><TD>User Instruction Counter</TD></TR> |
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0001_00xx</TT></TD><TH align=right>1</TH><TD>DMA Controller</TD></TR> |
</TABLE> |
<!-- |
<h3 align=center>Speed-I/O assignments</H3> |
--> |
|
<h1 align=center>Primary (ZipSystem) Interrupt Controller Assignments</H1> |
<TABLE align=center> |
<TR><TD><TH align=right>0</TH><TD>DMA controller</TD></TR> |
84,6 → 89,7
<TR><TD><TH align=right>5</TH><TD>PWM</TD></TR> |
<TR><TD><TH align=right>6</TH><TD>RX UART</TD></TR> |
<TR><TD><TH align=right>7</TH><TD>TX UART</TD></TR> |
<TR><TD><TH align=right>8-14</TH><TD>(Unused / reserved)</TD></TR> |
<TR><TD><TH align=right>8</TH><TD>Bus Timer (A Zip Timer, just on the bus)</TD></TR> |
<TR><TD><TH align=right>9-14</TH><TD>(Unused / reserved)</TD></TR> |
</TABLE> |
</BODY></HTML> |