URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/rtl/cpu
- from Rev 45 to Rev 46
- ↔ Reverse comparison
Rev 45 → Rev 46
/cpudefs.v
1,3 → 1,4
`define XULA25 |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpudefs.v |
/cpuops.v
96,6 → 96,7
// the Xilinx multiplexer fabric that follows. |
// Given that we wish to apply this multiplexer approach to 33-bits, |
// this will cost a minimum of 132 6-LUTs. |
wire w_illegal; |
generate |
if (IMPLEMENT_MPY == 0) |
begin |
126,9 → 127,10
|
assign o_busy = 1'b0; |
|
assign w_illegal = (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4)); |
reg r_illegal; |
always @(posedge i_clk) |
r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4)); |
r_illegal <= w_illegal; |
assign o_illegal = r_illegal; |
end else begin |
// |
181,6 → 183,7
|
assign o_busy = r_busy; |
|
assign w_illegal = 1'b0; |
assign o_illegal = 1'b0; |
end endgenerate |
|
195,6 → 198,6
if (i_rst) |
o_valid <= 1'b0; |
else |
o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5) |
o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)&&(~w_illegal) |
||(o_busy); |
endmodule |
/zipcpu.v
1045,8 → 1045,20
alu_wr <= 1'b0; |
alF_wr <= 1'b0; |
end else if (alu_ce) |
`ifdef OPT_ILLEGAL_INSTRUCTION |
begin |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond)&&(~op_illegal); |
alF_wr <= (opF_wr)&&(set_cond); |
end else if (~alu_busy) begin |
// These are strobe signals, so clear them if not |
// set for any particular clock |
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
end |
`else |
begin |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond); |
alF_wr <= (opF_wr)&&(set_cond); |
end else if (~alu_busy) begin |
1055,6 → 1067,7
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
end |
`endif |
|
`ifdef OPT_VLIW |
reg r_alu_phase; |
1091,6 → 1104,7
alu_pc <= op_pc; |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
/* |
reg r_alu_illegal; |
initial r_alu_illegal = 0; |
always @(posedge i_clk) |
1098,7 → 1112,9
r_alu_illegal <= 1'b0; |
else if ((alu_ce)||(mem_ce)) |
r_alu_illegal <= op_illegal; |
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal); |
||(r_alu_illegal); |
*/ |
assign alu_illegal = (alu_illegal_op); |
`endif |
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only |
1187,8 → 1203,7
// Further, alu_wr includes (set_cond), so we don't need to |
// check for that here either. |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (~alu_illegal)&& |
(((alu_wr)&&(~clear_pipeline) |
assign wr_reg_ce = (((alu_wr)&&(~clear_pipeline) |
&&((alu_valid)||(div_valid)||(fpu_valid))) |
||(mem_valid)); |
`else |