OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk/rtl/cpu
    from Rev 46 to Rev 50
    ↔ Reverse comparison
  •

Rev 46 → Rev 50

/pfcache.v
91,18 → 91,13
 
initial tagval = 0;
always @(posedge i_clk)
if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
&&(i_wb_ack)&&(~i_wb_err))
// Our tag value changes any time we finish reading a
// new cache line
tagval <= o_wb_addr[(AW-1):CW];
else if ((i_stall_n)&&(~o_wb_cyc))
// Otherwise, as long as we're not reading new stuff,
// the tag line changes any time the pipeline steps
// forwards. Our purpose here is primarily just to
// catch sudden changes. The result is that walking
// from one cache line to the next will cost a clock.
tagval <= tags[i_pc[(CW-1):PW]];
// It may be possible to recover a clock once the cache line
// has been filled, but our prior attempt to do so has lead
// to a race condition, so we keep this logic simple.
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
lastpc <= tags[i_pc[(CW-1):PW]];
else
tagval <= tags[lastpc[(CW-1):PW]];
 
// i_pc will only increment when everything else isn't stalled, thus
// we can set it without worrying about that. Doing this enables
202,10 → 197,12
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
vmask <= 0;
else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
vmask[lastpc[(CW-1):PW]] <= 1'b0;
else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
else begin
if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
vmask[lastpc[(CW-1):PW]] <= 1'b0;
end
 
reg illegal_valid;
initial illegal_cache = 0;
/idecode.v
98,16 → 98,9
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
wire w_wR, w_rA, w_rB, w_wR_n;
wire w_ljmp;
wire [31:0] iword;
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
wire [31:0] iword;
`ifdef OPT_VLIW
reg [16:0] r_nxt_half;
assign iword = (o_phase)
119,6 → 112,14
assign iword = { 1'b0, i_instruction[30:0] };
`endif
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
assign w_op= iword[26:22];
assign w_mov = (w_op == 5'h0f);
assign w_ldi = (w_op[4:1] == 4'hb);
/zipcpu.v
1045,20 → 1045,8
alu_wr <= 1'b0;
alF_wr <= 1'b0;
end else if (alu_ce)
`ifdef OPT_ILLEGAL_INSTRUCTION
begin
// alu_reg <= opR;
alu_wr <= (opR_wr)&&(set_cond)&&(~op_illegal);
alF_wr <= (opF_wr)&&(set_cond);
end else if (~alu_busy) begin
// These are strobe signals, so clear them if not
// set for any particular clock
alu_wr <= (i_halt)&&(i_dbg_we);
alF_wr <= 1'b0;
end
`else
begin
// alu_reg <= opR;
alu_wr <= (opR_wr)&&(set_cond);
alF_wr <= (opF_wr)&&(set_cond);
end else if (~alu_busy) begin
1067,7 → 1055,6
alu_wr <= (i_halt)&&(i_dbg_we);
alF_wr <= 1'b0;
end
`endif
 
`ifdef OPT_VLIW
reg r_alu_phase;
1104,7 → 1091,6
alu_pc <= op_pc;
 
`ifdef OPT_ILLEGAL_INSTRUCTION
/*
reg r_alu_illegal;
initial r_alu_illegal = 0;
always @(posedge i_clk)
1112,9 → 1098,7
r_alu_illegal <= 1'b0;
else if ((alu_ce)||(mem_ce))
r_alu_illegal <= op_illegal;
||(r_alu_illegal);
*/
assign alu_illegal = (alu_illegal_op);
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
`endif
 
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
1203,7 → 1187,8
// Further, alu_wr includes (set_cond), so we don't need to
// check for that here either.
`ifdef OPT_ILLEGAL_INSTRUCTION
assign wr_reg_ce = (((alu_wr)&&(~clear_pipeline)
assign wr_reg_ce = (~alu_illegal)&&
(((alu_wr)&&(~clear_pipeline)
&&((alu_valid)||(div_valid)||(fpu_valid)))
||(mem_valid));
`else
1294,7 → 1279,9
assign o_break = (((break_en)||(~op_gie))&&(op_break)
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
&&(~clear_pipeline))
||((~alu_gie)&&(bus_err));
||((~alu_gie)&&(bus_err))
||((~alu_gie)&&(div_valid)&&(div_error))
||((~alu_gie)&&(fpu_valid)&&(fpu_error));
`endif
 
 
1647,7 → 1634,7
`ifdef DEBUG_SCOPE
always @(posedge i_clk)
o_debug <= {
pf_pc[3:0], flags,
i_wb_err, pf_pc[2:0], flags,
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
op_ce, alu_ce, mem_ce,
//

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.