URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/rtl/cpu
- from Rev 67 to Rev 68
- ↔ Reverse comparison
Rev 67 → Rev 68
/zipsystem.v
173,7 → 173,7
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24, |
LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1, |
`ifdef OPT_MULTIPLY |
IMPLEMENT_MPY = 1, |
IMPLEMENT_MPY = `OPT_MULTIPLY, |
`else |
IMPLEMENT_MPY = 0, |
`endif |
369,7 → 369,8
// |
wire wdt_ack, wdt_stall, wdt_reset; |
wire [31:0] wdt_data; |
ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt, |
ziptimer #(32,31,0) |
watchdog(i_clk, cpu_reset, ~cmd_halt, |
sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we, |
sys_data, |
wdt_ack, wdt_stall, wdt_data, wdt_reset); |
523,7 → 524,7
wire cpu_gbl_cyc; |
assign dmac_stb = (sys_stb)&&(sys_addr[4]); |
`ifdef INCLUDE_DMA_CONTROLLER |
wbdmac #(AW) dma_controller(i_clk, |
wbdmac #(AW) dma_controller(i_clk, cpu_reset, |
sys_cyc, dmac_stb, sys_we, |
sys_addr[1:0], sys_data, |
dmac_ack, dmac_stall, dmac_data, |
535,12 → 536,6
main_int_vector[14:1], 1'b0 }, |
// DMAC interrupt, for upon completion |
dmac_int); |
// Whether or not the CPU wants the bus, and |
// thus we must kick the DMAC off. |
// However, the logic required for this |
// override never worked well, so here |
// we just don't use it. |
// cpu_gbl_cyc); |
`else |
reg r_dmac_ack; |
always @(posedge i_clk) |
677,8 → 672,15
wire [31:0] cpu_dbg_data; |
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5]) |
&&(dbg_we)&&(dbg_addr)); |
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE, IMPLEMENT_MPY, |
IMPLEMENT_DIVIDE, IMPLEMENT_FPU, IMPLEMENT_LOCK) |
zipcpu #( |
.RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ADDRESS_WIDTH), |
.LGICACHE(LGICACHE), |
.IMPLEMENT_MPY(IMPLEMENT_MPY), |
.IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE), |
.IMPLEMENT_FPU(IMPLEMENT_FPU), |
.IMPLEMENT_LOCK(IMPLEMENT_LOCK) |
) |
thecpu(i_clk, cpu_reset, pic_interrupt, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
dbg_idata, cpu_dbg_stall, cpu_dbg_data, |
726,7 → 728,7
:((~cmd_addr[5])?cpu_dbg_data : wb_data); |
initial dbg_ack = 1'b0; |
always @(posedge i_clk) |
dbg_ack <= (dbg_cyc)&&(~dbg_stall); |
dbg_ack <= (dbg_cyc)&&(dbg_stb)&&(~dbg_stall); |
assign dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr); |
|
// Now for the external wishbone bus |