URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/rtl
- from Rev 100 to Rev 101
- ↔ Reverse comparison
Rev 100 → Rev 101
/busmaster.v
47,7 → 47,16
// What innate capabilities are built into the board? |
// |
`define INCLUDE_ZIPCPU |
// `define NO_ZIP_WBU_DELAY |
|
// Without the ZipCPU competing for the bus, we don't need to delay it by a |
// cycle. |
`ifndef INCLUDE_ZIPCPU |
`define NO_ZIP_WBU_DELAY |
`endif |
`ifdef VERILATOR |
`define NO_ZIP_WBU_DELAY |
`endif |
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`define IMPLEMENT_ONCHIP_RAM |
`ifndef VERILATOR |
`ifndef XULA25 |
167,6 → 176,7
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall; |
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24])); |
wire [31:0] zip_dbg_data; |
wire wbu_dbg; |
wbubus genbus(i_clk, i_rx_stb, i_rx_data, |
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data, |
`ifdef INCLUDE_ZIPCPU |
180,7 → 190,8
wbu_err, dwb_idata, |
`endif |
w_interrupt, |
o_tx_stb, o_tx_data, i_tx_busy); |
o_tx_stb, o_tx_data, i_tx_busy, |
wbu_dbg); |
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// |
199,7 → 210,7
`ifdef INCLUDE_ZIPCPU |
`ifdef XULA25 |
wire [31:0] zip_debug; |
zipsystem #(24'h2000,ZA,8,1,9) |
zipsystem #(24'h2000,ZA,9,1,9) |
zippy(i_clk, 1'b0, |
// Zippys wishbone interface |
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data, |
261,7 → 272,32
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, |
dwb_ack, dwb_stall, dwb_err); |
|
// |
// |
// And because the ZIP CPU and the Arbiter create an unacceptable |
// delay, we fail timing. So we add in a delay cycle ... |
// |
// |
`ifdef NO_ZIP_WBU_DELAY |
assign wb_cyc = dwb_cyc; |
assign wb_stb = dwb_stb; |
assign wb_we = dwb_we; |
assign wb_addr = dwb_addr; |
assign wb_data = dwb_odata; |
assign dwb_idata = wb_idata; |
assign dwb_ack = wb_ack; |
assign dwb_stall = wb_stall; |
assign dwb_err = wb_err; |
`else |
busdelay wbu_zip_delay(i_clk, |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, |
dwb_ack, dwb_stall, dwb_idata, dwb_err, |
wb_cyc, wb_stb, wb_we, wb_addr, wb_data, |
wb_ack, wb_stall, wb_idata, wb_err); |
`endif |
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`else // if no ZIP_CPU |
assign zip_cyc = 1'b0; |
assign zip_stb = 1'b0; |
assign zip_we = 1'b0; |
289,32 → 325,7
`endif |
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// |
// |
// And because the ZIP CPU and the Arbiter create an unacceptable |
// delay, we fail timing. So we add in a delay cycle ... |
// |
// |
`ifdef NO_ZIP_WBU_DELAY |
assign wb_cyc = dwb_cyc; |
assign wb_stb = dwb_stb; |
assign wb_we = dwb_we; |
assign wb_addr = dwb_addr; |
assign wb_data = dwb_odata; |
assign dwb_idata = wb_idata; |
assign dwb_ack = wb_ack; |
assign dwb_stall = wb_stall; |
assign dwb_err = wb_err; |
`else |
busdelay wbu_zip_delay(i_clk, |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, |
dwb_ack, dwb_stall, dwb_idata, dwb_err, |
wb_cyc, wb_stb, wb_we, wb_addr, wb_data, |
wb_ack, wb_stall, wb_idata, wb_err); |
`endif |
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wire io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel, |
cfg_sel, mem_sel, sdram_sel, sdcard_sel, |
none_sel, many_sel, io_bank; |
475,13 → 486,12
`ifdef XULA25 |
wbpwmaudio #(16'd1813,1) // 44.1 kHz, user adjustable |
`else |
wbpwmaudio #(16'h2710,0,16) // 8 kHz, fixed audio rate |
wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate |
`endif |
pwmdev(i_clk, |
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0], |
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int); |
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// |
// FLASH MEMORY CONFIGURATION ACCESS |