URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
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- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/rtl
- from Rev 108 to Rev 109
- ↔ Reverse comparison
Rev 108 → Rev 109
/wbudecompress.v
2,7 → 2,7
// |
// Filename: wbudecompress.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Compression via this interface is simply a lookup table. |
// When writing, if requested, rather than writing a new 36-bit |
17,7 → 17,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
94,7 → 94,7
if (~r_word[34]) |
rd_len <= 10'h01 + { 6'h00, r_word[33:31] }; |
else |
rd_len <= 10'h08 + { 1'b0, r_word[33:31], r_word[29:24] }; |
rd_len <= 10'h09 + { 1'b0, r_word[33:31], r_word[29:24] }; |
|
// Clock three, read the table value |
// { o_stb, r_stb } = 4'h4 when done |
/wbuexec.v
2,7 → 2,7
// |
// Filename: wbuexec.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: This is the part of the USB-JTAG to wishbone conversion that |
// actually conducts a wishbone transaction. Transactions are |
52,7 → 52,8
input [35:0] i_codword; |
output wire o_busy; |
// Wishbone outputs |
output wire o_wb_cyc, o_wb_stb; |
output reg o_wb_cyc; |
output reg o_wb_stb; |
output reg o_wb_we; |
output reg [31:0] o_wb_addr, o_wb_data; |
// Wishbone inputs |
79,6 → 80,7
reg [2:0] wb_state; |
reg [9:0] r_acks_needed, r_len; |
reg r_inc, r_new_addr, last_read_request, last_ack, zero_acks; |
reg single_read_request; |
|
initial r_new_addr = 1'b1; |
initial wb_state = `WB_IDLE; |
88,9 → 90,13
begin |
wb_state <= `WB_IDLE; |
o_stb <= 1'b1; |
o_codword <= { 6'h3, i_wb_data[29:0] }; |
o_codword <= { 6'h3, i_wb_data[29:0] }; // BUS Reset |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else case(wb_state) |
`WB_IDLE: begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
// Now output codewords while we're idle, |
// ... unless we get an address command (later). |
o_stb <= 1'b0; |
127,18 → 133,21
// |
casez(i_codword[35:32]) |
4'b0000: begin // Set a new (arbitrary) address |
r_new_addr <= 1'b1; |
o_wb_addr <= i_codword[31:0]; |
// r_new_addr <= 1'b1; |
o_wb_addr <= i_codword[31:0]; //w_cod_data |
end |
4'b001?: begin // Set a new relative address |
r_new_addr <= 1'b1; |
o_wb_addr <= o_wb_addr |
// r_new_addr <= 1'b1; |
o_wb_addr <= o_wb_addr // + w_cod_data; |
|
+ { i_codword[32:31], i_codword[29:0] }; |
end |
4'b01??: begin // Start a write transaction, |
// address is alrdy set |
r_new_addr <= 1'b1; |
// r_new_addr <= 1'b1; |
wb_state <= `WB_WRITE_REQUEST; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
end |
4'b11??: begin // Start a vector read |
// Address is already set ... |
146,6 → 155,8
if (r_new_addr) |
o_stb <= 1'b1; |
wb_state <= `WB_READ_REQUEST; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
end |
default: |
; |
152,7 → 163,8
endcase |
end end |
`WB_READ_REQUEST: begin |
r_new_addr <= 1'b0; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
|
if (i_wb_err) |
wb_state <= `WB_IDLE; |
159,9 → 171,9
|
o_stb <= (i_wb_err)||(i_wb_ack); |
|
if (i_wb_err) |
if (i_wb_err) // Bus Error |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
else |
else // Read data on ack |
o_codword <= { 3'h7, i_wb_data[31:30], r_inc, |
i_wb_data[29:0] }; |
|
171,15 → 183,20
|
if (~i_wb_stall) // Deal with the strobe line |
begin // Strobe was accepted, busy should be '1' here |
if (last_read_request) // (r_len != 0) // read |
if ((single_read_request)||(last_read_request)) // (r_len != 0) // read |
begin |
wb_state <= `WB_ACK; |
o_wb_stb <= 1'b0; |
end |
end end |
`WB_WRITE_REQUEST: begin |
r_new_addr <= 1'b0; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
// |
|
if (i_wb_err) |
if (i_wb_err) // Bus Err |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
else |
else // Write acknowledgement |
o_codword <= { 6'h2, i_wb_data[29:0] }; |
|
if ((r_inc)&&(~i_wb_stall)) |
196,11 → 213,16
begin |
wb_state <= `WB_FLUSH_WRITE_REQUESTS; |
// |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else if (~i_wb_stall) |
begin |
wb_state <= `WB_WAIT_ON_NEXT_WRITE; |
end |
o_wb_stb <= 1'b0; |
end end |
`WB_ACK: begin |
r_new_addr <= 1'b0; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b0; |
// |
// No strobes are being sent out. No further |
// bus transactions are requested. We only need |
208,9 → 230,9
// for (and recording?) their acks. |
// |
// Process acknowledgements |
if (i_wb_err) |
if (i_wb_err) // Bus error |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
else |
else // Read data |
o_codword <= { 3'h7, i_wb_data[31:30], r_inc, |
i_wb_data[29:0] }; |
|
219,22 → 241,33
o_stb <= (((i_wb_ack)&&(~o_wb_we)) || (i_wb_err)); |
|
if (((last_ack)&&(i_wb_ack))||(zero_acks)||(i_wb_err)) |
begin |
o_wb_cyc <= 1'b0; |
wb_state <= `WB_IDLE; |
end |
end end |
`WB_WAIT_ON_NEXT_WRITE: begin |
r_new_addr <= 1'b0; |
|
o_codword <= { 6'h5, i_wb_data[29:0] }; |
o_stb <= (i_wb_err)||(w_new_err); |
|
o_wb_data <= w_cod_data; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b0; |
|
if (w_new_err) // Something other than a write or EOW |
begin |
o_wb_cyc <= 1'b0; |
wb_state <= `WB_IDLE; |
else if (i_wb_err) // Bus returns an error |
end else if (i_wb_err) // Bus returns an error |
begin |
o_wb_cyc <= 1'b0; |
wb_state <= `WB_FLUSH_WRITE_REQUESTS; |
end |
else if (w_newwr) // Need to make a new write request |
begin |
wb_state <= `WB_WRITE_REQUEST; |
o_wb_stb <= 1'b1; |
end |
else if (w_eow) // All done writing, wait for last ack |
wb_state <= `WB_ACK; |
end |
247,8 → 280,9
// In the off chance that we are in here in error, or |
// out of sync, we'll transition to WB_IDLE and just |
// issue a second error token. |
r_new_addr <= 1'b0; |
|
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
o_stb <= (w_new_err); |
|
259,6 → 293,8
o_stb <= 1'b1; |
o_codword <= { 6'h3, i_wb_data[29:0] }; |
wb_state <= `WB_IDLE; |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end |
endcase |
|
265,15 → 301,23
assign o_busy = (wb_state != `WB_IDLE) |
&&(wb_state != `WB_WAIT_ON_NEXT_WRITE) |
&&(wb_state != `WB_FLUSH_WRITE_REQUESTS); |
assign o_wb_cyc = (wb_state == `WB_READ_REQUEST) |
||(wb_state == `WB_WRITE_REQUEST) |
||(wb_state == `WB_ACK) |
||(wb_state == `WB_WAIT_ON_NEXT_WRITE); |
assign o_wb_stb = (wb_state == `WB_READ_REQUEST) |
||(wb_state == `WB_WRITE_REQUEST); |
//assign o_wb_cyc = (wb_state == `WB_READ_REQUEST) |
//||(wb_state == `WB_WRITE_REQUEST) |
//||(wb_state == `WB_ACK) |
//||(wb_state == `WB_WAIT_ON_NEXT_WRITE); |
//assign o_wb_stb = (wb_state == `WB_READ_REQUEST) |
// ||(wb_state == `WB_WRITE_REQUEST); |
|
always @(posedge i_clk) |
if (wb_state == `WB_IDLE) |
if (i_rst) |
r_new_addr <= 1'b1; |
else if ((~o_wb_cyc)&&(i_stb)&&(~i_codword[35])) |
r_new_addr <= 1'b1; |
else if (o_wb_cyc) |
r_new_addr <= 1'b0; |
|
always @(posedge i_clk) |
if (~o_wb_cyc) |
r_acks_needed <= 10'h00; // (i_codword[35])?i_codword[9:0]:10'h00; |
else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) |
r_acks_needed <= r_acks_needed + 10'h01; |
281,18 → 325,26
r_acks_needed <= r_acks_needed - 10'h01; |
|
always @(posedge i_clk) |
last_ack <= (~o_wb_stb)&&(r_acks_needed == 10'h01); |
last_ack <= (~o_wb_stb)&&(r_acks_needed == 10'h01) |
||(o_wb_stb)&&(r_acks_needed == 10'h00); |
|
always @(posedge i_clk) |
zero_acks <= (~o_wb_stb)&&(r_acks_needed == 10'h00); |
|
always @(posedge i_clk) |
if ((wb_state == `WB_IDLE)&&(i_codword[35:34] == 2'b11)) |
r_len <= i_codword[9:0] - 10'h01; |
if (~o_wb_cyc) // &&(i_codword[35:34] == 2'b11)) |
r_len <= i_codword[9:0]; |
else if ((o_wb_stb)&&(~i_wb_stall)&&(|r_len)) |
r_len <= r_len - 10'h01; |
|
always @(posedge i_clk) |
last_read_request <= (r_len[9:0] == 10'h000); |
begin |
single_read_request <= (~o_wb_cyc)&&(i_codword[9:0] == 10'h01); |
// When there is one read request left, it will be the last one |
// will be the last one |
last_read_request <= (o_wb_stb)&&(r_len[9:2] == 8'h00) |
&&((~r_len[1]) |
||((~r_len[0])&&(~i_wb_stall))); |
end |
|
endmodule |
/wbucompress.v
2,7 → 2,7
// |
// Filename: wbucompress.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: When reading many words that are identical, it makes no sense |
// to spend the time transmitting the same thing over and over |
26,7 → 26,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
133,7 → 133,7
// table is full or not. This logic follows: |
// |
reg [(TBITS-1):0] tbl_addr; |
reg r_compressed, tbl_filled; |
reg tbl_filled; |
// First part, write the compression table |
always @(posedge i_clk) |
// If we send a new address, then reset the table to empty |
175,29 → 175,58
// If we find any that matches, we're there. We might (or might not) |
// make it through the table first. That's irrelevant. We just look |
// while we can. |
reg tbl_match, nxt_match; // <= (nxt_rd_addr == tbl_addr); |
reg [(TBITS-1):0] rd_addr; |
wire [(TBITS-1):0] nxt_rd_addr; |
assign nxt_rd_addr = rd_addr - { {(TBITS-1){1'b0}}, 1'b1 }; |
reg [(TBITS-1):0] nxt_rd_addr; |
initial rd_addr = 0; |
initial tbl_match = 0; |
always @(posedge i_clk) |
begin |
nxt_match <= ((nxt_rd_addr-tbl_addr)=={{(TBITS-1){1'b0}},1'b1}); |
if ((w_accepted)||(~a_stb)) |
begin |
// Keep in mind, if a write was just accepted, then |
// rd_addr will need to be reset on the next clock |
// when (~a_stb). Hence this must be a two clock |
// update |
rd_addr <= tbl_addr + {(TBITS){1'b1}}; |
else if ((nxt_rd_addr != tbl_addr)&&(~match) |
nxt_rd_addr = tbl_addr + { {(TBITS-1){1'b1}}, 1'b0 }; |
tbl_match <= 1'b0; |
end else if ((~tbl_match)&&(~match) |
&&((~nxt_rd_addr[TBITS-1])||(tbl_filled))) |
begin |
rd_addr <= nxt_rd_addr; |
nxt_rd_addr = nxt_rd_addr - { {(TBITS-1){1'b0}}, 1'b1 }; |
tbl_match <= nxt_match; |
end |
end |
|
reg [1:0] pmatch; |
reg dmatch, // Match, on clock 'd' |
vaddr; // Was the address valid then? |
reg [(DW-1):0] cword; |
reg [(TBITS-1):0] caddr; |
reg [(TBITS-1):0] caddr, daddr, maddr; |
always @(posedge i_clk) |
begin |
cword <= compression_tbl[rd_addr]; |
caddr <= rd_addr; |
|
dmatch <= (cword == { r_word[32:31], r_word[29:0] }); |
daddr <= caddr; |
maddr <= tbl_addr - caddr; |
|
vaddr <= ( {1'b0, caddr} < {tbl_filled, tbl_addr} ) |
&&(caddr != tbl_addr); |
end |
|
always @(posedge i_clk) |
if ((w_accepted)||(~a_stb)) |
pmatch <= 0; // rd_addr is set on this clock |
else |
// cword is set on the next clock, pmatch = 3'b001 |
// dmatch is set on the next clock, pmatch = 3'b011 |
pmatch <= { pmatch[0], 1'b1 }; |
|
reg match; |
reg [9:0] matchaddr; |
always @(posedge i_clk) |
206,17 → 235,20
else if (~match) |
begin |
// To be a match, the table must not be empty, |
match <= (({1'b0, caddr } < {tbl_filled, tbl_addr})) |
// the word we are matching to must be |
// in the form of a read command |
&&(r_word[35:33] == 3'b111) |
// And the word in the table must be |
// identical to the word we are about |
// to send. |
&&(cword == { r_word[32:31], r_word[29:0] }); |
matchaddr <= tbl_addr-caddr; |
match <= (vaddr)&&(dmatch)&&(r_word[35:33]==3'b111) |
&&(pmatch == 2'b11); |
end |
|
reg zmatch, hmatch, fmatch; |
always @(posedge i_clk) |
if (~match) |
begin |
matchaddr <= maddr; |
fmatch <= (maddr < 10'h521); |
zmatch <= (maddr == 10'h1); |
hmatch <= (maddr < 10'd10); |
end |
|
// Did we find something? |
wire [(TBITS-1):0] adr_diff; |
wire [9:0] adr_dbld; |
224,24 → 256,22
assign adr_diff = matchaddr; |
assign adr_hlfd = matchaddr[2:0]- 3'd2; |
assign adr_dbld = matchaddr- 10'd10; |
initial r_compressed = 1'b0; |
reg [(CW-1):0] r_cword; // Record our result |
always @(posedge i_clk) |
begin |
if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written |
r_compressed <= 1'b0; // to our output |
else if (r_compressed)//Already compressed, wait 'til sent |
; |
else if ((match)&&(matchaddr < 10'd521)) // &&(r_word == a_addrword)) |
begin |
if (matchaddr == 10'h1) |
r_cword <= r_word; |
end else if ((match)&&(fmatch)) // &&(r_word == a_addrword)) |
begin |
r_cword <= r_word; |
if (zmatch) // matchaddr == 1 |
r_cword[35:30] <= { 5'h3, r_word[30] }; |
else if (adr_diff < 10'd10) |
else if (hmatch) // 2 <= matchaddr <= 9 |
r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] }; |
else // if (adr_diff < 10'd521) |
r_cword[35:24] <= { 2'b01, adr_dbld[8:6], |
r_word[30], adr_dbld[5:0] }; |
r_compressed <= 1'b1; |
end else |
r_cword <= r_word; |
end |
248,6 → 278,6
|
// Can we do this without a clock delay? |
assign o_stb = a_stb; |
assign o_cword = (r_compressed)?(r_cword):(a_addrword); |
assign o_cword = (r_stb)?(r_cword):(a_addrword); |
endmodule |
|