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/legal.v
File deleted
/rtclight.v
0,0 → 1,411
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: rtclight.v |
// |
// Project: A Wishbone Controlled Real--time Clock Core |
// |
// Purpose: Implement a real time clock, including alarm, count--down |
// timer, stopwatch, variable time frequency, and more. |
// |
// This is a light-weight version of the RTC found in this directory. |
// Unlike the full RTC, this version does not support time hacks, seven |
// segment display outputs, or LED's. It is an RTC for an internal core |
// only. (That's how I was using it on one of my projects anyway ...) |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
module rtclight(i_clk, |
// Wishbone interface |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
// o_wb_ack, o_wb_stb, o_wb_data, // no reads here |
// // Button inputs |
// i_btn, |
// Output registers |
o_data, // multiplexed based upon i_wb_addr |
// Output controls |
o_interrupt, |
// A once-per-day strobe on the last clock of the day |
o_ppd); |
parameter DEFAULT_SPEED = 32'd2814750; // 100 Mhz |
input i_clk; |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [2:0] i_wb_addr; |
input [31:0] i_wb_data; |
// input i_btn; |
output reg [31:0] o_data; |
output wire o_interrupt, o_ppd; |
|
reg [21:0] clock; |
reg [31:0] stopwatch, ckspeed; |
reg [25:0] timer; |
|
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel; |
assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000)); |
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001)); |
assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010)); |
assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011)); |
assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100)); |
|
reg [39:0] ck_counter; |
reg ck_carry; |
always @(posedge i_clk) |
{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed }; |
|
wire ck_pps; |
reg ck_prepps, ck_ppm, ck_pph, ck_ppd; |
reg [7:0] ck_sub; |
initial clock = 22'h00000; |
assign ck_pps = (ck_carry)&&(ck_prepps); |
always @(posedge i_clk) |
begin |
if (ck_carry) |
ck_sub <= ck_sub + 8'h1; |
ck_prepps <= (ck_sub == 8'hff); |
|
if (ck_pps) |
begin // advance the seconds |
if (clock[3:0] >= 4'h9) |
clock[3:0] <= 4'h0; |
else |
clock[3:0] <= clock[3:0] + 4'h1; |
if (clock[7:0] >= 8'h59) |
clock[7:4] <= 4'h0; |
else if (clock[3:0] >= 4'h9) |
clock[7:4] <= clock[7:4] + 4'h1; |
end |
ck_ppm <= (clock[7:0] == 8'h59); |
|
if ((ck_pps)&&(ck_ppm)) |
begin // advance the minutes |
if (clock[11:8] >= 4'h9) |
clock[11:8] <= 4'h0; |
else |
clock[11:8] <= clock[11:8] + 4'h1; |
if (clock[15:8] >= 8'h59) |
clock[15:12] <= 4'h0; |
else if (clock[11:8] >= 4'h9) |
clock[15:12] <= clock[15:12] + 4'h1; |
end |
ck_pph <= (clock[15:0] == 16'h5959); |
|
if ((ck_pps)&&(ck_pph)) |
begin // advance the hours |
if (clock[21:16] >= 6'h23) |
begin |
clock[19:16] <= 4'h0; |
clock[21:20] <= 2'h0; |
end else if (clock[19:16] >= 4'h9) |
begin |
clock[19:16] <= 4'h0; |
clock[21:20] <= clock[21:20] + 2'h1; |
end else begin |
clock[19:16] <= clock[19:16] + 4'h1; |
end |
end |
ck_ppd <= (clock[21:0] == 22'h235959); |
|
|
if ((ck_sel)&&(i_wb_we)) |
begin |
if (8'hff != i_wb_data[7:0]) |
begin |
clock[7:0] <= i_wb_data[7:0]; |
ck_ppm <= (i_wb_data[7:0] == 8'h59); |
end |
if (8'hff != i_wb_data[15:8]) |
begin |
clock[15:8] <= i_wb_data[15:8]; |
ck_pph <= (i_wb_data[15:8] == 8'h59); |
end |
if (6'h3f != i_wb_data[21:16]) |
clock[21:16] <= i_wb_data[21:16]; |
if (8'h00 == i_wb_data[7:0]) |
ck_sub <= 8'h00; |
end |
end |
|
// Clock updates take several clocks, so let's make sure we |
// are only looking at a valid clock value before testing it. |
reg [21:0] ck_last_clock; |
always @(posedge i_clk) |
ck_last_clock <= clock[21:0]; |
|
|
reg tm_pps, tm_ppm, tm_int; |
wire tm_stopped, tm_running, tm_alarm; |
assign tm_stopped = ~timer[24]; |
assign tm_running = timer[24]; |
assign tm_alarm = timer[25]; |
reg [23:0] tm_start; |
reg [7:0] tm_sub; |
initial tm_start = 24'h00; |
initial timer = 26'h00; |
initial tm_int = 1'b0; |
initial tm_pps = 1'b0; |
always @(posedge i_clk) |
begin |
if (ck_carry) |
begin |
tm_sub <= tm_sub + 8'h1; |
tm_pps <= (tm_sub == 8'hff); |
end else |
tm_pps <= 1'b0; |
|
if ((~tm_alarm)&&(tm_running)&&(tm_pps)) |
begin // If we are running ... |
timer[25] <= 1'b0; |
if (timer[23:0] == 24'h00) |
timer[25] <= 1'b1; |
else if (timer[3:0] != 4'h0) |
timer[3:0] <= timer[3:0]-4'h1; |
else begin // last digit is a zero |
timer[3:0] <= 4'h9; |
if (timer[7:4] != 4'h0) |
timer[7:4] <= timer[7:4]-4'h1; |
else begin // last two digits are zero |
timer[7:4] <= 4'h5; |
if (timer[11:8] != 4'h0) |
timer[11:8] <= timer[11:8]-4'h1; |
else begin // last three digits are zero |
timer[11:8] <= 4'h9; |
if (timer[15:12] != 4'h0) |
timer[15:12] <= timer[15:12]-4'h1; |
else begin |
timer[15:12] <= 4'h5; |
if (timer[19:16] != 4'h0) |
timer[19:16] <= timer[19:16]-4'h1; |
else begin |
// |
timer[19:16] <= 4'h9; |
timer[23:20] <= timer[23:20]-4'h1; |
end |
end |
end |
end |
end |
end |
|
if((~tm_alarm)&&(tm_running)) |
begin |
timer[25] <= (timer[23:0] == 24'h00); |
tm_int <= (timer[23:0] == 24'h00); |
end else tm_int <= 1'b0; |
if (tm_alarm) |
timer[24] <= 1'b0; |
|
if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running |
// Only allowed to stop the timer, nothing more |
timer[24] <= i_wb_data[24]; |
else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off |
begin |
timer[24] <= i_wb_data[24]; |
if ((timer[24])||(i_wb_data[24])) |
timer[25] <= 1'b0; |
if (i_wb_data[23:0] != 24'h0000) |
begin |
timer[23:0] <= i_wb_data[23:0]; |
tm_start <= i_wb_data[23:0]; |
tm_sub <= 8'h00; |
end else if (timer[23:0] == 24'h00) |
begin // Resetting timer to last valid timer start val |
timer[23:0] <= tm_start; |
tm_sub <= 8'h00; |
end |
// Any write clears the alarm |
timer[25] <= 1'b0; |
end |
end |
|
// |
// Stopwatch functionality |
// |
// Setting bit '0' starts the stop watch, clearing it stops it. |
// Writing to the register with bit '1' high will clear the stopwatch, |
// and return it to zero provided that the stopwatch is stopped either |
// before or after the write. Hence, writing a '2' to the device |
// will always stop and clear it, whereas writing a '3' to the device |
// will only clear it if it was already stopped. |
reg sw_pps, sw_ppm, sw_pph; |
reg [7:0] sw_sub; |
wire sw_running; |
assign sw_running = stopwatch[0]; |
initial stopwatch = 32'h00000; |
always @(posedge i_clk) |
begin |
sw_pps <= 1'b0; |
if (sw_running) |
begin |
if (ck_carry) |
begin |
sw_sub <= sw_sub + 8'h1; |
sw_pps <= (sw_sub == 8'hff); |
end |
end |
|
stopwatch[7:1] <= sw_sub[7:1]; |
|
if (sw_pps) |
begin // Second hand |
if (stopwatch[11:8] >= 4'h9) |
stopwatch[11:8] <= 4'h0; |
else |
stopwatch[11:8] <= stopwatch[11:8] + 4'h1; |
|
if (stopwatch[15:8] >= 8'h59) |
stopwatch[15:12] <= 4'h0; |
else if (stopwatch[11:8] >= 4'h9) |
stopwatch[15:12] <= stopwatch[15:12] + 4'h1; |
sw_ppm <= (stopwatch[15:8] == 8'h59); |
end else sw_ppm <= 1'b0; |
|
if (sw_ppm) |
begin // Minutes |
if (stopwatch[19:16] >= 4'h9) |
stopwatch[19:16] <= 4'h0; |
else |
stopwatch[19:16] <= stopwatch[19:16]+4'h1; |
|
if (stopwatch[23:16] >= 8'h59) |
stopwatch[23:20] <= 4'h0; |
else if (stopwatch[19:16] >= 4'h9) |
stopwatch[23:20] <= stopwatch[23:20]+4'h1; |
sw_pph <= (stopwatch[23:16] == 8'h59); |
end else sw_pph <= 1'b0; |
|
if (sw_pph) |
begin // And hours |
if (stopwatch[27:24] >= 4'h9) |
stopwatch[27:24] <= 4'h0; |
else |
stopwatch[27:24] <= stopwatch[27:24]+4'h1; |
|
if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf)) |
stopwatch[31:28] <= stopwatch[27:24]+4'h1; |
end |
|
if ((sw_sel)&&(i_wb_we)) |
begin |
stopwatch[0] <= i_wb_data[0]; |
if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0]))) |
begin |
stopwatch[31:1] <= 31'h00; |
sw_sub <= 8'h00; |
sw_pps <= 1'b0; |
sw_ppm <= 1'b0; |
sw_pph <= 1'b0; |
end |
end |
end |
|
// |
// The alarm code |
// |
// Set the alarm register to the time you wish the board to "alarm". |
// The "alarm" will take place once per day at that time. At that |
// time, the RTC code will generate a clock interrupt, and the CPU/host |
// can come and see that the alarm tripped. |
// |
// |
reg [21:0] alarm_time; |
reg al_int, // The alarm interrupt line |
al_enabled, // Whether the alarm is enabled |
al_tripped; // Whether the alarm has tripped |
initial al_enabled= 1'b0; |
initial al_tripped= 1'b0; |
always @(posedge i_clk) |
begin |
if ((al_sel)&&(i_wb_we)) |
begin |
// Only adjust the alarm hours if the requested hours |
// are valid. This allows writes to the register, |
// without a prior read, to leave these configuration |
// bits alone. |
if (i_wb_data[21:16] != 6'h3f) |
alarm_time[21:16] <= i_wb_data[21:16]; |
// Here's the same thing for the minutes: only adjust |
// the alarm minutes if the new bits are not all 1's. |
if (i_wb_data[15:8] != 8'hff) |
alarm_time[15:8] <= i_wb_data[15:8]; |
// Here's the same thing for the seconds: only adjust |
// the alarm minutes if the new bits are not all 1's. |
if (i_wb_data[7:0] != 8'hff) |
alarm_time[7:0] <= i_wb_data[7:0]; |
al_enabled <= i_wb_data[24]; |
// Reset the alarm if a '1' is written to the tripped |
// register, or if the alarm is disabled. |
if ((i_wb_data[25])||(~i_wb_data[24])) |
al_tripped <= 1'b0; |
end |
|
al_int <= 1'b0; |
if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time) |
&&(al_enabled)) |
begin |
al_tripped <= 1'b1; |
al_int <= 1'b1; |
end |
end |
|
// |
// The ckspeed register is equal to 2^48 divded by the number of |
// clock ticks you expect per second. Adjust high for a slower |
// clock, lower for a faster clock. In this fashion, a single |
// real time clock RTL file can handle tracking the clock in any |
// device. Further, because this is only the lower 32 bits of a |
// 48 bit counter per seconds, the clock jitter is kept below |
// 1 part in 65 thousand. |
// |
initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz |
// In the case of verilator, comment the above and uncomment the line |
// below. The clock constant below is "close" to simulation time, |
// meaning that my verilator simulation is running about 300x slower |
// than board time. |
// initial ckspeed = 32'd786432000; |
always @(posedge i_clk) |
if ((sp_sel)&&(i_wb_we)) |
ckspeed <= i_wb_data; |
|
assign o_interrupt = tm_int || al_int; |
|
// A once-per day strobe, on the last second of the day so that the |
// the next clock is the first clock of the day. This is useful for |
// connecting this module to a year/month/date date/calendar module. |
assign o_ppd = (ck_ppd)&&(ck_pps); |
|
always @(posedge i_clk) |
case(i_wb_addr[2:0]) |
3'b000: o_data <= { 10'h0, ck_last_clock }; |
3'b001: o_data <= { 6'h00, timer }; |
3'b010: o_data <= stopwatch; |
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time }; |
3'b100: o_data <= ckspeed; |
default: o_data <= 32'h000; |
endcase |
|
endmodule |
/cpu/wbarbiter.v
0,0 → 1,184
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbarbiter.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: At some point in time, I might wish to have two masters connect |
// to the same wishbone bus. As an example, I might wish to have |
// both the instruction fetch and the load/store operators |
// of my Zip CPU access the the same bus. How shall they both |
// get access to the same resource? This module allows the |
// wishbone interfaces from two sources to drive the bus, while |
// guaranteeing that only one drives the bus at a time. |
// |
// The core logic works like this: |
// |
// 1. If 'A' or 'B' asserts the o_cyc line, a bus cycle will begin, |
// with acccess granted to whomever requested it. |
// 2. If both 'A' and 'B' assert o_cyc at the same time, only 'A' |
// will be granted the bus. (If the alternating parameter |
// is set, A and B will alternate who gets the bus in |
// this case.) |
// 3. The bus will remain owned by whomever the bus was granted to |
// until they deassert the o_cyc line. |
// 4. At the end of a bus cycle, o_cyc is guaranteed to be |
// deasserted (low) for one clock. |
// 5. On the next clock, bus arbitration takes place again. If |
// 'A' requests the bus, no matter how long 'B' was |
// waiting, 'A' will then be granted the bus. (Unless |
// again the alternating parameter is set, then the |
// access is guaranteed to switch to B.) |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
`define WBA_ALTERNATING |
module wbarbiter(i_clk, i_rst, |
// Bus A |
i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err); |
// 18 bits will address one GB, 4 bytes at a time. |
// 19 bits will allow the ability to address things other than just |
// the 1GB of memory we are expecting. |
parameter DW=32, AW=19; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
// what it would (might) do to the synchronous reset signal, i_rst. |
input i_clk, i_rst; |
input [(AW-1):0] i_a_adr, i_b_adr; |
input [(DW-1):0] i_a_dat, i_b_dat; |
input i_a_we, i_a_stb, i_a_cyc; |
input i_b_we, i_b_stb, i_b_cyc; |
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall, |
o_a_err, o_b_err; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire o_we, o_stb, o_cyc; |
input i_ack, i_stall, i_err; |
|
// All the fancy stuff here is done with the three primary signals: |
// o_cyc |
// w_a_owner |
// w_b_owner |
// These signals are helped by r_cyc, r_a_owner, and r_b_owner. |
// If you understand these signals, all else will fall into place. |
|
// r_cyc just keeps track of the last o_cyc value. That way, on |
// the next clock we can tell if we've had one non-cycle before |
// starting another cycle. Specifically, no new cycles will be |
// allowed to begin unless r_cyc=0. |
reg r_cyc; |
always @(posedge i_clk) |
if (i_rst) |
r_cyc <= 1'b0; |
else |
r_cyc <= o_cyc; |
|
// Go high immediately (new cycle) if ... |
// Previous cycle was low and *someone* is requesting a bus cycle |
// Go low immadiately if ... |
// We were just high and the owner no longer wants the bus |
// WISHBONE Spec recommends no logic between a FF and the o_cyc |
// This violates that spec. (Rec 3.15, p35) |
assign o_cyc = ((~r_cyc)&&((i_a_cyc)||(i_b_cyc))) || ((r_cyc)&&((w_a_owner)||(w_b_owner))); |
|
|
// Register keeping track of the last owner, wire keeping track of the |
// current owner allowing us to not lose a clock in arbitrating the |
// first clock of the bus cycle |
reg r_a_owner, r_b_owner; |
wire w_a_owner, w_b_owner; |
`ifdef WBA_ALTERNATING |
reg r_a_last_owner; |
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = (w_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (w_b_owner) ? i_stall : 1'b1; |
|
`endif |
always @(posedge i_clk) |
if (i_rst) |
begin |
r_a_owner <= 1'b0; |
r_b_owner <= 1'b0; |
end else begin |
r_a_owner <= w_a_owner; |
r_b_owner <= w_b_owner; |
`ifdef WBA_ALTERNATING |
if (w_a_owner) |
r_a_last_owner <= 1'b1; |
else if (w_b_owner) |
r_a_last_owner <= 1'b0; |
`endif |
end |
// |
// If you are the owner, retain ownership until i_x_cyc is no |
// longer asserted. Likewise, you cannot become owner until o_cyc |
// is de-asserted for one cycle. |
// |
// 'A' is given arbitrary priority over 'B' |
// 'A' may own the bus only if he wants it. When 'A' drops i_a_cyc, |
// o_cyc must drop and so must w_a_owner on the same cycle. |
// However, when 'A' asserts i_a_cyc, he can only capture the bus if |
// it's had an idle cycle. |
// The same is true for 'B' with one exception: if both contend for the |
// bus on the same cycle, 'A' arbitrarily wins. |
`ifdef WBA_ALTERNATING |
assign w_a_owner = (i_a_cyc) // if A requests ownership, and either |
&& ((r_a_owner) // A has already been recognized or |
|| ((~r_cyc) // the bus is free and |
&&((~i_b_cyc) // B has not requested, or if he |
||(~r_a_last_owner)) )); // has, it's A's turn |
assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&((~i_a_cyc)||(r_a_last_owner)) )); |
`else |
assign w_a_owner = (i_a_cyc)&& ((r_a_owner) || (~r_cyc) ); |
assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&(~i_a_cyc)) ); |
`endif |
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat; |
assign o_we = (w_a_owner) ? i_a_we : i_b_we; |
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb); |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
// low if the particular master doesn't own the bus. |
assign o_a_ack = (w_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (w_b_owner) ? i_ack : 1'b0; |
|
// |
// |
assign o_a_err = (w_a_owner) ? i_err : 1'b0; |
assign o_b_err = (w_b_owner) ? i_err : 1'b0; |
|
endmodule |
|
/cpu/div.v
0,0 → 1,134
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: div.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Provide an Integer divide capability to the Zip CPU. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// `include "cpudefs.v" |
// |
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator, |
o_busy, o_valid, o_err, o_quotient, o_flags); |
parameter BW=32, LGBW = 5; |
input i_clk, i_rst; |
// Input parameters |
input i_wr, i_signed; |
input [(BW-1):0] i_numerator, i_denominator; |
// Output parameters |
output reg o_busy, o_valid, o_err; |
output reg [(BW-1):0] o_quotient; |
output wire [3:0] o_flags; |
|
reg [(2*BW-2):0] r_divisor; |
reg [(BW-1):0] r_dividend; |
wire [(BW):0] diff; // , xdiff[(BW-1):0]; |
assign diff = r_dividend - r_divisor[(BW-1):0]; |
// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] }; |
|
reg r_sign, pre_sign, r_z, r_c; |
reg [(LGBW):0] r_bit; |
|
always @(posedge i_clk) |
if (i_rst) |
begin |
o_busy <= 1'b0; |
end else if (i_wr) |
begin |
o_busy <= 1'b1; |
end else if ((o_busy)&&((r_bit == 6'h0)||(o_err))) |
o_busy <= 1'b0; |
// else busy is zero and stays at zero |
|
always @(posedge i_clk) |
if ((i_rst)||(i_wr)) |
o_valid <= 1'b0; |
else if (o_busy) |
begin |
if ((r_bit == 6'h0)||(o_err)) |
o_valid <= (o_err)||(~r_sign); |
end else if (r_sign) |
begin |
// if (o_err), o_valid is already one. |
// if not, o_valid has not yet become one. |
o_valid <= (~o_err); // 1'b1; |
end else |
o_valid <= 1'b0; |
|
always @(posedge i_clk) |
if((i_rst)||(o_valid)) |
o_err <= 1'b0; |
else if (o_busy) |
o_err <= (r_divisor == 0); |
|
always @(posedge i_clk) |
if (i_wr) |
begin |
o_quotient <= 0; |
// r_bit <= { 1'b1, {(LGBW){1'b0}} }; |
r_bit <= { 1'b0, {(LGBW){1'b1}} }; |
r_divisor <= { i_denominator, {(BW-1){1'b0}} }; |
r_dividend <= i_numerator; |
r_sign <= 1'b0; |
pre_sign <= i_signed; |
r_z <= 1'b1; |
end else if (pre_sign) |
begin |
// r_bit <= r_bit - 1; |
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));; |
if (r_dividend[BW-1]) |
r_dividend <= -r_dividend; |
if (r_divisor[(2*BW-2)]) |
r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)]; |
pre_sign <= 1'b0; |
end else if (o_busy) |
begin |
r_bit <= r_bit + {(LGBW+1){1'b1}}; // r_bit = r_bit - 1; |
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] }; |
if (|r_divisor[(2*BW-2):(BW)]) |
begin |
end else if (diff[BW]) |
begin |
end else begin |
r_dividend <= diff[(BW-1):0]; |
o_quotient[r_bit[(LGBW-1):0]] <= 1'b1; |
r_z <= 1'b0; |
end |
end else if (r_sign) |
begin |
r_sign <= 1'b0; |
o_quotient <= -o_quotient; |
end |
|
// Set Carry on an exact divide |
wire w_n; |
always @(posedge i_clk) |
r_c <= (o_busy)&&((diff == 0)||(r_dividend == 0)); |
assign w_n = o_quotient[(BW-1)]; |
|
assign o_flags = { 1'b0, w_n, r_c, r_z }; |
endmodule |
/cpu/wbwatchdog.v
0,0 → 1,76
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbwatchdog.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: A Zip timer, redesigned to be a bus watchdog |
// |
// This is a **really** stripped down Zip Timer. All options for external |
// control have been removed. This timer may be reset, and ... that's |
// about it. The goal is that this stripped down timer be used as a bus |
// watchdog element. Even at that, it's not really fully featured. The |
// rest of the important features can be found in the zipsystem module. |
// |
// As a historical note, the wishbone watchdog timer began as a normal |
// timer, with some fixed inputs. This makes sense, if you think about it: |
// if the goal is to interrupt a stalled wishbone transaction by inserting |
// a bus error, then you can't use the bus to set it up or configure it |
// simply because the bus in question is ... well, unreliable. You're |
// trying to make it reliable. |
// |
// The problem with using the ziptimer in a stripped down implementation |
// was that the fixed inputs caused the synthesis tool to complain about |
// the use of registers values would never change. This solves that |
// problem by explicitly removing the cruft that would otherwise |
// just create synthesis warnings and errors. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbwatchdog(i_clk, i_rst, i_ce, i_timeout, o_int); |
parameter BW = 32; |
input i_clk, i_rst, i_ce; |
// Inputs (these were at one time wishbone controlled ...) |
input [(BW-1):0] i_timeout; |
// Interrupt line |
output reg o_int; |
|
reg [(BW-1):0] r_value; |
initial r_value = 0; |
always @(posedge i_clk) |
if (i_rst) |
r_value <= i_timeout[(BW-1):0]; |
else if ((i_ce)&&(~o_int)) |
r_value <= r_value + {(BW){1'b1}}; // r_value - 1; |
|
// Set the interrupt on our last tick. |
initial o_int = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(~i_ce)) |
o_int <= 1'b0; |
else |
o_int <= (r_value == { {(BW-1){1'b0}}, 1'b1 }); |
|
endmodule |
/cpu/pfcache.v
0,0 → 1,233
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pfcache.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Keeping our CPU fed with instructions, at one per clock and |
// with no stalls. An unusual feature of this cache is the |
// requirement that the entire cache may be cleared (if necessary). |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache, |
// i_early_branch, i_from_addr, |
i_stall_n, i_pc, o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, |
o_illegal); |
parameter LGCACHELEN = 8, ADDRESS_WIDTH=24, |
CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH, |
CW=LGCACHELEN, PW=LGCACHELEN-5; |
input i_clk, i_rst, i_new_pc; |
input i_clear_cache; |
input i_stall_n; |
input [(AW-1):0] i_pc; |
output reg [(BUSW-1):0] o_i; |
output reg [(AW-1):0] o_pc; |
output wire o_v; |
// |
output reg o_wb_cyc, o_wb_stb; |
output wire o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output wire [(BUSW-1):0] o_wb_data; |
// |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [(BUSW-1):0] i_wb_data; |
// |
output reg o_illegal; |
|
// Fixed bus outputs: we read from the bus only, never write. |
// Thus the output data is ... irrelevant and don't care. We set it |
// to zero just to set it to something. |
assign o_wb_we = 1'b0; |
assign o_wb_data = 0; |
|
reg r_v; |
(* ram_style = "distributed" *) |
reg [(BUSW-1):0] cache [0:((1<<CW)-1)]; |
reg [(AW-CW-1):0] tags [0:((1<<(CW-PW))-1)]; |
reg [((1<<(CW-PW))-1):0] vmask; |
|
reg [(AW-1):0] lastpc; |
reg [(CW-1):0] rdaddr; |
reg [(AW-1):CW] tagval; |
wire [(AW-1):PW] lasttag; |
reg [(AW-1):PW] illegal_cache; |
|
initial o_i = 32'h76_00_00_00; // A NOOP instruction |
initial o_pc = 0; |
always @(posedge i_clk) |
if (~r_v) |
begin |
o_i <= cache[lastpc[(CW-1):0]]; |
o_pc <= lastpc; |
end else if ((i_stall_n)||(i_new_pc)) |
begin |
o_i <= cache[i_pc[(CW-1):0]]; |
o_pc <= i_pc; |
end |
|
initial tagval = 0; |
always @(posedge i_clk) |
if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}) |
&&(i_wb_ack)&&(~i_wb_err)) |
// Our tag value changes any time we finish reading a |
// new cache line |
tagval <= o_wb_addr[(AW-1):CW]; |
else if ((i_stall_n)&&(~o_wb_cyc)) |
// Otherwise, as long as we're not reading new stuff, |
// the tag line changes any time the pipeline steps |
// forwards. Our purpose here is primarily just to |
// catch sudden changes. The result is that walking |
// from one cache line to the next will cost a clock. |
tagval <= tags[i_pc[(CW-1):PW]]; |
|
// i_pc will only increment when everything else isn't stalled, thus |
// we can set it without worrying about that. Doing this enables |
// us to work in spite of stalls. For example, if the next address |
// isn't valid, but the decoder is stalled, get the next address |
// anyway. |
initial lastpc = 0; |
always @(posedge i_clk) |
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc)) |
lastpc <= i_pc; |
|
assign lasttag = lastpc[(AW-1):PW]; |
// initial lasttag = 0; |
// always @(posedge i_clk) |
// if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc)) |
// lasttag <= i_pc[(AW-1):PW]; |
|
wire r_v_from_pc, r_v_from_last; |
assign r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag) |
&&(tagval == i_pc[(AW-1):CW]) |
&&(vmask[i_pc[(CW-1):PW]])); |
assign r_v_from_last = ( |
//(lastpc[(AW-1):PW] == lasttag)&& |
(tagval == lastpc[(AW-1):CW]) |
&&(vmask[lastpc[(CW-1):PW]])); |
|
reg [1:0] delay; |
|
initial delay = 2'h3; |
initial r_v = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n))) |
begin |
r_v <= r_v_from_pc; |
delay <= 2'h2; |
end else if (~r_v) begin // Otherwise, r_v was true and we were |
r_v <= r_v_from_last; // stalled, hence only if ~r_v |
if (o_wb_cyc) |
delay <= 2'h2; |
else if (delay != 0) |
delay <= delay + 2'b11; // i.e. delay -= 1; |
end |
|
assign o_v = (r_v)&&(~i_new_pc); |
|
|
initial o_wb_cyc = 1'b0; |
initial o_wb_stb = 1'b0; |
initial o_wb_addr = {(AW){1'b0}}; |
initial rdaddr = 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else if (o_wb_cyc) |
begin |
if ((o_wb_stb)&&(~i_wb_stall)) |
begin |
if (o_wb_addr[(PW-1):0] == {(PW){1'b1}}) |
o_wb_stb <= 1'b0; |
else |
o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1; |
end |
|
if (i_wb_ack) |
begin |
rdaddr <= rdaddr + 1; |
if (rdaddr[(PW-1):0] == {(PW){1'b1}}) |
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW]; |
end |
|
if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err)) |
o_wb_cyc <= 1'b0; |
|
// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}}) |
// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW]; |
|
end else if ((~r_v)&&(delay==0) |
&&((tagval != lastpc[(AW-1):CW]) |
||(~vmask[lastpc[(CW-1):PW]])) |
&&(~o_illegal)) |
begin |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} }; |
rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} }; |
end |
|
// Can't initialize an array, so leave cache uninitialized |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
cache[rdaddr] <= i_wb_data; |
|
// VMask ... is a section loaded? |
initial vmask = 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
vmask <= 0; |
else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0)) |
vmask[lastpc[(CW-1):PW]] <= 1'b0; |
else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}})) |
vmask[rdaddr[(CW-1):PW]] <= 1'b1; |
|
reg illegal_valid; |
initial illegal_cache = 0; |
initial illegal_valid = 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
begin |
illegal_cache <= 0; |
illegal_valid <= 0; |
end else if ((o_wb_cyc)&&(i_wb_err)) |
begin |
illegal_cache <= lastpc[(AW-1):PW]; |
illegal_valid <= 1'b1; |
end |
|
initial o_illegal = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
o_illegal <= 1'b0; |
else |
o_illegal <= (illegal_valid) |
&&(tagval == i_pc[(AW-1):CW]) |
&&(illegal_cache == i_pc[(AW-1):PW]); |
|
endmodule |
/cpu/icontrol.v
0,0 → 1,153
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: icontrol.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: An interrupt controller, for managing many interrupt sources. |
// |
// This interrupt controller started from the question of how best to |
// design a simple interrupt controller. As such, it has a few nice |
// qualities to it: |
// 1. This is wishbone compliant |
// 2. It sits on a 32-bit wishbone data bus |
// 3. It only consumes one address on that wishbone bus. |
// 4. There is no extra delays associated with reading this |
// device. |
// 5. Common operations can all be done in one clock. |
// |
// So, how shall this be used? First, the 32-bit word is broken down as |
// follows: |
// |
// Bit 31 - This is the global interrupt enable bit. If set, interrupts |
// will be generated and passed on as they come in. |
// Bits 16-30 - These are specific interrupt enable lines. If set, |
// interrupts from source (bit#-16) will be enabled. |
// To set this line and enable interrupts from this source, write |
// to the register with this bit set and the global enable set. |
// To disable this line, write to this register with global enable |
// bit not set, but this bit set. (Writing a zero to any of these |
// bits has no effect, either setting or unsetting them.) |
// Bit 15 - This is the any interrupt pin. If any interrupt is pending, |
// this bit will be set. |
// Bits 0-14 - These are interrupt bits. When set, an interrupt is |
// pending from the corresponding source--regardless of whether |
// it was enabled. (If not enabled, it won't generate an |
// interrupt, but it will still register here.) To clear any |
// of these bits, write a '1' to the corresponding bit. Writing |
// a zero to any of these bits has no effect. |
// |
// The peripheral also sports a parameter, IUSED, which can be set |
// to any value between 1 and (buswidth/2-1, or) 15 inclusive. This will |
// be the number of interrupts handled by this routine. (Without the |
// parameter, Vivado was complaining about unused bits. With it, we can |
// keep the complaints down and still use the routine). |
// |
// To get access to more than 15 interrupts, chain these together, so |
// that one interrupt controller device feeds another. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus, |
i_brd_ints, o_interrupt); |
parameter IUSED = 15; |
input i_clk, i_reset; |
input i_wr; |
input [31:0] i_proc_bus; |
output wire [31:0] o_proc_bus; |
input [(IUSED-1):0] i_brd_ints; |
output wire o_interrupt; |
|
reg [(IUSED-1):0] r_int_state; |
reg [(IUSED-1):0] r_int_enable; |
wire [(IUSED-1):0] nxt_int_state; |
reg r_any, r_interrupt, r_gie; |
|
assign nxt_int_state = (r_int_state|i_brd_ints); |
initial r_int_state = 0; |
always @(posedge i_clk) |
if (i_reset) |
r_int_state <= 0; |
else if (i_wr) |
r_int_state <= nxt_int_state & (~i_proc_bus[(IUSED-1):0]); |
else |
r_int_state <= nxt_int_state; |
initial r_int_enable = 0; |
always @(posedge i_clk) |
if (i_reset) |
r_int_enable <= 0; |
else if ((i_wr)&&(i_proc_bus[31])) |
r_int_enable <= r_int_enable | i_proc_bus[(16+IUSED-1):16]; |
else if ((i_wr)&&(~i_proc_bus[31])) |
r_int_enable <= r_int_enable & (~ i_proc_bus[(16+IUSED-1):16]); |
|
initial r_gie = 1'b0; |
always @(posedge i_clk) |
if (i_reset) |
r_gie <= 1'b0; |
else if (i_wr) |
r_gie <= i_proc_bus[31]; |
|
initial r_any = 1'b0; |
always @(posedge i_clk) |
r_any <= ((r_int_state & r_int_enable) != 0); |
initial r_interrupt = 1'b0; |
always @(posedge i_clk) |
r_interrupt <= r_gie & r_any; |
|
generate |
if (IUSED < 15) |
begin |
assign o_proc_bus = { |
r_gie, { {(15-IUSED){1'b0}}, r_int_enable }, |
r_any, { {(15-IUSED){1'b0}}, r_int_state } }; |
end else begin |
assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state }; |
end endgenerate |
|
/* |
reg int_condition; |
initial int_condition = 1'b0; |
initial o_interrupt_strobe = 1'b0; |
always @(posedge i_clk) |
if (i_reset) |
begin |
int_condition <= 1'b0; |
o_interrupt_strobe <= 1'b0; |
end else if (~r_interrupt) // This might end up generating |
begin // many, many, (wild many) interrupts |
int_condition <= 1'b0; |
o_interrupt_strobe <= 1'b0; |
end else if ((~int_condition)&&(r_interrupt)) |
begin |
int_condition <= 1'b1; |
o_interrupt_strobe <= 1'b1; |
end else |
o_interrupt_strobe <= 1'b0; |
*/ |
|
assign o_interrupt = r_interrupt; |
|
endmodule |
/cpu/wbdblpriarb.v
0,0 → 1,142
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbdblpriarb.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This should almost be identical to the priority arbiter, save |
// for a simple diffence: it allows the arbitration of two |
// separate wishbone buses. The purpose of this is to push the address |
// resolution back one cycle, so that by the first clock visible to this |
// core, it is known which of two parts of the bus the desired address |
// will be on, save that we still use the arbiter since the underlying |
// device doesn't know that there are two wishbone buses. |
// |
// So at this point we've deviated from the WB spec somewhat, by allowing |
// two CYC and two STB lines. Everything else is the same. This allows |
// (in this case the Zip CPU) to determine whether or not the access |
// will be to the local ZipSystem bus or the external WB bus on the clock |
// before the local bus access, otherwise peripherals were needing to do |
// multiple device selection comparisons/test within a clock: 1) is this |
// for the local or external bus, and 2) is this referencing me as a |
// peripheral. This then caused the ZipCPU to fail all timing specs. |
// By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the |
// determination of local vs external can be made one clock earlier |
// where there's still time for the logic, and the second comparison |
// now has time to complete. |
// |
// So let me try to explain this again. To use this arbiter, one of the |
// two masters sets CYC and STB before, only the master determines which |
// of two address spaces the CYC and STB apply to before the clock and |
// only sets the appropriate CYC and STB lines. Then, on the clock tick, |
// the arbiter determines who gets *both* busses, as they both share every |
// other WB line. Thus, only one of CYC_A and CYC_B going out will ever |
// be high at a given time. |
// |
// Hopefully this makes more sense than it sounds. If not, check out the |
// code below for a better explanation. |
// |
// 20150919 -- Added supported for the WB error signal. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbdblpriarb(i_clk, i_rst, |
// Bus A |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, |
i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
// what it would (might) do to the synchronous reset signal, i_rst. |
input i_clk, i_rst; |
// Bus A |
input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
input i_ack, i_stall, i_err; |
|
// All of our logic is really captured in the 'r_a_owner' register. |
// This register determines who owns the bus. If no one is requesting |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// requesting the bus and A is not, then ownership goes to not A on |
// the next clock. (Sounds simple ...) |
// |
// The CYC logic is here to make certain that, by the time we determine |
// who the bus owner is, we can do so based upon determined criteria. |
assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
if (i_rst) |
r_a_owner <= 1'b1; |
else if ((~o_cyc_a)&&(~o_cyc_b)) |
r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1; |
|
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on these various lines are |
// irrelevant. |
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a; |
assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b; |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
// low if the particular master doesn't own the bus. |
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (~r_a_owner) ? i_ack : 1'b0; |
|
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (~r_a_owner) ? i_stall : 1'b1; |
|
// |
// These error lines will be implemented soon, as soon as the rest of |
// the Zip CPU is ready to support them. |
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
|
endmodule |
|
/cpu/wbpriarbiter.v
0,0 → 1,117
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbpriarbiter.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This is a priority bus arbiter. It allows two separate wishbone |
// masters to connect to the same bus, while also guaranteeing |
// that one master can have the bus with no delay any time the |
// other master is not using the bus. The goal is to eliminate |
// the combinatorial logic required in the other wishbone |
// arbiter, while still guarateeing access time for the priority |
// channel. |
// |
// The core logic works like this: |
// |
// 1. When no one requests the bus, 'A' is granted the bus and |
// guaranteed that any access will go right through. |
// 2. If 'B' requests the bus (asserts cyc), and the bus is idle, |
// then 'B' will be granted the bus. |
// 3. Bus grants last as long as the 'cyc' line is high. |
// 4. Once 'cyc' is dropped, the bus returns to 'A' as the owner. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbpriarbiter(i_clk, |
// Bus A |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// |
input i_clk; |
// Bus A |
input i_a_cyc, i_a_stb, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc, i_b_stb, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
output wire o_cyc, o_stb, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
input i_ack, i_stall, i_err; |
|
// Go high immediately (new cycle) if ... |
// Previous cycle was low and *someone* is requesting a bus cycle |
// Go low immadiately if ... |
// We were just high and the owner no longer wants the bus |
// WISHBONE Spec recommends no logic between a FF and the o_cyc |
// This violates that spec. (Rec 3.15, p35) |
assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc; |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
if (~i_b_cyc) |
r_a_owner <= 1'b1; |
else if ((i_b_cyc)&&(~i_a_cyc)) |
r_a_owner <= 1'b0; |
|
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb; |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
// low if the particular master doesn't own the bus. |
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (~r_a_owner) ? i_ack : 1'b0; |
|
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (~r_a_owner) ? i_stall : 1'b1; |
|
// |
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
|
endmodule |
|
/cpu/pipemem.v
0,0 → 1,190
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pipemem.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: A memory unit to support a CPU, this time one supporting |
// pipelined wishbone memory accesses. The goal is to be able |
// to issue one pipelined wishbone access per clock, and (given the memory |
// is fast enough) to be able to read the results back at one access per |
// clock. This renders on-chip memory fast enough to handle single cycle |
// (pipelined) access. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_pipe_stb, i_lock; |
// CPU interface |
input i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
// CPU outputs |
output wire o_busy; |
output wire o_pipe_stalled; |
output reg o_valid; |
output reg o_err; |
output reg [4:0] o_wreg; |
output reg [31:0] o_result; |
// Wishbone outputs |
output wire o_wb_cyc_gbl; |
output reg o_wb_stb_gbl; |
output wire o_wb_cyc_lcl; |
output reg o_wb_stb_lcl, o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
reg [3:0] rdaddr, wraddr; |
wire [3:0] nxt_rdaddr; |
reg [(5-1):0] fifo_oreg [0:15]; |
initial rdaddr = 0; |
initial wraddr = 0; |
always @(posedge i_clk) |
fifo_oreg[wraddr] <= i_oreg; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
wraddr <= 0; |
else if (i_pipe_stb) |
wraddr <= wraddr + 4'h1; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
rdaddr <= 0; |
else if ((i_wb_ack)&&(cyc)) |
rdaddr <= rdaddr + 4'h1; |
assign nxt_rdaddr = rdaddr + 4'h1; |
|
reg cyc; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (~lcl_stb); |
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
initial cyc = 0; |
initial r_wb_cyc_lcl = 0; |
initial r_wb_cyc_gbl = 0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
o_wb_stb_gbl <= 1'b0; |
o_wb_stb_lcl <= 1'b0; |
cyc <= 1'b0; |
end else if (cyc) |
begin |
if ((~i_wb_stall)&&(~i_pipe_stb)) |
begin |
o_wb_stb_gbl <= 1'b0; |
o_wb_stb_lcl <= 1'b0; |
// end else if ((i_pipe_stb)&&(~i_wb_stall)) |
// begin |
// o_wb_addr <= i_addr[(AW-1):0]; |
// o_wb_data <= i_data; |
end |
|
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err)) |
begin |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
cyc <= 1'b0; |
end |
end else if (i_pipe_stb) // New memory operation |
begin // Grab the wishbone |
r_wb_cyc_lcl <= lcl_stb; |
r_wb_cyc_gbl <= gbl_stb; |
o_wb_stb_lcl <= lcl_stb; |
o_wb_stb_gbl <= gbl_stb; |
cyc <= 1'b1; |
// o_wb_addr <= i_addr[(AW-1):0]; |
// o_wb_data <= i_data; |
// o_wb_we <= i_op |
end |
always @(posedge i_clk) |
if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
end else if ((~cyc)&&(i_pipe_stb)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
end |
|
always @(posedge i_clk) |
if ((i_pipe_stb)&&(~cyc)) |
o_wb_we <= i_op; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we); |
initial o_err = 1'b0; |
always @(posedge i_clk) |
o_err <= (cyc)&&(i_wb_err); |
assign o_busy = cyc; |
|
always @(posedge i_clk) |
o_wreg <= fifo_oreg[rdaddr]; |
always @(posedge i_clk) |
if (i_wb_ack) |
o_result <= i_wb_data; |
|
assign o_pipe_stalled = (cyc) |
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl))); |
|
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg lock_gbl, lock_lcl; |
|
initial lock_gbl = 1'b0; |
initial lock_lcl = 1'b0; |
always @(posedge i_clk) |
begin |
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl)); |
end |
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); |
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl); |
|
end else begin |
assign o_wb_cyc_gbl = (r_wb_cyc_gbl); |
assign o_wb_cyc_lcl = (r_wb_cyc_lcl); |
end endgenerate |
|
endmodule |
/cpu/idecode.v
0,0 → 1,405
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: idecode.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This RTL file specifies how instructions are to be decoded |
// into their underlying meanings. This is specifically a version |
// designed to support a "Next Generation", or "Version 2" instruction |
// set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option |
// in cpudefs.v. |
// |
// I expect to (eventually) retire the old instruction set, at which point |
// this will become the default instruction set decoder. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
// |
`include "cpudefs.v" |
// |
// |
// |
module idecode(i_clk, i_rst, i_ce, i_stalled, |
i_instruction, i_gie, i_pc, i_pf_valid, |
i_illegal, |
o_phase, o_illegal, |
o_pc, o_gie, |
o_dcdR, o_dcdA, o_dcdB, o_I, o_zI, |
o_cond, o_wF, |
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, |
o_pipe |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH; |
input i_clk, i_rst, i_ce, i_stalled; |
input [31:0] i_instruction; |
input i_gie; |
input [(AW-1):0] i_pc; |
input i_pf_valid, i_illegal; |
output wire o_phase; |
output reg o_illegal; |
output reg [(AW-1):0] o_pc; |
output reg o_gie; |
output reg [6:0] o_dcdR, o_dcdA, o_dcdB; |
output wire [31:0] o_I; |
output reg o_zI; |
output reg [3:0] o_cond; |
output reg o_wF; |
output reg [3:0] o_op; |
output reg o_ALU, o_M, o_DV, o_FP, o_break, o_lock; |
output reg o_wR, o_rA, o_rB; |
output wire o_early_branch; |
output wire [(AW-1):0] o_branch_pc; |
output reg o_pipe; |
|
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire o_dcd_early_branch; |
wire [(AW-1):0] o_dcd_branch_pc; |
reg o_dcdI, o_dcdIz; |
|
|
wire [4:0] w_op; |
wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU; |
wire [4:0] w_dcdR, w_dcdB, w_dcdA; |
wire w_dcdR_pc, w_dcdR_cc; |
wire w_dcdA_pc, w_dcdA_cc; |
wire w_dcdB_pc, w_dcdB_cc; |
wire [3:0] w_cond; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP; |
wire w_wR, w_rA, w_rB, w_wR_n; |
|
|
wire [31:0] iword; |
`ifdef OPT_VLIW |
reg [16:0] r_nxt_half; |
assign iword = (o_phase) |
// set second half as a NOOP ... but really |
// shouldn't matter |
? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 } |
: i_instruction; |
`else |
assign iword = { 1'b0, i_instruction[30:0] }; |
`endif |
|
assign w_op= iword[26:22]; |
assign w_mov = (w_op == 5'h0f); |
assign w_ldi = (w_op[4:1] == 4'hb); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldixx = (w_op[4:1] == 4'h4); |
assign w_ALU = (~w_op[4]); |
|
// 4 LUTs |
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
iword[30:27] }; |
// 4 LUTs |
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie, |
iword[17:14] }; |
|
// 0 LUTs |
assign w_dcdA = w_dcdR; |
// 2 LUTs, 1 delay each |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
// 0 LUTs |
assign w_dcdA_pc = w_dcdR_pc; |
assign w_dcdA_cc = w_dcdR_cc; |
// 2 LUTs, 1 delays each |
assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG); |
|
// Under what condition will we execute this |
// instruction? Only the load immediate instruction |
// is completely unconditional. |
// |
// 3+4 LUTs |
assign w_cond = (w_ldi) ? 4'h8 : |
(iword[31])?{(iword[20:19]==2'b00), |
1'b0,iword[20:19]} |
: { (iword[21:19]==3'h0), iword[21:19] }; |
|
// 1 LUT |
assign w_dcdM = (w_op[4:1] == 4'h9); |
// 1 LUT |
assign w_dcdDV = (w_op[4:1] == 4'ha); |
// 1 LUT |
assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7); |
// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before) |
// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV |
assign w_rA = (w_dcdFP) |
// Divide's read A |
||(w_dcdDV) |
// ALU read's A, unless it's a MOV to A |
// This includes LDIHI/LDILO |
||((~w_op[4])&&(w_op[3:0]!=4'hf)) |
// STO's read A |
||((w_dcdM)&&(w_op[0])) |
// Test/compares |
||(w_op[4:1]== 4'h8); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx))); |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = ((w_dcdM)&&(w_op[0])) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
assign w_wR = ~w_wR_n; |
// 1-output bit (5 Opcode bits, 3 out-reg bits, 3 condition bits) |
// |
// This'd be 4 LUTs, save that we have the carve out for NOOPs |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldixx)))); |
|
// Bottom 13 bits: no LUT's |
// w_dcd[12: 0] -- no LUTs |
// w_dcd[ 13] -- 2 LUTs |
// w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay |
// w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined) |
reg [22:0] r_I; |
wire [22:0] w_I, w_fullI; |
wire w_Iz; |
|
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move |
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] } |
: { {(23-14){iword[13]}}, iword[13:0] } |
)); |
|
`ifdef OPT_VLIW |
wire [5:0] w_halfI; |
assign w_halfI = (w_ldi) ? iword[5:0] |
:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]}); |
assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI; |
`else |
assign w_I = w_fullI; |
`endif |
assign w_Iz = (w_I == 0); |
|
|
`ifdef OPT_VLIW |
// |
// The o_phase parameter is special. It needs to let the software |
// following know that it cannot break/interrupt on an o_phase asserted |
// instruction, lest the break take place between the first and second |
// half of a VLIW instruction. To do this, o_phase must be asserted |
// when the first instruction half is valid, but not asserted on either |
// a 32-bit instruction or the second half of a 2x16-bit instruction. |
reg r_phase; |
initial r_phase = 1'b0; |
always @(posedge i_clk) |
if (i_rst) // When no instruction is in the pipe, phase is zero |
r_phase <= 1'b0; |
else if (i_ce) |
r_phase <= (o_phase)? 1'b0:(i_instruction[31]); |
// Phase is '1' on the first instruction of a two-part set |
// But, due to the delay in processing, it's '1' when our output is |
// valid for that first part, but that'll be the same time we |
// are processing the second part ... so it may look to us like a '1' |
// on the second half of processing. |
|
assign o_phase = r_phase; |
`else |
assign o_phase = 1'b0; |
`endif |
|
|
initial o_illegal = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
o_illegal <= 1'b0; |
else if (i_ce) |
begin |
`ifdef OPT_VLIW |
o_illegal <= (i_illegal); |
`else |
o_illegal <= ((i_illegal) || (i_instruction[31])); |
`endif |
if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5)) |
o_illegal <= 1'b1; |
|
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
|
|
if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP)) |
o_illegal <= 1'b1; |
|
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7) |
&&( |
(w_op[2:0] != 3'h2) // LOCK |
&&(w_op[2:0] != 3'h1) // BREAK |
&&(w_op[2:0] != 3'h0))) // NOOP |
o_illegal <= 1'b1; |
end |
|
|
always @(posedge i_clk) |
if (i_ce) |
begin |
`ifdef OPT_VLIW |
if (~o_phase) |
begin |
o_gie<= i_gie; |
// i.e. dcd_pc+1 |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
end |
`else |
o_gie<= i_gie; |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
`endif |
|
// Under what condition will we execute this |
// instruction? Only the load immediate instruction |
// is completely unconditional. |
o_cond <= w_cond; |
// Don't change the flags on conditional instructions, |
// UNLESS: the conditional instruction was a CMP |
// or TST instruction. |
o_wF <= w_wF; |
|
// Record what operation/op-code (4-bits) we are doing |
// Note that LDI magically becomes a MOV |
// instruction here. That way it's a pass through |
// the ALU. Likewise, the two compare instructions |
// CMP and TST becomes SUB and AND here as well. |
// We keep only the bottom four bits, since we've |
// already done the rest of the decode necessary to |
// settle between the other instructions. For example, |
// o_FP plus these four bits uniquely defines the FP |
// instruction, o_DV plus the bottom of these defines |
// the divide, etc. |
o_op <= (w_ldi)? 4'hf:w_op[3:0]; |
|
// Default values |
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR}; |
o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA}; |
o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB}; |
o_wR <= w_wR; |
o_rA <= w_rA; |
o_rB <= w_rB; |
r_I <= w_I; |
o_zI <= w_Iz; |
|
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT |
o_M <= w_dcdM; |
o_DV <= w_dcdDV; |
o_FP <= w_dcdFP; |
|
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001); |
o_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010); |
`ifdef OPT_VLIW |
r_nxt_half <= { iword[31], iword[13:5], |
((iword[21])? iword[20:19] : 2'h0), |
iword[4:0] }; |
`endif |
end |
|
|
generate |
if (EARLY_BRANCHING!=0) |
begin |
reg r_early_branch; |
reg [(AW-1):0] r_branch_pc; |
always @(posedge i_clk) |
if ((i_ce)&&(w_dcdR_pc)&&(w_cond[3])) |
begin |
if ((w_op == 5'hf)&&(w_dcdB_pc)&&(w_dcdA_pc)) |
begin // Move (X+PC) to PC |
r_early_branch <= 1'b1; |
end else if (w_op[4:1] == 4'hb) // LDI to PC |
begin // LDI x,PC |
r_early_branch <= 1'b1; |
end else if ((w_op[4:0] == 5'h00)&&(~w_rB)&&(w_dcdA_pc)) |
begin // Add x,PC |
r_early_branch <= 1'b1; |
end else begin |
r_early_branch <= 1'b0; |
end |
end else begin |
if (i_ce) |
r_early_branch <= 1'b0; |
end |
always @(posedge i_clk) |
if (i_ce) |
begin |
if (w_op[4:1] == 4'hb) |
r_branch_pc <= {{(AW-23){w_I[22]}},w_I}; |
else |
r_branch_pc <= i_pc+{{(AW-23){w_I[22]}},w_I} |
+{{(AW-1){1'b0}},1'b1}; |
end |
|
assign o_early_branch = r_early_branch; |
assign o_branch_pc = r_branch_pc; |
end else begin |
assign o_early_branch = 1'b0; |
assign o_branch_pc = {(AW){1'b0}}; |
end endgenerate |
|
|
// To be a pipeable operation there must be ... |
// 1. Two valid adjacent instructions |
// 2. Both must be memory operations, of the same time (both lods |
// or both stos) |
// 3. Both must use the same register base address |
// 4. Both must be to the same address, or the address incremented |
// by one |
// Note that we're not using iword here ... there's a lot of logic |
// taking place, and it's only valid if the new word is not compressed. |
// |
reg r_valid; |
always @(posedge i_clk) |
if (i_ce) |
o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31]) |
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22]) |
&&(i_instruction[17:14] == o_dcdB[3:0]) |
&&(i_gie == o_gie) |
&&((i_instruction[21:19]==o_cond[2:0]) |
||(o_cond[2:0] == 3'h0)) |
&&((i_instruction[13:0]==r_I[13:0]) |
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1))); |
always @(posedge i_clk) |
if (i_rst) |
r_valid <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_valid <= 1'b1; |
else if (~i_stalled) |
r_valid <= 1'b0; |
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; |
|
endmodule |
/cpu/wbdmac.v
0,0 → 1,336
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: wbdmac.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Wishbone DMA controller |
// |
// This module is controllable via the wishbone, and moves values from |
// one location in the wishbone address space to another. The amount of |
// memory moved at any given time can be up to 4kB, or equivalently 1kW. |
// Four registers control this DMA controller: a control/status register, |
// a length register, a source WB address and a destination WB address. |
// These register may be read at any time, but they may only be written |
// to when the controller is idle. |
// |
// The meanings of three of the setup registers should be self explanatory: |
// - The length register controls the total number of words to |
// transfer. |
// - The source address register controls where the DMA controller |
// reads from. This address may or may not be incremented |
// after each read, depending upon the setting in the |
// control/status register. |
// - The destination address register, which controls where the DMA |
// controller writes to. This address may or may not be |
// incremented after each write, also depending upon the |
// setting in the control/status register. |
// |
// It is the control/status register, at local address zero, that needs |
// more definition: |
// |
// Bits: |
// 31 R Write protect If this is set to one, it means the |
// write protect bit is set and the controller |
// is therefore idle. This bit will be set upon |
// completing any transfer. |
// 30 R Error. The controller stopped mid-transfer |
// after receiving a bus error. |
// 29 R/W inc_s_n If set to one, the source address |
// will not increment from one read to the next. |
// 28 R/W inc_d_n If set to one, the destination address |
// will not increment from one write to the next. |
// 27 R Always 0 |
// 26..16 R nread Indicates how many words have been read, |
// and not necessarily written (yet). This |
// combined with the cfg_len parameter should tell |
// exactly where the controller is at mid-transfer. |
// 27..16 W WriteProtect When a 12'h3db is written to these |
// bits, the write protect bit will be cleared. |
// |
// 15 R/W on_dev_trigger When set to '1', the controller will |
// wait for an external interrupt before starting. |
// 14..10 R/W device_id This determines which external interrupt |
// will trigger a transfer. |
// 9..0 R/W transfer_len How many bytes to transfer at one time. |
// The minimum transfer length is one, while zero |
// is mapped to a transfer length of 1kW. |
// |
// |
// To use this, follow this checklist: |
// 1. Wait for any prior DMA operation to complete |
// (Read address 0, wait 'till either top bit is set or cfg_len==0) |
// 2. Write values into length, source and destination address. |
// (writei(3, &vals) should be sufficient for this.) |
// 3. Enable the DMAC interrupt in whatever interrupt controller is present |
// on the system. |
// 4. Write the final start command to the setup/control/status register: |
// Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger, |
// appropriately for your task |
// Write 12'h3db to the upper word. |
// Set the lower word to either all zeros, or a smaller transfer |
// length if desired. |
// 5. wait() for the interrupt and the operation to complete. |
// Prior to completion, number of items successfully transferred |
// be read from the length register. If the internal buffer is |
// being used, then you can read how much has been read into that |
// buffer by reading from bits 25..16 of this control/status |
// register. |
// |
// Creator: Dan Gisselquist |
// Gisselquist Technology, LLC |
// |
// Copyright: 2015 |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbdmac(i_clk, |
i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data, |
o_swb_ack, o_swb_stall, o_swb_data, |
o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data, |
i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err, |
i_dev_ints, |
o_interrupt); |
parameter ADDRESS_WIDTH=32, LGMEMLEN = 10, |
DW=32, LGDV=5,AW=ADDRESS_WIDTH; |
input i_clk; |
// Slave/control wishbone inputs |
input i_swb_cyc, i_swb_stb, i_swb_we; |
input [1:0] i_swb_addr; |
input [(DW-1):0] i_swb_data; |
// Slave/control wishbone outputs |
output reg o_swb_ack; |
output wire o_swb_stall; |
output reg [(DW-1):0] o_swb_data; |
// Master/DMA wishbone control |
output reg o_mwb_cyc, o_mwb_stb, o_mwb_we; |
output reg [(AW-1):0] o_mwb_addr; |
output reg [(DW-1):0] o_mwb_data; |
// Master/DMA wishbone responses from the bus |
input i_mwb_ack, i_mwb_stall; |
input [(DW-1):0] i_mwb_data; |
input i_mwb_err; |
// The interrupt device interrupt lines |
input [(DW-1):0] i_dev_ints; |
// An interrupt to be set upon completion |
output reg o_interrupt; |
// Need to release the bus for a higher priority user |
// This logic had lots of problems, so it is being |
// removed. If you want to make sure the bus is available |
// for a higher priority user, adjust the transfer length |
// accordingly. |
// |
// input i_other_busmaster_requests_bus; |
// |
|
|
reg cfg_wp; // Write protect |
reg cfg_err; |
reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len; |
reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one; |
reg cfg_incs, cfg_incd; |
reg [(LGDV-1):0] cfg_dev_trigger; |
reg cfg_on_dev_trigger; |
|
// Single block operations: We'll read, then write, up to a single |
// memory block here. |
|
reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)]; |
reg [(LGMEMLEN):0] nread, nwritten, nacks; |
wire [(AW-1):0] bus_nacks; |
assign bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks }; |
|
initial o_interrupt = 1'b0; |
initial o_mwb_cyc = 1'b0; |
initial cfg_err = 1'b0; |
initial cfg_wp = 1'b0; |
initial cfg_len = {(AW){1'b0}}; |
initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}}; |
initial cfg_on_dev_trigger = 1'b0; |
always @(posedge i_clk) |
if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle |
begin |
if ((o_mwb_stb)&&(~i_mwb_stall)) |
begin |
nwritten <= nwritten+1; |
if (nwritten == nread-1) |
// Wishbone interruptus |
o_mwb_stb <= 1'b0; |
else if (cfg_incd) begin |
o_mwb_addr <= o_mwb_addr + 1; |
cfg_waddr <= cfg_waddr + 1; |
end |
// o_mwb_data <= dma_mem[nwritten + 1]; |
end |
|
if (i_mwb_err) |
begin |
o_mwb_cyc <= 1'b0; |
cfg_err <= 1'b1; |
cfg_len <= 0; |
nread <= 0; |
end else if (i_mwb_ack) |
begin |
nacks <= nacks+1; |
cfg_len <= cfg_len - 1; |
if ((nacks+1 == nwritten)&&(~o_mwb_stb)) |
begin |
o_mwb_cyc <= 1'b0; |
nread <= 0; |
o_interrupt <= (cfg_len == 1); |
// Turn write protect back on |
cfg_wp <= 1'b1; |
end |
end |
end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle |
begin |
if ((o_mwb_stb)&&(~i_mwb_stall)) |
begin |
nacks <= nacks+1; |
if ((nacks == {1'b0, cfg_blocklen_sub_one}) |
||(bus_nacks <= cfg_len-1)) |
// Wishbone interruptus |
o_mwb_stb <= 1'b0; |
else if (cfg_incs) begin |
o_mwb_addr <= o_mwb_addr + 1; |
end |
end |
|
if (i_mwb_err) |
begin |
o_mwb_cyc <= 1'b0; |
cfg_err <= 1'b1; |
cfg_len <= 0; |
nread <= 0; |
end else if (i_mwb_ack) |
begin |
nread <= nread+1; |
if ((~o_mwb_stb)&&(nread+1 == nacks)) |
begin |
o_mwb_cyc <= 1'b0; |
nacks <= 0; |
end |
if (cfg_incs) |
cfg_raddr <= cfg_raddr + 1; |
// dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data; |
end |
end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err)) |
begin // Initiate/continue a write cycle |
o_mwb_cyc <= 1'b1; |
o_mwb_stb <= 1'b1; |
o_mwb_we <= 1'b1; |
// o_mwb_data <= dma_mem[0]; |
o_mwb_addr <= cfg_waddr; |
// nwritten <= 0; // Can't set to zero, in case we're |
// nacks <= 0; // continuing a cycle |
end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp) |
&&((~cfg_on_dev_trigger) |
||(i_dev_ints[cfg_dev_trigger]))) |
begin // Initiate a read cycle |
o_mwb_cyc <= 1'b1; |
o_mwb_stb <= 1'b1; |
o_mwb_we <= 1'b0; |
o_mwb_addr<= cfg_raddr; |
nwritten <= 0; |
nread <= 0; |
nacks <= 0; |
end else begin |
o_mwb_cyc <= 1'b0; |
o_mwb_stb <= 1'b0; |
o_mwb_we <= 1'b0; |
o_mwb_addr <= cfg_raddr; |
o_interrupt<= 1'b0; |
nwritten <= 0; |
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)) |
begin |
cfg_wp <= 1'b1; |
case(i_swb_addr) |
2'b00: begin |
cfg_wp <= (i_swb_data[27:16]!=12'hfed); |
cfg_blocklen_sub_one |
<= i_swb_data[(LGMEMLEN-1):0] |
+ {(LGMEMLEN){1'b1}}; |
// i.e. -1; |
cfg_dev_trigger <= i_swb_data[14:10]; |
cfg_on_dev_trigger <= i_swb_data[15]; |
cfg_incs <= ~i_swb_data[29]; |
cfg_incd <= ~i_swb_data[28]; |
cfg_err <= 1'b0; |
end |
2'b01: cfg_len <= i_swb_data[(AW-1):0]; |
2'b10: cfg_raddr <= i_swb_data[(AW-1):0]; |
2'b11: cfg_waddr <= i_swb_data[(AW-1):0]; |
endcase |
end |
end |
|
// |
// This is tricky. In order for Vivado to consider dma_mem to be a |
// proper memory, it must have a simple address fed into it. Hence |
// the read_address (rdaddr) register. The problem is that this |
// register must always be one greater than the address we actually |
// want to read from, unless we are idling. So ... the math is touchy. |
// |
reg [(LGMEMLEN-1):0] rdaddr; |
always @(posedge i_clk) |
if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)) |
// This would be the normal advance, save that we are |
// already one ahead of nwritten |
rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1}; |
else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err)) |
// Here's where we do our extra advance |
rdaddr <= nwritten[(LGMEMLEN-1):0]+1; |
else if ((~o_mwb_cyc)||(~o_mwb_we)) |
rdaddr <= nwritten[(LGMEMLEN-1):0]; |
always @(posedge i_clk) |
if ((~o_mwb_cyc)||((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))) |
o_mwb_data <= dma_mem[rdaddr]; |
always @(posedge i_clk) |
if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack)) |
dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data; |
|
always @(posedge i_clk) |
casez(i_swb_addr) |
2'b00: o_swb_data <= { ~cfg_wp, cfg_err, |
~cfg_incs, ~cfg_incd, |
1'b0, nread, |
cfg_on_dev_trigger, cfg_dev_trigger, |
cfg_blocklen_sub_one |
}; |
2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len }; |
2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr}; |
2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr}; |
endcase |
|
always @(posedge i_clk) |
if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we)) |
o_swb_ack <= 1'b1; |
// else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0)) |
else |
o_swb_ack <= 1'b0; |
|
assign o_swb_stall = 1'b0; |
|
endmodule |
|
/cpu/prefetch.v
0,0 → 1,124
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: prefetch.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This is a very simple instruction fetch approach. It gets |
// one instruction at a time. Future versions should pipeline |
// fetches and perhaps even cache results--this doesn't do that. |
// It should, however, be simple enough to get things running. |
// |
// The interface is fascinating. The 'i_pc' input wire is just |
// a suggestion of what to load. Other wires may be loaded |
// instead. i_pc is what must be output, not necessarily input. |
// |
// 20150919 -- Added support for the WB error signal. When reading an |
// instruction results in this signal being raised, the pipefetch |
// module will set an illegal instruction flag to be returned to |
// the CPU together with the instruction. Hence, the ZipCPU |
// can trap on it if necessary. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Flash requires a minimum of 4 clocks per byte to read, so that would be |
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline |
// mode which this prefetch does not support. In non--pipelined mode, the |
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read, |
// or 72 clocks to fetch one instruction. |
module prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux, |
o_i, o_pc, o_aux, o_valid, o_illegal, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH; |
input i_clk, i_rst, i_ce, i_stalled_n; |
input [(AW-1):0] i_pc; |
input [(AUX_WIDTH-1):0] i_aux; |
output reg [31:0] o_i; |
output reg [(AW-1):0] o_pc; |
output reg [(AUX_WIDTH-1):0] o_aux; |
output reg o_valid, o_illegal; |
// Wishbone outputs |
output reg o_wb_cyc, o_wb_stb; |
output wire o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
// And return inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
|
assign o_wb_we = 1'b0; |
assign o_wb_data = 32'h0000; |
|
// Let's build it simple and upgrade later: For each instruction |
// we do one bus cycle to get the instruction. Later we should |
// pipeline this, but for now let's just do one at a time. |
initial o_wb_cyc = 1'b0; |
initial o_wb_stb = 1'b0; |
initial o_wb_addr= 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_ack)) |
begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle |
begin |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
end else if (o_wb_cyc) // Independent of ce |
begin |
if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)) |
o_wb_stb <= 1'b0; |
if (i_wb_ack) |
o_wb_cyc <= 1'b0; |
end |
|
always @(posedge i_clk) |
if (i_rst) // Set the address to guarantee the result is invalid |
o_wb_addr <= {(AW){1'b1}}; |
else if ((i_ce)&&(~o_wb_cyc)) |
o_wb_addr <= i_pc; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
o_aux <= i_aux; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
o_i <= i_wb_data; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
o_pc <= o_wb_addr; |
initial o_valid = 1'b0; |
initial o_illegal = 1'b0; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
begin |
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err); |
o_illegal <= i_wb_err; |
end else if (i_stalled_n) |
begin |
o_valid <= 1'b0; |
o_illegal <= 1'b0; |
end |
|
endmodule |
/cpu/memops.v
0,0 → 1,150
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memops.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: A memory unit to support a CPU. |
// |
// In the interests of code simplicity, this memory operator is |
// susceptible to unknown results should a new command be sent to it |
// before it completes the last one. Unpredictable results might then |
// occurr. |
// |
// 20150919 -- Added support for handling BUS ERR's (i.e., the WB |
// error signal). |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module memops(i_clk, i_rst, i_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_stb, i_lock; |
// CPU interface |
input i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
// CPU outputs |
output wire o_busy; |
output reg o_valid; |
output reg o_err; |
output reg [4:0] o_wreg; |
output reg [31:0] o_result; |
// Wishbone outputs |
output wire o_wb_cyc_gbl; |
output reg o_wb_stb_gbl; |
output wire o_wb_cyc_lcl; |
output reg o_wb_stb_lcl; |
output reg o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
initial r_wb_cyc_gbl = 1'b0; |
initial r_wb_cyc_lcl = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl)) |
begin |
if ((i_wb_ack)||(i_wb_err)) |
begin |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
end |
end else if (i_stb) // New memory operation |
begin // Grab the wishbone |
r_wb_cyc_lcl <= lcl_stb; |
r_wb_cyc_gbl <= gbl_stb; |
end |
always @(posedge i_clk) |
if (o_wb_cyc_gbl) |
o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall); |
else |
o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation |
always @(posedge i_clk) |
if (o_wb_cyc_lcl) |
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); |
else |
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation |
always @(posedge i_clk) |
if (i_stb) |
begin |
o_wb_we <= i_op; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW-1):0]; |
end |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we); |
initial o_err = 1'b0; |
always @(posedge i_clk) |
o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err); |
assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl); |
|
always @(posedge i_clk) |
if (i_stb) |
o_wreg <= i_oreg; |
always @(posedge i_clk) |
if (i_wb_ack) |
o_result <= i_wb_data; |
|
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg lock_gbl, lock_lcl; |
|
initial lock_gbl = 1'b0; |
initial lock_lcl = 1'b0; |
|
always @(posedge i_clk) |
begin |
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl)); |
end |
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); |
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl); |
end else begin |
assign o_wb_cyc_gbl = (r_wb_cyc_gbl); |
assign o_wb_cyc_lcl = (r_wb_cyc_lcl); |
end endgenerate |
endmodule |
/cpu/zipjiffies.v
0,0 → 1,142
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipjiffies.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This peripheral is motivated by the Linux use of 'jiffies'. |
// A process, in Linux, can request to be put to sleep until a certain |
// number of 'jiffies' have elapsed. Using this interface, the CPU can |
// read the number of 'jiffies' from this peripheral (it only has the |
// one location in address space), add the sleep length to it, and |
// write the result back to the peripheral. The zipjiffies peripheral |
// will record the value written to it only if it is nearer the current |
// counter value than the last current waiting interrupt time. If no |
// other interrupts are waiting, and this time is in the future, it will |
// be enabled. (There is currrently no way to disable a jiffie interrupt |
// once set.) The processor may then place this sleep request into a |
// list among other sleep requests. Once the timer expires, it would |
// write the next jiffy request to the peripheral and wake up the process |
// whose timer had expired. |
// |
// Quite elementary, really. |
// |
// Interface: |
// This peripheral contains one register: a counter. Reads from the |
// register return the current value of the counter. Writes within |
// the (N-1) bit space following the current time set an interrupt. |
// Writes of values that occurred in the last 2^(N-1) ticks will be |
// ignored. The timer then interrupts when it's value equals that time. |
// Multiple writes cause the jiffies timer to select the nearest possible |
// interrupt. Upon an interrupt, the next interrupt time/value is cleared |
// and will need to be reset if the CPU wants to get notified again. With |
// only the single interface, there is no way of knowing when the next |
// interrupt is scheduled for, neither is there any way to slow down the |
// interrupt timer in case you don't want it overflowing as often and you |
// wish to wait more jiffies than it supports. Thus, currently, if you |
// have a timer you wish to wait upon that is more than 2^31 into the |
// future, you would need to set timers along the way, wake up on those |
// timers, and set further timer's until you finally get to your |
// destination. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module zipjiffies(i_clk, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_int); |
parameter BW = 32, VW = (BW-2); |
input i_clk, i_ce; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(BW-1):0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output wire [(BW-1):0] o_wb_data; |
// Interrupt line |
output reg o_int; |
|
// |
// Our counter logic: The counter is always counting up--it cannot |
// be stopped or altered. It's really quite simple. Okay, not quite. |
// We still support the clock enable line. We do this in order to |
// support debugging, so that if we get everything running inside a |
// debugger, the timer's all slow down so that everything can be stepped |
// together, one clock at a time. |
// |
reg [(BW-1):0] r_counter; |
always @(posedge i_clk) |
if (i_ce) |
r_counter <= r_counter+1; |
|
// |
// Writes to the counter set an interrupt--but only if they are in the |
// future as determined by the signed result of an unsigned subtract. |
// |
reg int_set, new_set; |
reg [(BW-1):0] int_when, new_when; |
wire signed [(BW-1):0] till_when, till_wb; |
assign till_when = int_when-r_counter; |
assign till_wb = new_when-r_counter; |
|
initial new_set = 1'b0; |
always @(posedge i_clk) |
// Delay things by a clock to simplify our logic |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
begin |
new_set <= 1'b1; |
new_when<= i_wb_data; |
end else |
new_set <= 1'b0; |
|
initial o_int = 1'b0; |
initial int_set = 1'b0; |
always @(posedge i_clk) |
begin |
o_int <= 1'b0; |
if ((i_ce)&&(int_set)&&(r_counter == int_when)) |
begin // Interrupts are self-clearing |
o_int <= 1'b1; // Set the interrupt flag |
int_set <= 1'b0;// Clear the interrupt |
end |
|
if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set))) |
begin |
int_when <= new_when; |
int_set <= ((int_set)||(till_wb>0)); |
end |
end |
|
// |
// Acknowledge any wishbone accesses -- everything we did took only |
// one clock anyway. |
// |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
|
assign o_wb_data = r_counter; |
assign o_wb_stall = 1'b0; |
endmodule |
/cpu/zipcounter.v
0,0 → 1,82
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcounter.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: |
// A very, _very_ simple counter. It's purpose doesn't really |
// include rollover, but it will interrupt on rollover. It can be set, |
// although my design concept is that it can be reset. It cannot be |
// halted. It will always produce interrupts--whether or not they are |
// handled interrupts is another question--that's up to the interrupt |
// controller. |
// |
// My intention is to use this counter for process accounting: I should |
// be able to use this to count clock ticks of processor time assigned to |
// each task by resetting the counter at the beginning of every task |
// interval, and reading the result at the end of the interval. As long |
// as the interval is less than 2^32 clocks, there should be no problem. |
// Similarly, this can be used to measure CPU wishbone bus stalls, |
// prefetch stalls, or other CPU stalls (i.e. stalling as part of a JMP |
// instruction, or a read from the condition codes following a write). |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module zipcounter(i_clk, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_int); |
parameter BW = 32; |
input i_clk, i_ce; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(BW-1):0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(BW-1):0] o_wb_data; |
// Interrupt line |
output reg o_int; |
|
initial o_wb_data = 32'h00; |
always @(posedge i_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
o_wb_data <= i_wb_data; |
else if (i_ce) |
o_wb_data <= o_wb_data + 1; |
|
initial o_int = 0; |
always @(posedge i_clk) |
if (i_ce) |
o_int <= &o_wb_data; |
else |
o_int <= 1'b0; |
|
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
assign o_wb_stall = 1'b0; |
endmodule |
/cpu/ziptimer.v
0,0 → 1,135
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: ziptimer.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: A lighter weight implementation of the Zip Timer. |
// |
// Interface: |
// Two options: |
// 1. One combined register for both control and value, and ... |
// The reload value is set any time the timer data value is "set". |
// Reading the register returns the timer value. Controls are |
// set so that writing a value to the timer automatically starts |
// it counting down. |
// 2. Two registers, one for control one for value. |
// The control register would have the reload value in it. |
// On the clock when the interface is set to zero the interrupt is set. |
// Hence setting the timer to zero will disable the timer without |
// setting any interrupts. Thus setting it to five will count |
// 5 clocks: 5, 4, 3, 2, 1, Interrupt. |
// |
// |
// Control bits: |
// (Start_n/Stop. This bit has been dropped. Writing to this |
// timer any value but zero starts it. Writing a zero |
// clears and stops it.) |
// AutoReload. If set, then on reset the timer automatically |
// loads the last set value and starts over. This is |
// useful for distinguishing between a one-time interrupt |
// timer, and a repetitive interval timer. |
// (INTEN. Interrupt enable--reaching zero always creates an |
// interrupt, so this control bit isn't needed. The |
// interrupt controller can be used to mask the interrupt.) |
// (COUNT-DOWN/UP: This timer is *only* a count-down timer. |
// There is no means of setting it to count up.) |
// WatchDog |
// This timer can be implemented as a watchdog timer simply by |
// connecting the interrupt line to the reset line of the CPU. |
// When the timer then expires, it will trigger a CPU reset. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module ziptimer(i_clk, i_rst, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_int); |
parameter BW = 32, VW = (BW-1); |
input i_clk, i_rst, i_ce; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(BW-1):0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output wire [(BW-1):0] o_wb_data; |
// Interrupt line |
output reg o_int; |
|
reg r_auto_reload, r_running; |
reg [(VW-1):0] r_reload_value; |
|
wire wb_write; |
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)); |
|
initial r_running = 1'b0; |
initial r_auto_reload = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_running <= 1'b0; |
else if (wb_write) |
r_running <= (|i_wb_data[(VW-1):0]); |
else if ((o_int)&&(~r_auto_reload)) |
r_running <= 1'b0; |
|
|
always @(posedge i_clk) |
if (wb_write) |
r_auto_reload <= (i_wb_data[(BW-1)]); |
|
// If setting auto-reload mode, and the value to other |
// than zero, set the auto-reload value |
always @(posedge i_clk) |
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0])) |
r_reload_value <= i_wb_data[(VW-1):0]; |
|
|
reg [(VW-1):0] r_value; |
initial r_value = 0; |
always @(posedge i_clk) |
if (wb_write) |
r_value <= i_wb_data[(VW-1):0]; |
else if ((r_running)&&(i_ce)&&(~o_int)) |
r_value <= r_value + {(VW){1'b1}}; // r_value - 1; |
else if ((r_running)&&(r_auto_reload)&&(o_int)) |
r_value <= r_reload_value; |
|
// Set the interrupt on our last tick. |
initial o_int = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 }); |
else |
o_int <= 1'b0; |
|
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
assign o_wb_stall = 1'b0; |
|
assign o_wb_data = { r_auto_reload, r_value }; |
|
endmodule |
/cpu/pipefetch.v
0,0 → 1,299
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pipefetch.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Keeping our CPU fed with instructions, at one per clock and |
// with no stalls, can be quite a chore. Worse, the Wishbone |
// takes a couple of cycles just to read one instruction from |
// the bus. However, if we use pipeline accesses to the Wishbone |
// bus, then we can read more and faster. Further, if we cache |
// these results so that we have them before we need them, then |
// we have a chance of keeping our CPU from stalling. Those are |
// the purposes of this instruction fetch module: 1) Pipeline |
// wishbone accesses, and 2) an instruction cache. |
// |
// 20150919 -- Fixed a nasty race condition whereby the pipefetch routine |
// would produce either the same instruction twice, or skip |
// an instruction. This condition was dependent on the CPU stall |
// condition, and would only take place if the pipeline wasn't |
// completely full throughout the stall. |
// |
// Interface support was also added for trapping on illegal |
// instructions (i.e., instruction fetches that cause bus errors), |
// however the internal interface has not caught up to supporting |
// these exceptions yet. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc, |
o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request, |
o_illegal); |
parameter RESET_ADDRESS=32'h0010_0000, |
LGCACHELEN = 6, ADDRESS_WIDTH=24, |
CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH; |
input i_clk, i_rst, i_new_pc, |
i_clear_cache, i_stall_n; |
input [(AW-1):0] i_pc; |
output reg [(BUSW-1):0] o_i; |
output reg [(AW-1):0] o_pc; |
output wire o_v; |
// |
output reg o_wb_cyc, o_wb_stb; |
output wire o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output wire [(BUSW-1):0] o_wb_data; |
// |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [(BUSW-1):0] i_wb_data; |
// |
// Is the (data) memory unit also requesting access to the bus? |
input i_wb_request; |
output wire o_illegal; |
|
// Fixed bus outputs: we read from the bus only, never write. |
// Thus the output data is ... irrelevant and don't care. We set it |
// to zero just to set it to something. |
assign o_wb_we = 1'b0; |
assign o_wb_data = 0; |
|
reg [(AW-1):0] r_cache_base; |
reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting; |
reg [(BUSW-1):0] cache[0:(CACHELEN-1)]; |
|
wire [(LGCACHELEN-1):0] w_cache_offset; |
reg [1:0] r_cache_offset; |
|
reg r_addr_set; |
reg [(AW-1):0] r_addr; |
|
wire [(AW-1):0] bus_nvalid; |
assign bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid }; |
|
// What are some of the conditions for which we need to restart the |
// cache? |
wire w_pc_out_of_bounds; |
assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0) |
||(i_pc < r_cache_base) |
||(i_pc >= r_cache_base + CACHELEN) |
||(i_pc >= r_cache_base + bus_nvalid+5))); |
wire w_ran_off_end_of_cache; |
assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base) |
||(r_addr >= r_cache_base + CACHELEN) |
||(r_addr >= r_cache_base + bus_nvalid+5))); |
wire w_running_out_of_cache; |
assign w_running_out_of_cache = (r_addr_set) |
&&(r_addr >= r_cache_base + |
// {{(AW-LGCACHELEN-1),{1'b0}},2'b11, |
// {(LGCACHELEN-1){1'b0}}}) |
// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1))) |
+(3<<(LGCACHELEN-2))) |
&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]); |
|
initial r_cache_base = RESET_ADDRESS; |
always @(posedge i_clk) |
begin |
if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err))) |
begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
// r_cache_base <= RESET_ADDRESS; |
// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0) |
// &&(i_pc >= r_cache_base) |
// &&(i_pc < r_cache_base + bus_nvalid)) |
// begin |
// The new instruction is in our cache, do nothing |
// with the bus here. |
end else if ((o_wb_cyc)&&(w_pc_out_of_bounds)) |
begin |
// We need to abandon our bus action to start over in |
// a new region, setting up a new cache. This may |
// happen mid cycle while waiting for a result. By |
// dropping o_wb_cyc, we state that we are no longer |
// interested in that result--whatever it might be. |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set)) |
begin |
// Restart a bus cycle that was interrupted when the |
// data section wanted access to our bus. |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
// o_wb_addr <= r_cache_base + bus_nvalid; |
end else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache))) |
begin |
// Start a bus transaction |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
// o_wb_addr <= (i_new_pc) ? i_pc : r_addr; |
// r_nvalid <= 0; |
// r_cache_base <= (i_new_pc) ? i_pc : r_addr; |
// w_cache_offset <= 0; |
end else if ((~o_wb_cyc)&&(w_running_out_of_cache)) |
begin |
// If we're using the last quarter of the cache, then |
// let's start a bus transaction to extend the cache. |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN)); |
// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2)); |
// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2)); |
// w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2)); |
end else if (o_wb_cyc) |
begin |
// This handles everything ... but the case where |
// while reading we need to extend our cache. |
if ((o_wb_stb)&&(~i_wb_stall)) |
begin |
// o_wb_addr <= o_wb_addr + 1; |
if ((o_wb_addr - r_cache_base >= CACHELEN-1) |
||(i_wb_request)) |
o_wb_stb <= 1'b0; |
end |
|
if (i_wb_ack) |
begin |
// r_nvalid <= r_nvalid + 1; |
if ((r_acks_waiting == 1)&&(~o_wb_stb)) |
o_wb_cyc <= 1'b0; |
end else if ((r_acks_waiting == 0)&&(~o_wb_stb)) |
o_wb_cyc <= 1'b0; |
end |
end |
|
|
initial r_nvalid = 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset |
r_nvalid <= 0; |
else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache))) |
r_nvalid <= 0; |
else if ((~o_wb_cyc)&&(w_running_out_of_cache)) |
r_nvalid[LGCACHELEN:(LGCACHELEN-2)] |
<= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111; |
// i.e. - (1<<(LGCACHELEN-2)); |
else if ((o_wb_cyc)&&(i_wb_ack)) |
r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1; |
|
always @(posedge i_clk) |
if (i_clear_cache) |
r_cache_base <= i_pc; |
else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds) |
||(w_ran_off_end_of_cache))) |
r_cache_base <= (i_new_pc) ? i_pc : r_addr; |
else if ((~o_wb_cyc)&&(w_running_out_of_cache)) |
r_cache_base[(AW-1):(LGCACHELEN-2)] |
<= r_cache_base[(AW-1):(LGCACHELEN-2)] |
+ {{(AW-LGCACHELEN+1){1'b0}},1'b1}; |
// i.e. + (1<<(LGCACHELEN-2)); |
|
always @(posedge i_clk) |
if (i_clear_cache) |
r_cache_offset <= 0; |
else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds) |
||(w_ran_off_end_of_cache))) |
r_cache_offset <= 0; |
else if ((~o_wb_cyc)&&(w_running_out_of_cache)) |
r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01; |
assign w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} }; |
|
always @(posedge i_clk) |
if (i_clear_cache) |
o_wb_addr <= i_pc; |
else if ((o_wb_cyc)&&(w_pc_out_of_bounds)) |
begin |
if (i_wb_ack) |
o_wb_addr <= r_cache_base + bus_nvalid+1; |
else |
o_wb_addr <= r_cache_base + bus_nvalid; |
end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds) |
||(w_ran_off_end_of_cache))) |
o_wb_addr <= (i_new_pc) ? i_pc : r_addr; |
else if ((o_wb_stb)&&(~i_wb_stall)) // && o_wb_cyc |
o_wb_addr <= o_wb_addr + 1; |
|
initial r_acks_waiting = 0; |
always @(posedge i_clk) |
if (~o_wb_cyc) |
r_acks_waiting <= 0; |
// o_wb_cyc *must* be true for all following |
else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc) |
r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1}; |
else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc) |
r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1; |
|
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset] |
<= i_wb_data; |
|
initial r_addr_set = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
r_addr_set <= 1'b0; |
else if (i_new_pc) |
r_addr_set <= 1'b1; |
|
// Now, read from the cache |
wire w_cv; // Cache valid, address is in the cache |
reg r_cv; |
assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base) |
&&(r_addr-r_cache_base < bus_nvalid)); |
always @(posedge i_clk) |
r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv))); |
assign o_v = (r_cv)&&(~i_new_pc); |
|
always @(posedge i_clk) |
if (i_new_pc) |
r_addr <= i_pc; |
else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) ) |
r_addr <= r_addr + {{(AW-1){1'b0}},1'b1}; |
|
wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base; |
assign c_cache_base = r_cache_base[(LGCACHELEN-1):0]; |
assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset; |
always @(posedge i_clk) |
if ((~o_v)||((i_stall_n)&&(o_v))) |
o_i <= cache[c_rdaddr]; |
always @(posedge i_clk) |
if ((~o_v)||((i_stall_n)&&(o_v))) |
o_pc <= r_addr; |
|
reg [(AW-1):0] ill_address; |
initial ill_address = 0; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_err)) |
ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting}; |
|
assign o_illegal = (o_pc == ill_address); |
|
|
endmodule |
/cpu/zipsystem.v
0,0 → 1,802
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipsystem.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This portion of the ZIP CPU implements a number of soft |
// peripherals to the CPU nearby its CORE. The functionality |
// sits on the data bus, and does not include any true |
// external hardware peripherals. The peripherals included here |
// include: |
// |
// |
// Local interrupt controller--for any/all of the interrupts generated |
// here. This would include a pin for interrupts generated |
// elsewhere, so this interrupt controller could be a master |
// handling all interrupts. My interrupt controller would work |
// for this purpose. |
// |
// The ZIP-CPU supports only one interrupt because, as I understand |
// modern systems (Linux), they tend to send all interrupts to the |
// same interrupt vector anyway. Hence, that's what we do here. |
// |
// Bus Error interrupts -- generates an interrupt any time the wishbone |
// bus produces an error on a given access, for whatever purpose |
// also records the address on the bus at the time of the error. |
// |
// Trap instructions |
// Writing to this "register" will always create an interrupt. |
// After the interrupt, this register may be read to see what |
// value had been written to it. |
// |
// Bit reverse register ... ? |
// |
// (Potentially an eventual floating point co-processor ...) |
// |
// Real-time clock |
// |
// Interval timer(s) (Count down from fixed value, and either stop on |
// zero, or issue an interrupt and restart automatically on zero) |
// These can be implemented as watchdog timers if desired--the |
// only difference is that a watchdog timer's interrupt feeds the |
// reset line instead of the processor interrupt line. |
// |
// Watch-dog timer: this is the same as an interval timer, only it's |
// interrupt/time-out line is wired to the reset line instead of |
// the interrupt line of the CPU. |
// |
// ROM Memory map |
// Set a register to control this map, and a DMA will begin to |
// fill this memory from a slower FLASH. Once filled, accesses |
// will be from this memory instead of |
// |
// |
// Doing some market comparison, let's look at what peripherals a TI |
// MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC, |
// Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL, |
// brown-out-reset(s), real-time-clocks, temperature sensors, USB ports, |
// Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O, |
// watchdog-timers, |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
`include "cpudefs.v" |
// |
// While I hate adding delays to any bus access, this next delay is required |
// to make timing close in my Basys-3 design. |
`define DELAY_DBG_BUS |
// On my previous version, I needed to add a delay to access the external |
// bus. Activate the define below and that delay will be put back into place. |
// This particular version no longer needs the delay in order to run at |
// 100 MHz. Timing indicates I may even run this at 250 MHz without the |
// delay too, so we're doing better. To get rid of this, I placed the logic |
// determining whether or not I was accessing the local system bus one clock |
// earlier, or into the memops.v file. This also required my wishbone bus |
// arbiter to maintain the bus selection as well, so that got updated ... |
// you get the picture. But, the bottom line is that I no longer need this |
// delay. |
// |
// `define DELAY_EXT_BUS // Required no longer! |
// |
// |
// If space is tight, you might not wish to have your performance and |
// accounting counters, so let's make those optional here |
// Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU) |
// When including counters, |
// Slice LUTs ZipSystem ZipCPU |
// With Counters 3315 2432 |
// Without Counters 2796 2046 |
|
// |
// Now, where am I placing all of my peripherals? |
`define PERIPHBASE 32'hc0000000 |
`define INTCTRL 5'h0 // |
`define WATCHDOG 5'h1 // Interrupt generates reset signal |
`define BUSWATCHDOG 5'h2 // Sets IVEC[0] |
`define CTRINT 5'h3 // Sets IVEC[5] |
`define TIMER_A 5'h4 // Sets IVEC[4] |
`define TIMER_B 5'h5 // Sets IVEC[3] |
`define TIMER_C 5'h6 // Sets IVEC[2] |
`define JIFFIES 5'h7 // Sets IVEC[1] |
|
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
`define MSTR_TASK_CTR 5'h08 |
`define MSTR_MSTL_CTR 5'h09 |
`define MSTR_PSTL_CTR 5'h0a |
`define MSTR_INST_CTR 5'h0b |
`define USER_TASK_CTR 5'h0c |
`define USER_MSTL_CTR 5'h0d |
`define USER_PSTL_CTR 5'h0e |
`define USER_INST_CTR 5'h0f |
`endif |
|
// Although I have a hole at 5'h2, the DMA controller requires four wishbone |
// addresses, therefore we place it by itself and expand our address bus |
// width here by another bit. |
`define DMAC 5'h10 |
|
// `define RTC_CLOCK 32'hc0000008 // A global something |
// `define BITREV 32'hc0000003 |
// |
// DBGCTRL |
// 10 HALT |
// 9 HALT(ED) |
// 8 STEP (W=1 steps, and returns to halted) |
// 7 INTERRUPT-FLAG |
// 6 RESET_FLAG |
// ADDRESS: |
// 5 PERIPHERAL-BIT |
// [4:0] REGISTER-ADDR |
// DBGDATA |
// read/writes internal registers |
// |
// |
// |
module zipsystem(i_clk, i_rst, |
// Wishbone master interface from the CPU |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, |
// Incoming interrupts |
i_ext_int, |
// Our one outgoing interrupt |
o_ext_int, |
// Wishbone slave interface for debugging purposes |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data |
`ifdef DEBUG_SCOPE |
, o_cpu_debug |
`endif |
); |
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24, |
LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1, |
`ifdef OPT_MULTIPLY |
IMPLEMENT_MPY = 1, |
`else |
IMPLEMENT_MPY = 0, |
`endif |
`ifdef OPT_DIVIDE |
IMPLEMENT_DIVIDE=1, |
`else |
IMPLEMENT_DIVIDE=0, |
`endif |
`ifdef OPT_IMPLEMENT_FPU |
IMPLEMENT_FPU=1, |
`else |
IMPLEMENT_FPU=0, |
`endif |
IMPLEMENT_LOCK=1, |
// Derived parameters |
AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
// Wishbone master |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
// Incoming interrupts |
input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int; |
// Outgoing interrupt |
output wire o_ext_int; |
// Wishbone slave |
input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr; |
input [31:0] i_dbg_data; |
output wire o_dbg_ack; |
output wire o_dbg_stall; |
output wire [31:0] o_dbg_data; |
// |
`ifdef DEBUG_SCOPE |
output wire [31:0] o_cpu_debug; |
`endif |
|
wire [31:0] ext_idata; |
|
// Handle our interrupt vector generation/coordination |
wire [14:0] main_int_vector, alt_int_vector; |
wire ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int; |
wire mtc_int, moc_int, mpc_int, mic_int, |
utc_int, uoc_int, upc_int, uic_int; |
generate |
if (EXTERNAL_INTERRUPTS < 9) |
assign main_int_vector = { {(9-EXTERNAL_INTERRUPTS){1'b0}}, |
i_ext_int, ctri_int, |
tma_int, tmb_int, tmc_int, |
jif_int, dmac_int }; |
else |
assign main_int_vector = { i_ext_int[8:0], ctri_int, |
tma_int, tmb_int, tmc_int, |
jif_int, dmac_int }; |
endgenerate |
generate |
if (EXTERNAL_INTERRUPTS <= 9) |
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
assign alt_int_vector = { 7'h00, |
mtc_int, moc_int, mpc_int, mic_int, |
utc_int, uoc_int, upc_int, uic_int }; |
`else |
assign alt_int_vector = { 15'h00 }; |
`endif |
else |
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
assign alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}}, |
i_ext_int[(EXTERNAL_INTERRUPTS-1):9], |
mtc_int, moc_int, mpc_int, mic_int, |
utc_int, uoc_int, upc_int, uic_int }; |
`else |
assign alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}}, |
i_ext_int[(EXTERNAL_INTERRUPTS-1):9] }; |
`endif |
endgenerate |
|
|
// Delay the debug port by one clock, to meet timing requirements |
wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall; |
wire [31:0] dbg_idata, dbg_odata; |
reg dbg_ack; |
`ifdef DELAY_DBG_BUS |
wire dbg_err, no_dbg_err; |
assign dbg_err = 1'b0; |
busdelay #(1,32) wbdelay(i_clk, |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err, |
dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, |
dbg_ack, dbg_stall, dbg_odata, dbg_err); |
`else |
assign dbg_cyc = i_dbg_cyc; |
assign dbg_stb = i_dbg_stb; |
assign dbg_we = i_dbg_we; |
assign dbg_addr = i_dbg_addr; |
assign dbg_idata = i_dbg_data; |
assign o_dbg_ack = dbg_ack; |
assign o_dbg_stall = dbg_stall; |
assign o_dbg_data = dbg_odata; |
`endif |
|
// |
// |
// |
wire sys_cyc, sys_stb, sys_we; |
wire [4:0] sys_addr; |
wire [(AW-1):0] cpu_addr; |
wire [31:0] sys_data; |
wire sys_ack, sys_stall; |
|
// |
// The external debug interface |
// |
// We offer only a limited interface here, requiring a pre-register |
// write to set the local address. This interface allows access to |
// the Zip System on a debug basis only, and not to the rest of the |
// wishbone bus. Further, to access these registers, the control |
// register must first be accessed to both stop the CPU and to |
// set the following address in question. Hence all accesses require |
// two accesses: write the address to the control register (and halt |
// the CPU if not halted), then read/write the data from the data |
// register. |
// |
wire cpu_break, dbg_cmd_write; |
reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache; |
reg [5:0] cmd_addr; |
wire [3:0] cpu_dbg_cc; |
assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr); |
// |
initial cmd_reset = 1'b1; |
always @(posedge i_clk) |
cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6])); |
// |
initial cmd_halt = 1'b1; |
always @(posedge i_clk) |
if (i_rst) |
cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0; |
else if (dbg_cmd_write) |
cmd_halt <= ((dbg_idata[10])||(dbg_idata[8])); |
else if ((cmd_step)||(cpu_break)) |
cmd_halt <= 1'b1; |
|
always @(posedge i_clk) |
cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write) |
&&((dbg_idata[11])||(dbg_idata[6])); |
// |
initial cmd_step = 1'b0; |
always @(posedge i_clk) |
cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]); |
// |
always @(posedge i_clk) |
if (dbg_cmd_write) |
cmd_addr <= dbg_idata[5:0]; |
|
wire cpu_reset; |
assign cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst); |
|
wire cpu_halt, cpu_dbg_stall; |
assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step)); |
wire [31:0] pic_data; |
wire [31:0] cmd_data; |
// Values: |
// 0x0003f -> cmd_addr mask |
// 0x00040 -> reset |
// 0x00080 -> PIC interrrupt pending |
// 0x00100 -> cmd_step |
// 0x00200 -> cmd_stall |
// 0x00400 -> cmd_halt |
// 0x00800 -> cmd_clear_pf_cache |
// 0x01000 -> cc.sleep |
// 0x02000 -> cc.gie |
// 0x04000 -> External (PIC) interrupt line is high |
// Other external interrupts follow |
generate |
if (EXTERNAL_INTERRUPTS < 16) |
assign cmd_data = { {(16-EXTERNAL_INTERRUPTS){1'b0}}, |
i_ext_int, |
cpu_dbg_cc, // 4 bits |
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0, |
pic_data[15], cpu_reset, cmd_addr }; |
else |
assign cmd_data = { i_ext_int[15:0], cpu_dbg_cc, |
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0, |
pic_data[15], cpu_reset, cmd_addr }; |
endgenerate |
|
wire cpu_gie; |
assign cpu_gie = cpu_dbg_cc[1]; |
|
`ifdef USE_TRAP |
// |
// The TRAP peripheral |
// |
wire trap_ack, trap_stall, trap_int; |
wire [31:0] trap_data; |
ziptrap trapp(i_clk, |
sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we, |
sys_data, |
trap_ack, trap_stall, trap_data, trap_int); |
`endif |
|
// |
// The WATCHDOG Timer |
// |
wire wdt_ack, wdt_stall, wdt_reset; |
wire [31:0] wdt_data; |
ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt, |
sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we, |
sys_data, |
wdt_ack, wdt_stall, wdt_data, wdt_reset); |
|
// |
// Position two, a second watchdog timer--this time for the wishbone |
// bus, in order to tell/find wishbone bus lockups. In its current |
// configuration, it cannot be configured and all bus accesses must |
// take less than the number written to this register. |
// |
reg wdbus_ack; |
reg [(AW-1):0] r_wdbus_data; |
wire [31:0] wdbus_data; |
wire [14:0] wdbus_ignored_data; |
wire reset_wdbus_timer, wdbus_int; |
assign reset_wdbus_timer = ((o_wb_cyc)&&((o_wb_stb)||(i_wb_ack))); |
wbwatchdog #(14) watchbus(i_clk,(cpu_reset)||(reset_wdbus_timer), |
o_wb_cyc, 14'h2000, wdbus_int); |
initial r_wdbus_data = 0; |
always @(posedge i_clk) |
if ((wdbus_int)||(cpu_ext_err)) |
r_wdbus_data = o_wb_addr; |
assign wdbus_data = { {(32-AW){1'b0}}, r_wdbus_data }; |
initial wdbus_ack = 1'b0; |
always @(posedge i_clk) |
wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02)); |
|
// Counters -- for performance measurement and accounting |
// |
// Here's the stuff we'll be counting .... |
// |
wire cpu_op_stall, cpu_pf_stall, cpu_i_count; |
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
// |
// The master counters will, in general, not be reset. They'll be used |
// for an overall counter. |
// |
// Master task counter |
wire mtc_ack, mtc_stall; |
wire [31:0] mtc_data; |
zipcounter mtask_ctr(i_clk, (~cpu_halt), sys_cyc, |
(sys_stb)&&(sys_addr == `MSTR_TASK_CTR), |
sys_we, sys_data, |
mtc_ack, mtc_stall, mtc_data, mtc_int); |
|
// Master Operand Stall counter |
wire moc_ack, moc_stall; |
wire [31:0] moc_data; |
zipcounter mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc, |
(sys_stb)&&(sys_addr == `MSTR_MSTL_CTR), |
sys_we, sys_data, |
moc_ack, moc_stall, moc_data, moc_int); |
|
// Master PreFetch-Stall counter |
wire mpc_ack, mpc_stall; |
wire [31:0] mpc_data; |
zipcounter mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc, |
(sys_stb)&&(sys_addr == `MSTR_PSTL_CTR), |
sys_we, sys_data, |
mpc_ack, mpc_stall, mpc_data, mpc_int); |
|
// Master Instruction counter |
wire mic_ack, mic_stall; |
wire [31:0] mic_data; |
zipcounter mins_ctr(i_clk,(cpu_i_count), sys_cyc, |
(sys_stb)&&(sys_addr == `MSTR_INST_CTR), |
sys_we, sys_data, |
mic_ack, mic_stall, mic_data, mic_int); |
|
// |
// The user counters are different from those of the master. They will |
// be reset any time a task is given control of the CPU. |
// |
// User task counter |
wire utc_ack, utc_stall; |
wire [31:0] utc_data; |
zipcounter utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc, |
(sys_stb)&&(sys_addr == `USER_TASK_CTR), |
sys_we, sys_data, |
utc_ack, utc_stall, utc_data, utc_int); |
|
// User Op-Stall counter |
wire uoc_ack, uoc_stall; |
wire [31:0] uoc_data; |
zipcounter umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc, |
(sys_stb)&&(sys_addr == `USER_MSTL_CTR), |
sys_we, sys_data, |
uoc_ack, uoc_stall, uoc_data, uoc_int); |
|
// User PreFetch-Stall counter |
wire upc_ack, upc_stall; |
wire [31:0] upc_data; |
zipcounter upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc, |
(sys_stb)&&(sys_addr == `USER_PSTL_CTR), |
sys_we, sys_data, |
upc_ack, upc_stall, upc_data, upc_int); |
|
// User instruction counter |
wire uic_ack, uic_stall; |
wire [31:0] uic_data; |
zipcounter uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc, |
(sys_stb)&&(sys_addr == `USER_INST_CTR), |
sys_we, sys_data, |
uic_ack, uic_stall, uic_data, uic_int); |
|
// A little bit of pre-cleanup (actr = accounting counters) |
wire actr_ack, actr_stall; |
wire [31:0] actr_data; |
assign actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack) |
|(utc_ack | uoc_ack | upc_ack | uic_ack)); |
assign actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall) |
|(utc_stall | uoc_stall | upc_stall|uic_stall)); |
assign actr_data = ((mtc_ack) ? mtc_data |
: ((moc_ack) ? moc_data |
: ((mpc_ack) ? mpc_data |
: ((mic_ack) ? mic_data |
: ((utc_ack) ? utc_data |
: ((uoc_ack) ? uoc_data |
: ((upc_ack) ? upc_data |
: uic_data))))))); |
`else // INCLUDE_ACCOUNTING_COUNTERS |
reg actr_ack; |
wire actr_stall; |
wire [31:0] actr_data; |
assign actr_stall = 1'b0; |
assign actr_data = 32'h0000; |
|
assign mtc_int = 1'b0; |
assign moc_int = 1'b0; |
assign mpc_int = 1'b0; |
assign mic_int = 1'b0; |
assign utc_int = 1'b0; |
assign uoc_int = 1'b0; |
assign upc_int = 1'b0; |
assign uic_int = 1'b0; |
|
always @(posedge i_clk) |
actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01); |
`endif // INCLUDE_ACCOUNTING_COUNTERS |
|
// |
// The DMA Controller |
// |
wire dmac_stb, dc_err; |
wire [31:0] dmac_data; |
wire dmac_ack, dmac_stall; |
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall; |
wire [31:0] dc_data; |
wire [(AW-1):0] dc_addr; |
wire cpu_gbl_cyc; |
assign dmac_stb = (sys_stb)&&(sys_addr[4]); |
`ifdef INCLUDE_DMA_CONTROLLER |
wbdmac #(AW) dma_controller(i_clk, |
sys_cyc, dmac_stb, sys_we, |
sys_addr[1:0], sys_data, |
dmac_ack, dmac_stall, dmac_data, |
// Need the outgoing DMAC wishbone bus |
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, |
dc_ack, dc_stall, ext_idata, dc_err, |
// External device interrupts |
{ 1'b0, alt_int_vector, 1'b0, |
main_int_vector[14:1], 1'b0 }, |
// DMAC interrupt, for upon completion |
dmac_int); |
// Whether or not the CPU wants the bus, and |
// thus we must kick the DMAC off. |
// However, the logic required for this |
// override never worked well, so here |
// we just don't use it. |
// cpu_gbl_cyc); |
`else |
reg r_dmac_ack; |
always @(posedge i_clk) |
r_dmac_ack <= (sys_cyc)&&(dmac_stb); |
assign dmac_ack = r_dmac_ack; |
assign dmac_data = 32'h000; |
assign dmac_stall = 1'b0; |
|
assign dc_cyc = 1'b0; |
assign dc_stb = 1'b0; |
assign dc_we = 1'b0; |
assign dc_addr = { (AW) {1'b0} }; |
assign dc_data = 32'h00; |
|
assign dmac_int = 1'b0; |
`endif |
|
wire ctri_sel, ctri_stall; |
reg ctri_ack; |
wire [31:0] ctri_data; |
assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT); |
always @(posedge i_clk) |
ctri_ack <= ctri_sel; |
assign ctri_stall = 1'b0; |
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
// |
// Counter Interrupt controller |
// |
generate |
if (EXTERNAL_INTERRUPTS <= 9) |
begin |
icontrol #(8) ctri(i_clk, cpu_reset, (ctri_sel), |
sys_data, ctri_data, alt_int_vector[7:0], |
ctri_int); |
end else begin |
icontrol #(8+(EXTERNAL_INTERRUPTS-9)) |
ctri(i_clk, cpu_reset, (ctri_sel), |
sys_data, ctri_data, |
alt_int_vector[(EXTERNAL_INTERRUPTS-1):0], |
ctri_int); |
end endgenerate |
|
`else // INCLUDE_ACCOUNTING_COUNTERS |
|
generate |
if (EXTERNAL_INTERRUPTS <= 9) |
begin |
assign ctri_stall = 1'b0; |
assign ctri_data = 32'h0000; |
assign ctri_int = 1'b0; |
end else begin |
icontrol #(EXTERNAL_INTERRUPTS-9) |
ctri(i_clk, cpu_reset, (ctri_sel), |
sys_data, ctri_data, |
alt_int_vector[(EXTERNAL_INTERRUPTS-10):0], |
ctri_int); |
end endgenerate |
`endif // INCLUDE_ACCOUNTING_COUNTERS |
|
|
// |
// Timer A |
// |
wire tma_ack, tma_stall; |
wire [31:0] tma_data; |
ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt, |
sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we, |
sys_data, |
tma_ack, tma_stall, tma_data, tma_int); |
|
// |
// Timer B |
// |
wire tmb_ack, tmb_stall; |
wire [31:0] tmb_data; |
ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt, |
sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we, |
sys_data, |
tmb_ack, tmb_stall, tmb_data, tmb_int); |
|
// |
// Timer C |
// |
wire tmc_ack, tmc_stall; |
wire [31:0] tmc_data; |
ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt, |
sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we, |
sys_data, |
tmc_ack, tmc_stall, tmc_data, tmc_int); |
|
// |
// JIFFIES |
// |
wire jif_ack, jif_stall; |
wire [31:0] jif_data; |
zipjiffies jiffies(i_clk, ~cmd_halt, |
sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we, |
sys_data, |
jif_ack, jif_stall, jif_data, jif_int); |
|
// |
// The programmable interrupt controller peripheral |
// |
wire pic_interrupt; |
generate |
if (EXTERNAL_INTERRUPTS < 9) |
begin |
icontrol #(6+EXTERNAL_INTERRUPTS) pic(i_clk, cpu_reset, |
(sys_cyc)&&(sys_stb)&&(sys_we) |
&&(sys_addr==`INTCTRL), |
sys_data, pic_data, |
main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], pic_interrupt); |
end else begin |
icontrol #(15) pic(i_clk, cpu_reset, |
(sys_cyc)&&(sys_stb)&&(sys_we) |
&&(sys_addr==`INTCTRL), |
sys_data, pic_data, |
main_int_vector[14:0], pic_interrupt); |
end endgenerate |
|
wire pic_stall; |
assign pic_stall = 1'b0; |
reg pic_ack; |
always @(posedge i_clk) |
pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL); |
|
// |
// The CPU itself |
// |
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_dbg_we; |
wire [31:0] cpu_data, wb_data; |
wire cpu_ack, cpu_stall, cpu_err; |
wire [31:0] cpu_dbg_data; |
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5]) |
&&(dbg_we)&&(dbg_addr)); |
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE, IMPLEMENT_MPY, |
IMPLEMENT_DIVIDE, IMPLEMENT_FPU, IMPLEMENT_LOCK) |
thecpu(i_clk, cpu_reset, pic_interrupt, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
dbg_idata, cpu_dbg_stall, cpu_dbg_data, |
cpu_dbg_cc, cpu_break, |
cpu_gbl_cyc, cpu_gbl_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_addr, cpu_data, |
cpu_ack, cpu_stall, wb_data, |
cpu_err, |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
`ifdef DEBUG_SCOPE |
, o_cpu_debug |
`endif |
); |
|
// Now, arbitrate the bus ... first for the local peripherals |
// For the debugger to have access to the local system bus, the |
// following must be true: |
// (dbg_cyc) The debugger must request the bus |
// (~cpu_lcl_cyc) The CPU cannot be using it (CPU gets priority) |
// (dbg_addr) The debugger must be requesting its data |
// register, not just the control register |
// and one of two other things. Either |
// ((cpu_halt)&&(~cpu_dbg_stall)) the CPU is completely halted, |
// or |
// (~cmd_addr[5]) we are trying to read a CPU register |
// while in motion. Let the user beware that, |
// by not waiting for the CPU to fully halt, |
// his results may not be what he expects. |
// |
wire sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr)) |
&&(((cpu_halt)&&(~cpu_dbg_stall)) |
||(~cmd_addr[5])); |
assign sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc); |
assign sys_stb = (cpu_lcl_cyc) |
? (cpu_lcl_stb) |
: ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5])); |
|
assign sys_we = (cpu_lcl_cyc) ? cpu_we : dbg_we; |
assign sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0]; |
assign sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata; |
|
// Return debug response values |
assign dbg_odata = (~dbg_addr)?cmd_data |
:((~cmd_addr[5])?cpu_dbg_data : wb_data); |
initial dbg_ack = 1'b0; |
always @(posedge i_clk) |
dbg_ack <= (dbg_cyc)&&(~dbg_stall); |
assign dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr); |
|
// Now for the external wishbone bus |
// Need to arbitrate between the flash cache and the CPU |
// The way this works, though, the CPU will stall once the flash |
// cache gets access to the bus--the CPU will be stuck until the |
// flash cache is finished with the bus. |
wire ext_cyc, ext_stb, ext_we, ext_err; |
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall, |
cpu_ext_err; |
wire [(AW-1):0] ext_addr; |
wire [31:0] ext_odata; |
wbpriarbiter #(32,AW) dmacvcpu(i_clk, |
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, |
cpu_ext_ack, cpu_ext_stall, cpu_ext_err, |
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, |
dc_ack, dc_stall, dc_err, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, |
ext_ack, ext_stall, ext_err); |
|
`ifdef DELAY_EXT_BUS |
busdelay #(AW,32) extbus(i_clk, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, |
ext_ack, ext_stall, ext_idata, ext_err, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int)); |
`else |
assign o_wb_cyc = ext_cyc; |
assign o_wb_stb = ext_stb; |
assign o_wb_we = ext_we; |
assign o_wb_addr = ext_addr; |
assign o_wb_data = ext_odata; |
assign ext_ack = i_wb_ack; |
assign ext_stall = i_wb_stall; |
assign ext_idata = i_wb_data; |
assign ext_err = (i_wb_err)||(wdbus_int); |
`endif |
|
wire tmr_ack; |
assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack); |
wire [31:0] tmr_data; |
assign tmr_data = (tma_ack)?tma_data |
:(tmb_ack ? tmb_data |
:(tmc_ack ? tmc_data |
:jif_data)); |
assign wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data) |
:((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data) |
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data) |
:((wdbus_ack)?wdbus_data:(ext_idata)))); |
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall |
| wdt_stall | ctri_stall | actr_stall |
| pic_stall | dmac_stall); |
assign cpu_stall = (sys_stall)|(cpu_ext_stall); |
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack); |
assign cpu_ack = (sys_ack)||(cpu_ext_ack); |
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc); |
|
assign o_ext_int = (cmd_halt) && (~cpu_stall); |
|
endmodule |
/cpu/busdelay.v
0,0 → 1,101
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: busdelay.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Delay any access to the wishbone bus by a single clock. |
// |
// When the first Zip System would not meet the timing requirements of |
// the board it was placed upon, this bus delay was added to help out. |
// It may no longer be necessary, having cleaned some other problems up |
// first, but it will remain here as a means of alleviating timing |
// problems. |
// |
// The specific problem takes place on the stall line: a wishbone master |
// *must* know on the first clock whether or not the bus will stall. |
// |
// |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module busdelay(i_clk, |
// The input bus |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err, |
// The delayed bus |
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data, |
i_dly_ack, i_dly_stall, i_dly_data, i_dly_err); |
parameter AW=32, DW=32; |
input i_clk; |
// Input/master bus |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(AW-1):0] i_wb_addr; |
input [(DW-1):0] i_wb_data; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(DW-1):0] o_wb_data; |
output wire o_wb_err; |
// Delayed bus |
output reg o_dly_cyc, o_dly_stb, o_dly_we; |
output reg [(AW-1):0] o_dly_addr; |
output reg [(DW-1):0] o_dly_data; |
input i_dly_ack; |
input i_dly_stall; |
input [(DW-1):0] i_dly_data; |
input i_dly_err; |
|
initial o_dly_cyc = 1'b0; |
initial o_dly_stb = 1'b0; |
|
always @(posedge i_clk) |
o_dly_cyc <= i_wb_cyc; |
// Add the i_wb_cyc criteria here, so we can simplify the o_wb_stall |
// criteria below, which would otherwise *and* these two. |
always @(posedge i_clk) |
if (~o_wb_stall) |
o_dly_stb <= ((i_wb_cyc)&&(i_wb_stb)); |
always @(posedge i_clk) |
if (~o_wb_stall) |
o_dly_we <= i_wb_we; |
always @(posedge i_clk) |
if (~o_wb_stall) |
o_dly_addr<= i_wb_addr; |
always @(posedge i_clk) |
if (~o_wb_stall) |
o_dly_data <= i_wb_data; |
always @(posedge i_clk) |
o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc); |
always @(posedge i_clk) |
o_wb_data <= i_dly_data; |
|
// Our only non-delayed line, yet still really delayed. Perhaps |
// there's a way to register this? |
// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such? |
// assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc |
assign o_wb_stall = ((i_dly_stall)&&(o_dly_stb));//&&o_cyc |
assign o_wb_err = i_dly_err; |
|
endmodule |
/cpu/cpuops.v
0,0 → 1,200
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpuops.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This supports the instruction set reordering of operations |
// created by the second generation instruction set, as well as |
// the new operations of POPC (population count) and BREV (bit reversal). |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid, |
o_illegal, o_busy); |
parameter IMPLEMENT_MPY = 1; |
input i_clk, i_rst, i_ce; |
input [3:0] i_op; |
input [31:0] i_a, i_b; |
input i_valid; |
output reg [31:0] o_c; |
output wire [3:0] o_f; |
output reg o_valid; |
output wire o_illegal; |
output wire o_busy; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result; |
assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}} |
: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR |
assign w_lsr_result = (|i_b[31:5])? 33'h00 |
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR |
|
// Bit reversal pre-logic |
wire [31:0] w_brev_result; |
genvar k; |
generate |
for(k=0; k<32; k=k+1) |
begin : bit_reversal_cpuop |
assign w_brev_result[k] = i_b[31-k]; |
end endgenerate |
|
// Popcount pre-logic |
wire [31:0] w_popc_result; |
assign w_popc_result[5:0]= |
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]}) |
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]}) |
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]}) |
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]}) |
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]}) |
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]}) |
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]}) |
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]}); |
assign w_popc_result[31:6] = 26'h00; |
|
// Prelogic for our flags registers |
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD |
||(i_op == 4'h6) // LSL |
||(i_op == 4'h5)); // LSR |
|
|
// A 4-way multiplexer can be done in one 6-LUT. |
// A 16-way multiplexer can therefore be done in 4x 6-LUT's with |
// the Xilinx multiplexer fabric that follows. |
// Given that we wish to apply this multiplexer approach to 33-bits, |
// this will cost a minimum of 132 6-LUTs. |
generate |
if (IMPLEMENT_MPY == 0) |
begin |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB |
4'b0001: o_c <= i_a & i_b; // BTST/And |
4'b0010:{c,o_c } <= i_a + i_b; // Add |
4'b0011: o_c <= i_a | i_b; // Or |
4'b0100: o_c <= i_a ^ i_b; // Xor |
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
// 4'h1010: The unimplemented MPYU, |
// 4'h1011: and here for the unimplemented MPYS |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
default: o_c <= i_b; // MOV, LDI |
endcase |
end |
|
assign o_busy = 1'b0; |
|
reg r_illegal; |
always @(posedge i_clk) |
r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4)); |
assign o_illegal = r_illegal; |
end else begin |
// |
// Multiply pre-logic |
// |
wire signed [16:0] w_mpy_a_input, w_mpy_b_input; |
wire [33:0] w_mpy_result; |
reg [31:0] r_mpy_result; |
assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] }; |
assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] }; |
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input; |
always @(posedge i_clk) |
if (i_ce) |
r_mpy_result = w_mpy_result[31:0]; |
|
// |
// The master ALU case statement |
// |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB |
4'b0001: o_c <= i_a & i_b; // BTST/And |
4'b0010:{c,o_c } <= i_a + i_b; // Add |
4'b0011: o_c <= i_a | i_b; // Or |
4'b0100: o_c <= i_a ^ i_b; // Xor |
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'b1010: o_c <= r_mpy_result; // MPYU |
4'b1011: o_c <= r_mpy_result; // MPYS |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
default: o_c <= i_b; // MOV, LDI |
endcase |
end else if (r_busy) |
o_c <= r_mpy_result; |
|
reg r_busy; |
initial r_busy = 1'b0; |
always @(posedge i_clk) |
r_busy <= (~i_rst)&&(i_ce)&&(i_valid) |
&&(i_op[3:1] == 3'h5); |
|
assign o_busy = r_busy; |
|
assign o_illegal = 1'b0; |
end endgenerate |
|
assign z = (o_c == 32'h0000); |
assign n = (o_c[31]); |
assign v = (set_ovfl)&&(pre_sign != o_c[31]); |
|
assign o_f = { v, n, c, z }; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
o_valid <= 1'b0; |
else |
o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5) |
||(o_busy); |
endmodule |
/cpu/zipcpu.v
0,0 → 1,1656
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcpu.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This is the top level module holding the core of the Zip CPU |
// together. The Zip CPU is designed to be as simple as possible. |
// (actual implementation aside ...) The instruction set is about as |
// RISC as you can get, there are only 16 instruction types supported. |
// Please see the accompanying spec.pdf file for a description of these |
// instructions. |
// |
// All instructions are 32-bits wide. All bus accesses, both address and |
// data, are 32-bits over a wishbone bus. |
// |
// The Zip CPU is fully pipelined with the following pipeline stages: |
// |
// 1. Prefetch, returns the instruction from memory. |
// |
// 2. Instruction Decode |
// |
// 3. Read Operands |
// |
// 4. Apply Instruction |
// |
// 4. Write-back Results |
// |
// Further information about the inner workings of this CPU may be |
// found in the spec.pdf file. (The documentation within this file |
// had become out of date and out of sync with the spec.pdf, so look |
// to the spec.pdf for accurate and up to date information.) |
// |
// |
// In general, the pipelining is controlled by three pieces of logic |
// per stage: _ce, _stall, and _valid. _valid means that the stage |
// holds a valid instruction. _ce means that the instruction from the |
// previous stage is to move into this one, and _stall means that the |
// instruction from the previous stage may not move into this one. |
// The difference between these control signals allows individual stages |
// to propagate instructions independently. In general, the logic works |
// as: |
// |
// |
// assign (n)_ce = (n-1)_valid && (~(n)_stall) |
// |
// |
// always @(posedge i_clk) |
// if ((i_rst)||(clear_pipeline)) |
// (n)_valid = 0 |
// else if (n)_ce |
// (n)_valid = 1 |
// else if (n+1)_ce |
// (n)_valid = 0 |
// |
// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) ) |
// || ( (n)_valid && (n+1)_stall ); |
// |
// and ... |
// |
// always @(posedge i_clk) |
// if (n)_ce |
// (n)_variable = ... whatever logic for this stage |
// |
// Note that a stage can stall even if no instruction is loaded into |
// it. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
// Slice LUTs ZipSystem ZipCPU |
// Single Fetching 2521 1734 |
// Pipelined fetching 2796 2046 |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error |
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero |
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error |
`define CPU_TRAP_BIT 9 // User TRAP has taken place |
`define CPU_ILL_BIT 8 // Illegal instruction |
`define CPU_BREAK_BIT 7 |
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions |
`define CPU_GIE_BIT 5 |
`define CPU_SLEEP_BIT 4 |
// Compile time defines |
// |
`include "cpudefs.v" |
// |
// |
module zipcpu(i_clk, i_rst, i_interrupt, |
// Debug interface |
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data, |
o_dbg_stall, o_dbg_reg, o_dbg_cc, |
o_break, |
// CPU interface to the wishbone bus |
o_wb_gbl_cyc, o_wb_gbl_stb, |
o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_err, |
// Accounting/CPU usage interface |
o_op_stall, o_pf_stall, o_i_count |
`ifdef DEBUG_SCOPE |
, o_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24, |
LGICACHE=6; |
`ifdef OPT_MULTIPLY |
parameter IMPLEMENT_MPY = 1; |
`else |
parameter IMPLEMENT_MPY = 0; |
`endif |
`ifdef OPT_DIVIDE |
parameter IMPLEMENT_DIVIDE = 1; |
`else |
parameter IMPLEMENT_DIVIDE = 0; |
`endif |
`ifdef OPT_IMPLEMENT_FPU |
parameter IMPLEMENT_FPU = 1, |
`else |
parameter IMPLEMENT_FPU = 0, |
`endif |
IMPLEMENT_LOCK=1; |
`ifdef OPT_EARLY_BRANCHING |
parameter EARLY_BRANCHING = 1; |
`else |
parameter EARLY_BRANCHING = 0; |
`endif |
parameter AW=ADDRESS_WIDTH; |
input i_clk, i_rst, i_interrupt; |
// Debug interface -- inputs |
input i_halt, i_clear_pf_cache; |
input [4:0] i_dbg_reg; |
input i_dbg_we; |
input [31:0] i_dbg_data; |
// Debug interface -- outputs |
output reg o_dbg_stall; |
output reg [31:0] o_dbg_reg; |
output reg [3:0] o_dbg_cc; |
output wire o_break; |
// Wishbone interface -- outputs |
output wire o_wb_gbl_cyc, o_wb_gbl_stb; |
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
// Wishbone interface -- inputs |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
// Accounting outputs ... to help us count stalls and usage |
output wire o_op_stall; |
output wire o_pf_stall; |
output wire o_i_count; |
// |
`ifdef DEBUG_SCOPE |
output reg [31:0] o_debug; |
`endif |
|
|
// Registers |
// |
// The distributed RAM style comment is necessary on the |
// SPARTAN6 with XST to prevent XST from oversimplifying the register |
// set and in the process ruining everything else. It basically |
// optimizes logic away, to where it no longer works. The logic |
// as described herein will work, this just makes sure XST implements |
// that logic. |
// |
(* ram_style = "distributed" *) |
reg [31:0] regset [0:31]; |
|
// Condition codes |
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
reg [3:0] flags, iflags; |
wire [13:0] w_uflags, w_iflags; |
reg trap, break_en, step, gie, sleep; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg ill_err_u, ill_err_i; |
`else |
wire ill_err_u, ill_err_i; |
`endif |
reg ibus_err_flag, ubus_err_flag; |
wire idiv_err_flag, udiv_err_flag; |
wire ifpu_err_flag, ufpu_err_flag; |
wire ihalt_phase, uhalt_phase; |
|
// The master chip enable |
wire master_ce; |
|
// |
// |
// PIPELINE STAGE #1 :: Prefetch |
// Variable declarations |
// |
reg [(AW-1):0] pf_pc; |
reg new_pc; |
wire clear_pipeline; |
assign clear_pipeline = new_pc || i_clear_pf_cache; |
|
wire dcd_stalled; |
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err; |
wire [(AW-1):0] pf_addr; |
wire [31:0] pf_data; |
wire [31:0] instruction; |
wire [(AW-1):0] instruction_pc; |
wire pf_valid, instruction_gie, pf_illegal; |
|
// |
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Variable declarations |
// |
// |
reg opvalid, opvalid_mem, opvalid_alu; |
reg opvalid_div, opvalid_fpu; |
wire op_stall, dcd_ce, dcd_phase; |
wire [3:0] dcdOp; |
wire [4:0] dcdA, dcdB, dcdR; |
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc; |
wire [3:0] dcdF; |
wire dcdR_wr, dcdA_rd, dcdB_rd, |
dcdALU, dcdM, dcdDV, dcdFP, |
dcdF_wr, dcd_gie, dcd_break, dcd_lock, |
dcd_pipe; |
reg r_dcdvalid; |
wire dcdvalid; |
wire [(AW-1):0] dcd_pc; |
wire [31:0] dcdI; |
wire dcd_zI; // true if dcdI == 0 |
wire dcdA_stall, dcdB_stall, dcdF_stall; |
|
wire dcd_illegal; |
wire dcd_early_branch; |
wire [(AW-1):0] dcd_branch_pc; |
|
|
// |
// |
// PIPELINE STAGE #3 :: Read Operands |
// Variable declarations |
// |
// |
// |
// Now, let's read our operands |
reg [4:0] alu_reg; |
reg [3:0] opn; |
reg [4:0] opR; |
reg [31:0] r_opA, r_opB; |
reg [(AW-1):0] op_pc; |
wire [31:0] w_opA, w_opB; |
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opR_cc, opF_wr, op_gie; |
wire [13:0] opFl; |
reg [5:0] r_opF; |
wire [7:0] opF; |
wire op_ce, op_phase; |
// Some pipeline control wires |
`ifdef OPT_PIPELINED |
reg opA_alu, opA_mem; |
reg opB_alu, opB_mem; |
`endif |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`endif |
reg op_break; |
wire op_lock; |
|
|
// |
// |
// PIPELINE STAGE #4 :: ALU / Memory |
// Variable declarations |
// |
// |
reg [(AW-1):0] alu_pc; |
reg alu_pc_valid; |
wire alu_phase; |
wire alu_ce, alu_stall; |
wire [31:0] alu_result; |
wire [3:0] alu_flags; |
wire alu_valid, alu_busy; |
wire set_cond; |
reg alu_wr, alF_wr, alu_gie; |
wire alu_illegal_op; |
wire alu_illegal; |
|
|
|
wire mem_ce, mem_stalled; |
`ifdef OPT_PIPELINED_BUS_ACCESS |
wire mem_pipe_stalled; |
`endif |
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err, |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we; |
wire [4:0] mem_wreg; |
|
wire mem_busy, mem_rdbusy; |
wire [(AW-1):0] mem_addr; |
wire [31:0] mem_data, mem_result; |
|
wire div_ce, div_error, div_busy, div_valid; |
wire [31:0] div_result; |
wire [3:0] div_flags; |
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
wire fpu_ce, fpu_error, fpu_busy, fpu_valid; |
wire [31:0] fpu_result; |
wire [3:0] fpu_flags; |
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
|
// |
// |
// PIPELINE STAGE #5 :: Write-back |
// Variable declarations |
// |
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc; |
wire [4:0] wr_reg_id; |
wire [31:0] wr_reg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
reg [(AW-1):0] upc, ipc; |
|
|
|
// |
// MASTER: clock enable. |
// |
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep); |
|
|
// |
// PIPELINE STAGE #1 :: Prefetch |
// Calculate stall conditions |
// |
// These are calculated externally, within the prefetch module. |
// |
|
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
`ifdef OPT_PIPELINED |
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline); |
`else |
assign dcd_ce = 1'b1; |
`endif |
`ifdef OPT_PIPELINED |
assign dcd_stalled = (dcdvalid)&&(op_stall); |
`else |
// If not pipelined, there will be no opvalid_ anything, and the |
// op_stall will be false, dcdX_stall will be false, thus we can simply |
// do a ... |
assign dcd_stalled = 1'b0; |
`endif |
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
wire op_lock_stall; |
`ifdef OPT_PIPELINED |
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins |
// Stall if we're stopped, and not allowed to execute |
// an instruction |
// (~master_ce) // Already captured in alu_stall |
// |
// Stall if going into the ALU and the ALU is stalled |
// i.e. if the memory is busy, or we are single |
// stepping. This also includes our stalls for |
// op_break and op_lock, so we don't need to |
// include those as well here. |
// This also includes whether or not the divide or |
// floating point units are busy. |
(alu_stall) |
// |
// Stall if we are going into memory with an operation |
// that cannot be pipelined, and the memory is |
// already busy |
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled |
) |
||(dcdvalid)&&( |
// Stall if we need to wait for an operand A |
// to be ready to read |
(dcdA_stall) |
// Likewise for B, also includes logic |
// regarding immediate offset (register must |
// be in register file if we need to add to |
// an immediate) |
||(dcdB_stall) |
// Or if we need to wait on flags to work on the |
// CC register |
||(dcdF_stall) |
); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline); |
`else |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal)); |
`endif |
|
// |
// PIPELINE STAGE #4 :: ALU / Memory |
// Calculate stall conditions |
// |
// 1. Basic stall is if the previous stage is valid and the next is |
// busy. |
// 2. Also stall if the prior stage is valid and the master clock enable |
// is de-selected |
// 3. Stall if someone on the other end is writing the CC register, |
// since we don't know if it'll put us to sleep or not. |
// 4. Last case: Stall if we would otherwise move a break instruction |
// through the ALU. Break instructions are not allowed through |
// the ALU. |
`ifdef OPT_PIPELINED |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2 |
// Old case #3--this isn't an ALU stall though ... |
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie) |
&&(wr_write_cc)) // Case 3 |
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal)) |
&&(~alu_stall) |
&&(~clear_pipeline); |
`else |
assign alu_stall = ((~master_ce)&&(opvalid_alu)) |
||((opvalid_alu)&&(op_break)); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall); |
`endif |
// |
|
// |
// Note: if you change the conditions for mem_ce, you must also change |
// alu_pc_valid. |
// |
`ifdef OPT_PIPELINED |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`else |
// If we aren't pipelined, then no one will be changing what's in the |
// pipeline (i.e. clear_pipeline), while our only instruction goes |
// through the ... pipeline. |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled); |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
(mem_pipe_stalled) |
||((~op_pipe)&&(mem_busy)) |
||(div_busy) |
||(fpu_busy) |
// Stall waiting for flags to be valid |
// Or waiting for a write to the PC register |
// Or CC register, since that can change the |
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie) |
&&((wr_write_pc)||(wr_write_cc))))); |
`else |
`ifdef OPT_PIPELINED |
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
// Or waiting for a write to the PC register |
// Or CC register, since that can change the |
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc))))); |
`else |
assign mem_stalled = (opvalid_mem)&&(~master_ce); |
`endif |
`endif |
|
|
// |
// |
// PIPELINE STAGE #1 :: Prefetch |
// |
// |
`ifdef OPT_SINGLE_FETCH |
wire pf_ce; |
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid); |
prefetch #(ADDRESS_WIDTH) |
pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data); |
|
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch)); |
else if ((op_ce)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
|
`else // Pipe fetch |
|
`ifdef OPT_TRADITIONAL_PFCACHE |
pfcache #(LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)), |
i_clear_pf_cache, |
// dcd_pc, |
~dcd_stalled, |
((dcd_early_branch)&&(dcdvalid)&&(~new_pc)) |
? dcd_branch_pc:pf_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
pf_illegal); |
`else |
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)), |
i_clear_pf_cache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
//`ifdef OPT_PRECLEAR_BUS |
//((dcd_clear_bus)&&(dcdvalid)) |
//||((op_clear_bus)&&(opvalid)) |
//|| |
//`endif |
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
`endif |
assign instruction_gie = gie; |
|
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch)); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
`endif |
|
`ifdef OPT_NEW_INSTRUCTION_SET |
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
`else |
idecode_deprecated |
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
`endif |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
reg op_pipe; |
|
initial op_pipe = 1'b0; |
// To be a pipeable operation, there must be |
// two valid adjacent instructions |
// Both must be memory instructions |
// Both must be writes, or both must be reads |
// Both operations must be to the same identical address, |
// or at least a single (one) increment above that address |
// |
// However ... we need to know this before this clock, hence this is |
// calculated in the instruction decoder. |
always @(posedge i_clk) |
if (op_ce) |
op_pipe <= dcd_pipe; |
`endif |
|
// |
// |
// PIPELINE STAGE #3 :: Read Operands (Registers) |
// |
// |
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
|
wire [31:0] w_pcA_v; |
generate |
if (AW < 32) |
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc; |
endgenerate |
|
`ifdef OPT_PIPELINED |
reg [4:0] opA_id, opB_id; |
reg opA_rd, opB_rd; |
always @(posedge i_clk) |
if (op_ce) |
begin |
opA_id <= dcdA; |
opB_id <= dcdB; |
opA_rd <= dcdA_rd; |
opB_rd <= dcdB_rd; |
end |
`endif |
|
always @(posedge i_clk) |
if (op_ce) // &&(dcdvalid)) |
begin |
if ((wr_reg_ce)&&(wr_reg_id == dcdA)) |
r_opA <= wr_reg_vl; |
else if (dcdA_pc) |
r_opA <= w_pcA_v; |
else if (dcdA_cc) |
r_opA <= { w_opA[31:14], (dcdA[4])?w_uflags:w_iflags }; |
else |
r_opA <= w_opA; |
`ifdef OPT_PIPELINED |
end else |
begin // We were going to pick these up when they became valid, |
// but for some reason we're stuck here as they became |
// valid. Pick them up now anyway |
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid))) |
// r_opA <= wr_reg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd)) |
r_opA <= wr_reg_vl; |
`endif |
end |
|
wire [31:0] w_opBnI, w_pcB_v; |
generate |
if (AW < 32) |
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc; |
endgenerate |
|
assign w_opBnI = (~dcdB_rd) ? 32'h00 |
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl |
: ((dcdB_pc) ? w_pcB_v |
: ((dcdB_cc) ? { w_opB[31:14], (dcdB[4])?w_uflags:w_iflags} |
: w_opB))); |
|
always @(posedge i_clk) |
if (op_ce) // &&(dcdvalid)) |
r_opB <= w_opBnI + dcdI; |
`ifdef OPT_PIPELINED |
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd)) |
r_opB <= wr_reg_vl; |
`endif |
|
// The logic here has become more complex than it should be, no thanks |
// to Xilinx's Vivado trying to help. The conditions are supposed to |
// be two sets of four bits: the top bits specify what bits matter, the |
// bottom specify what those top bits must equal. However, two of |
// conditions check whether bits are on, and those are the only two |
// conditions checking those bits. Therefore, Vivado complains that |
// these two bits are redundant. Hence the convoluted expression |
// below, arriving at what we finally want in the (now wire net) |
// opF. |
always @(posedge i_clk) |
if (op_ce) |
begin // Set the flag condition codes, bit order is [3:0]=VNCZ |
case(dcdF[2:0]) |
3'h0: r_opF <= 6'h00; // Always |
`ifdef OPT_NEW_INSTRUCTION_SET |
// These were remapped as part of the new instruction |
// set in order to make certain that the low order |
// two bits contained the most commonly used |
// conditions: Always, LT, Z, and NZ. |
3'h1: r_opF <= 6'h24; // LT |
3'h2: r_opF <= 6'h11; // Z |
3'h3: r_opF <= 6'h10; // NE |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h20; // GE (!N) |
`else |
3'h1: r_opF <= 6'h11; // Z |
3'h2: r_opF <= 6'h10; // NE |
3'h3: r_opF <= 6'h20; // GE (!N) |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h24; // LT |
`endif |
3'h6: r_opF <= 6'h02; // C |
3'h7: r_opF <= 6'h08; // V |
endcase |
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } |
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
|
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
end else if (op_ce) |
begin |
// Do we have a valid instruction? |
// The decoder may vote to stall one of its |
// instructions based upon something we currently |
// have in our queue. This instruction must then |
// move forward, and get a stall cycle inserted. |
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= w_opvalid; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid); |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid); |
`else |
opvalid_alu <= (dcdALU)&&(w_opvalid); |
opvalid_mem <= (dcdM)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
`endif |
end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce)) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
end |
|
// Here's part of our debug interface. When we recognize a break |
// instruction, we set the op_break flag. That'll prevent this |
// instruction from entering the ALU, and cause an interrupt before |
// this instruction. Thus, returning to this code will cause the |
// break to repeat and continue upon return. To get out of this |
// condition, replace the break instruction with what it is supposed |
// to be, step through it, and then replace it back. In this fashion, |
// a debugger can step through code. |
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
initial op_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) op_break <= 1'b0; |
else if (op_ce) op_break <= (dcd_break); |
else if ((clear_pipeline)||(~opvalid)) |
op_break <= 1'b0; |
|
`ifdef OPT_PIPELINED |
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_op_lock, r_op_lock_stall; |
|
initial r_op_lock_stall = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_op_lock_stall <= 1'b0; |
else |
r_op_lock_stall <= (~opvalid)||(~op_lock) |
||(~dcdvalid)||(~pf_valid); |
|
assign op_lock_stall = r_op_lock_stall; |
|
initial r_op_lock = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_op_lock <= 1'b0; |
else if ((op_ce)&&(dcd_lock)) |
r_op_lock <= 1'b1; |
else if ((op_ce)||(clear_pipeline)) |
r_op_lock <= 1'b0; |
assign op_lock = r_op_lock; |
|
end else begin |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
end endgenerate |
|
`else |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
`endif |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial op_illegal = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
op_illegal <= 1'b0; |
else if(op_ce) |
`ifdef OPT_PIPELINED |
op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)); |
`else |
op_illegal <= (dcd_illegal)||(dcd_lock); |
`endif |
`endif |
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not |
// set, dcd_early_branch will simply be a wire connected to zero and |
// this logic should just optimize. |
always @(posedge i_clk) |
if (op_ce) |
begin |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
|
always @(posedge i_clk) |
if (op_ce) |
begin |
opn <= dcdOp; // Which ALU operation? |
// opM <= dcdM; // Is this a memory operation? |
// What register will these results be written into? |
opR <= dcdR; |
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie); |
// User level (1), vs supervisor (0)/interrupts disabled |
op_gie <= dcd_gie; |
|
|
// |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
end |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
|
`ifdef OPT_VLIW |
reg r_op_phase; |
initial r_op_phase = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
r_op_phase <= 1'b0; |
else if (op_ce) |
r_op_phase <= dcd_phase; |
assign op_phase = r_op_phase; |
`else |
assign op_phase = 1'b0; |
`endif |
|
// This is tricky. First, the PC and Flags registers aren't kept in |
// register set but in special registers of their own. So step one |
// is to select the right register. Step to is to replace that |
// register with the results of an ALU or memory operation, if such |
// results are now available. Otherwise, we'd need to insert a wait |
// state of some type. |
// |
// The alternative approach would be to define some sort of |
// op_stall wire, which would stall any upstream stage. |
// We'll create a flag here to start our coordination. Once we |
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
`ifdef OPT_PIPELINED |
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd)) |
? wr_reg_vl : r_opA; |
`else |
assign opA = r_opA; |
`endif |
|
`ifdef OPT_PIPELINED |
// Stall if we have decoded an instruction that will read register A |
// AND ... something that may write a register is running |
// AND (series of conditions here ...) |
// The operation might set flags, and we wish to read the |
// CC register |
// OR ... (No other conditions) |
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere |
&&((opvalid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)) |
&&((opF_wr)&&(dcdA_cc)); |
`else |
// There are no pipeline hazards, if we aren't pipelined |
assign dcdA_stall = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED |
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd)) |
? wr_reg_vl: r_opB; |
`else |
assign opB = r_opB; |
`endif |
|
`ifdef OPT_PIPELINED |
// Stall if we have decoded an instruction that will read register B |
// AND ... something that may write a (unknown) register is running |
// AND (series of conditions here ...) |
// The operation might set flags, and we wish to read the |
// CC register |
// OR the operation might set register B, and we still need |
// a clock to add the offset to it |
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere |
// If the op stage isn't valid, yet something |
// is running, then it must have been valid. |
// We'll use the last values from that stage |
// (opR_wr, opF_wr, opR) in our logic below. |
&&((opvalid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)) |
&&( |
// Stall on memory ops writing to my register |
// (i.e. loads), or on any write to my |
// register if I have an immediate offset |
// Note the exception for writing to the PC: |
// if I write to the PC, the whole next |
// instruction is invalid, not just the |
// operand. That'll get wiped in the |
// next operation anyway, so don't stall |
// here. This keeps a BC X, BNZ Y from |
// stalling between the two branches. |
// BC X, BRA Y is still clear, since BRA Y |
// is an early branch instruction. |
// (This exception is commented out in |
// order to help keep our logic simple, and |
// because multiple conditional branches |
// following each other constitutes a |
// fairly unusualy code structure.) |
// |
((~dcd_zI)&&(opR == dcdB)&&(opR_wr)) |
// &&(opR != { op_gie, `CPU_PC_REG } ) |
// Stall following any instruction that will |
// set the flags, if we're going to need the |
// flags (CC) register for opB. |
||((opF_wr)&&(dcdB_cc)) |
// Stall on any ongoing memory operation that |
// will write to opB -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI)) |
); |
`else |
// No stalls without pipelining, 'cause how can you have a pipeline |
// hazard without the pipeline? |
assign dcdB_stall = 1'b0; |
`endif |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
// |
// |
// PIPELINE STAGE #4 :: Apply Instruction |
// |
// |
`ifdef OPT_NEW_INSTRUCTION_SET |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce, |
(opvalid_alu), opn, opA, opB, |
alu_result, alu_flags, alu_valid, alu_illegal_op, |
alu_busy); |
`else |
cpuops_deprecated #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce, |
(opvalid_alu), opn, opA, opB, |
alu_result, alu_flags, alu_valid, alu_illegal_op); |
assign alu_busy = 1'b0; |
`endif |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0], |
opA, opB, div_busy, div_valid, div_error, div_result, |
div_flags); |
end else begin |
assign div_error = 1'b1; |
assign div_busy = 1'b0; |
assign div_valid = 1'b0; |
assign div_result= 32'h00; |
assign div_flags = 4'h0; |
end endgenerate |
|
generate |
if (IMPLEMENT_FPU != 0) |
begin |
// |
// sfpu thefpu(i_clk, i_rst, fpu_ce, |
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// fpu_flags); |
// |
assign fpu_error = 1'b1; |
assign fpu_busy = 1'b0; |
assign fpu_valid = 1'b0; |
assign fpu_result= 32'h00; |
assign fpu_flags = 4'h0; |
end else begin |
assign fpu_error = 1'b1; |
assign fpu_busy = 1'b0; |
assign fpu_valid = 1'b0; |
assign fpu_result= 32'h00; |
assign fpu_flags = 4'h0; |
end endgenerate |
|
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]); |
initial alF_wr = 1'b0; |
initial alu_wr = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
alu_wr <= 1'b0; |
alF_wr <= 1'b0; |
end else if (alu_ce) |
begin |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond); |
alF_wr <= (opF_wr)&&(set_cond); |
end else if (~alu_busy) begin |
// These are strobe signals, so clear them if not |
// set for any particular clock |
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
end |
|
`ifdef OPT_VLIW |
reg r_alu_phase; |
initial r_alu_phase = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_alu_phase <= 1'b0; |
else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce)) |
r_alu_phase <= op_phase; |
assign alu_phase = r_alu_phase; |
`else |
assign alu_phase = 1'b0; |
`endif |
|
always @(posedge i_clk) |
if ((alu_ce)||(div_ce)||(fpu_ce)) |
alu_reg <= opR; |
else if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
|
reg [31:0] dbg_val; |
reg dbgv; |
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
initial dbgv = 1'b0; |
always @(posedge i_clk) |
dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we)); |
always @(posedge i_clk) |
if ((alu_ce)||(mem_ce)) |
alu_gie <= op_gie; |
always @(posedge i_clk) |
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline) |
&&(~mem_stalled))) |
alu_pc <= op_pc; |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg r_alu_illegal; |
initial r_alu_illegal = 0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_alu_illegal <= 1'b0; |
else if ((alu_ce)||(mem_ce)) |
r_alu_illegal <= op_illegal; |
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal); |
`endif |
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only |
// problem is that mem_ce is gated by the set_cond, and |
// the PC will be valid independent of the set condition. Hence, this |
// equals (alu_ce)||(everything in mem_ce but the set condition) |
initial alu_pc_valid = 1'b0; |
always @(posedge i_clk) |
alu_pc_valid <= ((alu_ce) |
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled))); |
|
wire bus_lock; |
`ifdef OPT_PIPELINED |
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_bus_lock; |
initial r_bus_lock = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_bus_lock <= 1'b0; |
else if ((op_ce)&&(op_lock)) |
r_bus_lock <= 1'b1; |
else if (~opvalid_mem) |
r_bus_lock <= 1'b0; |
assign bus_lock = r_bus_lock; |
end else begin |
assign bus_lock = 1'b0; |
end endgenerate |
`else |
assign bus_lock = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
mem_busy, mem_pipe_stalled, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, mem_err, i_wb_data); |
|
`else // PIPELINED_BUS_ACCESS |
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
mem_busy, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, mem_err, i_wb_data); |
`endif // PIPELINED_BUS_ACCESS |
assign mem_rdbusy = ((mem_busy)&&(~mem_we)); |
|
// Either the prefetch or the instruction gets the memory bus, but |
// never both. |
wbdblpriarb #(32,AW) pformem(i_clk, i_rst, |
// Memory access to the arbiter, priority position |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err, |
// Prefetch access to the arbiter |
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, |
// Common wires, in and out, of the arbiter |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err); |
|
// |
// |
// PIPELINE STAGE #5 :: Write-back results |
// |
// |
// This stage is not allowed to stall. If results are ready to be |
// written back, they are written back at all cost. Sleepy CPU's |
// won't prevent write back, nor debug modes, halting the CPU, nor |
// anything else. Indeed, the (master_ce) bit is only as relevant |
// as knowinig something is available for writeback. |
|
// |
// Write back to our generic register set ... |
// When shall we write back? On one of two conditions |
// Note that the flags needed to be checked before issuing the |
// bus instruction, so they don't need to be checked here. |
// Further, alu_wr includes (set_cond), so we don't need to |
// check for that here either. |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (~alu_illegal)&& |
(((alu_wr)&&(~clear_pipeline) |
&&((alu_valid)||(div_valid)||(fpu_valid))) |
||(mem_valid)); |
`else |
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid); |
`endif |
// Which register shall be written? |
// COULD SIMPLIFY THIS: by adding three bits to these registers, |
// One or PC, one for CC, and one for GIE match |
// Note that the alu_reg is the register to write on a divide or |
// FPU operation. |
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg; |
// Are we writing to the CC register? |
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG); |
// Are we writing to the PC? |
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG); |
// What value to write? |
assign wr_reg_vl = ((mem_valid) ? mem_result |
:((div_valid|fpu_valid)) |
? ((div_valid) ? div_result:fpu_result) |
:((dbgv) ? dbg_val : alu_result)); |
always @(posedge i_clk) |
if (wr_reg_ce) |
regset[wr_reg_id] <= wr_reg_vl; |
|
// |
// Write back to the condition codes/flags register ... |
// When shall we write to our flags register? alF_wr already |
// includes the set condition ... |
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign w_uflags = { uhalt_phase, ufpu_err_flag, |
udiv_err_flag, ubus_err_flag, trap, ill_err_u, |
1'b0, step, 1'b1, sleep, |
((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { ihalt_phase, ifpu_err_flag, |
idiv_err_flag, ibus_err_flag, trap, ill_err_i, |
break_en, 1'b0, 1'b0, sleep, |
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
|
|
// What value to write? |
always @(posedge i_clk) |
// If explicitly writing the register itself |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc)) |
flags <= wr_reg_vl[3:0]; |
// Otherwise if we're setting the flags from an ALU operation |
else if ((wr_flags_ce)&&(alu_gie)) |
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags |
: alu_flags); |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
iflags <= wr_reg_vl[3:0]; |
else if ((wr_flags_ce)&&(~alu_gie)) |
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags |
: alu_flags); |
|
// The 'break' enable bit. This bit can only be set from supervisor |
// mode. It control what the CPU does upon encountering a break |
// instruction. |
// |
// The goal, upon encountering a break is that the CPU should stop and |
// not execute the break instruction, choosing instead to enter into |
// either interrupt mode or halt first. |
// if ((break_en) AND (break_instruction)) // user mode or not |
// HALT CPU |
// else if (break_instruction) // only in user mode |
// set an interrupt flag, go to supervisor mode |
// allow supervisor to step the CPU. |
// Upon a CPU halt, any break condition will be reset. The |
// external debugger will then need to deal with whatever |
// condition has taken place. |
initial break_en = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(i_halt)) |
break_en <= 1'b0; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
break_en <= wr_reg_vl[`CPU_BREAK_BIT]; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign o_break = ((break_en)||(~op_gie))&&(op_break) |
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy) |
&&(~div_busy)&&(~fpu_busy) |
&&(~clear_pipeline) |
||((~alu_gie)&&(bus_err)) |
||((~alu_gie)&&(div_valid)&&(div_error)) |
||((~alu_gie)&&(fpu_valid)&&(fpu_error)) |
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal)); |
`else |
assign o_break = (((break_en)||(~op_gie))&&(op_break) |
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy) |
&&(~clear_pipeline)) |
||((~alu_gie)&&(bus_err)); |
`endif |
|
|
// The sleep register. Setting the sleep register causes the CPU to |
// sleep until the next interrupt. Setting the sleep register within |
// interrupt mode causes the processor to halt until a reset. This is |
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
// In supervisor mode, we have no protections. The |
// supervisor can set the sleep bit however he wants. |
// Well ... not quite. Switching to user mode and |
// sleep mode shouold only be possible if the interrupt |
// flag isn't set. |
// Thus: if (i_interrupt)&&(wr_reg_vl[GIE]) |
// don't set the sleep bit |
// otherwise however it would o.w. be set |
sleep <= (wr_reg_vl[`CPU_SLEEP_BIT]) |
&&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT])); |
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT])) |
// In user mode, however, you can only set the sleep |
// mode while remaining in user mode. You can't switch |
// to sleep mode *and* supervisor mode at the same |
// time, lest you halt the CPU. |
sleep <= wr_reg_vl[`CPU_SLEEP_BIT]; |
|
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
step <= 1'b0; |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc)) |
step <= wr_reg_vl[`CPU_STEP_BIT]; |
else if ((alu_pc_valid)&&(step)&&(gie)) |
step <= 1'b0; |
|
// The GIE register. Only interrupts can disable the interrupt register |
assign w_switch_to_interrupt = (gie)&&( |
// On interrupt (obviously) |
((i_interrupt)&&(~alu_phase)&&(~bus_lock)) |
// If we are stepping the CPU |
||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock)) |
// If we encounter a break instruction, if the break |
// enable isn't set. |
||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(op_break)&&(~break_en)) |
`ifdef OPT_ILLEGAL_INSTRUCTION |
// On an illegal instruction |
||((alu_pc_valid)&&(alu_illegal)) |
`endif |
// On division by zero. If the divide isn't |
// implemented, div_valid and div_error will be short |
// circuited and that logic will be bypassed |
||((div_valid)&&(div_error)) |
// Same thing on a floating point error. |
||((fpu_valid)&&(fpu_error)) |
// |
||(bus_err) |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
); |
assign w_release_from_interrupt = (~gie)&&(~i_interrupt) |
// Then if we write the CC register |
&&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT]) |
&&(~wr_reg_id[4])&&(wr_write_cc)) |
); |
always @(posedge i_clk) |
if (i_rst) |
gie <= 1'b0; |
else if (w_switch_to_interrupt) |
gie <= 1'b0; |
else if (w_release_from_interrupt) |
gie <= 1'b1; |
|
initial trap = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_write_cc)) // &&(wr_reg_id[4]) implied |
trap <= 1'b1; |
else if (w_release_from_interrupt) |
trap <= 1'b0; |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial ill_err_i = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ill_err_i <= 1'b0; |
// The debug interface can clear this bit |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_ILL_BIT])) |
ill_err_i <= 1'b0; |
else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie)) |
ill_err_i <= 1'b1; |
initial ill_err_u = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ill_err_u <= 1'b0; |
// The bit is automatically cleared on release from interrupt |
else if (w_release_from_interrupt) |
ill_err_u <= 1'b0; |
// If the supervisor writes to this register, clearing the |
// bit, then clear it |
else if (((~alu_gie)||(dbgv)) |
&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
ill_err_u <= 1'b0; |
else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie)) |
ill_err_u <= 1'b1; |
`else |
assign ill_err_u = 1'b0; |
assign ill_err_i = 1'b0; |
`endif |
// Supervisor/interrupt bus error flag -- this will crash the CPU if |
// ever set. |
initial ibus_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ibus_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_BUSERR_BIT])) |
ibus_err_flag <= 1'b0; |
else if ((bus_err)&&(~alu_gie)) |
ibus_err_flag <= 1'b1; |
// User bus error flag -- if ever set, it will cause an interrupt to |
// supervisor mode. |
initial ubus_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ubus_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
ubus_err_flag <= 1'b0; |
// else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4]) |
// &&(i_dbg_reg == {1'b1, `CPU_CC_REG}) |
// &&(~i_dbg_data[`CPU_BUSERR_BIT])) |
// ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(~wr_reg_vl[`CPU_BUSERR_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
ubus_err_flag <= 1'b0; |
else if ((bus_err)&&(alu_gie)) |
ubus_err_flag <= 1'b1; |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
reg r_idiv_err_flag, r_udiv_err_flag; |
|
// Supervisor/interrupt divide (by zero) error flag -- this will |
// crash the CPU if ever set. This bit is thus available for us |
// to be able to tell if/why the CPU crashed. |
initial r_idiv_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_idiv_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_DIVERR_BIT])) |
r_idiv_err_flag <= 1'b0; |
else if ((div_error)&&(div_valid)&&(~alu_gie)) |
r_idiv_err_flag <= 1'b1; |
// User divide (by zero) error flag -- if ever set, it will |
// cause a sudden switch interrupt to supervisor mode. |
initial r_udiv_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_udiv_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
r_udiv_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(~wr_reg_vl[`CPU_DIVERR_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
r_udiv_err_flag <= 1'b0; |
else if ((div_error)&&(alu_gie)&&(div_valid)) |
r_udiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
assign udiv_err_flag = r_udiv_err_flag; |
end else begin |
assign idiv_err_flag = 1'b0; |
assign udiv_err_flag = 1'b0; |
end endgenerate |
|
generate |
if (IMPLEMENT_FPU !=0) |
begin |
// Supervisor/interrupt floating point error flag -- this will |
// crash the CPU if ever set. |
reg r_ifpu_err_flag, r_ufpu_err_flag; |
initial r_ifpu_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_ifpu_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG}) |
&&(~wr_reg_vl[`CPU_FPUERR_BIT])) |
r_ifpu_err_flag <= 1'b0; |
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie)) |
r_ifpu_err_flag <= 1'b1; |
// User floating point error flag -- if ever set, it will cause |
// a sudden switch interrupt to supervisor mode. |
initial r_ufpu_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_ufpu_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
r_ufpu_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(~wr_reg_vl[`CPU_FPUERR_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
r_ufpu_err_flag <= 1'b0; |
else if ((fpu_error)&&(alu_gie)&&(fpu_valid)) |
r_ufpu_err_flag <= 1'b1; |
|
assign ifpu_err_flag = r_ifpu_err_flag; |
assign ufpu_err_flag = r_ufpu_err_flag; |
end else begin |
assign ifpu_err_flag = 1'b0; |
assign ufpu_err_flag = 1'b0; |
end endgenerate |
|
`ifdef OPT_VLIW |
reg r_ihalt_phase, r_uhalt_phase; |
|
initial r_ihalt_phase = 0; |
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if (~alu_gie) |
r_ihalt_phase <= alu_phase; |
always @(posedge i_clk) |
if (alu_gie) |
r_uhalt_phase <= alu_phase; |
else if (w_release_from_interrupt) |
r_uhalt_phase <= 1'b0; |
|
assign ihalt_phase = r_ihalt_phase; |
assign uhalt_phase = r_uhalt_phase; |
`else |
assign ihalt_phase = 1'b0; |
assign uhalt_phase = 1'b0; |
`endif |
|
// |
// Write backs to the PC register, and general increments of it |
// We support two: upc and ipc. If the instruction is normal, |
// we increment upc, if interrupt level we increment ipc. If |
// the instruction writes the PC, we write whichever PC is appropriate. |
// |
// Do we need to all our partial results from the pipeline? |
// What happens when the pipeline has gie and ~gie instructions within |
// it? Do we clear both? What if a gie instruction tries to clear |
// a non-gie instruction? |
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
upc <= wr_reg_vl[(AW-1):0]; |
else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
upc <= alu_pc; |
|
always @(posedge i_clk) |
if (i_rst) |
ipc <= RESET_ADDRESS; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= wr_reg_vl[(AW-1):0]; |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
ipc <= alu_pc; |
|
always @(posedge i_clk) |
if (i_rst) |
pf_pc <= RESET_ADDRESS; |
else if (w_switch_to_interrupt) |
pf_pc <= ipc; |
else if (w_release_from_interrupt) |
pf_pc <= upc; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_reg_vl[(AW-1):0]; |
`ifdef OPT_PIPELINED |
else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid))) |
pf_pc <= dcd_branch_pc + 1; |
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |
`else |
else if ((alu_pc_valid)&&(~clear_pipeline)) |
pf_pc <= alu_pc; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
// |
// The debug interface |
generate |
if (AW<32) |
begin |
always @(posedge i_clk) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end |
end else begin |
always @(posedge i_clk) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end |
end endgenerate |
|
always @(posedge i_clk) |
o_dbg_cc <= { o_break, bus_err, gie, sleep }; |
|
always @(posedge i_clk) |
o_dbg_stall <= (i_halt)&&( |
(pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy) |
||((~opvalid)&&(~i_rst)) |
||((~dcdvalid)&&(~i_rst))); |
|
// |
// |
// Produce accounting outputs: Account for any CPU stalls, so we can |
// later evaluate how well we are doing. |
// |
// |
assign o_op_stall = (master_ce)&&(op_stall); |
assign o_pf_stall = (master_ce)&&(~pf_valid); |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline); |
|
`ifdef DEBUG_SCOPE |
always @(posedge i_clk) |
o_debug <= { |
pf_pc[3:0], flags, |
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid, |
op_ce, alu_ce, mem_ce, |
// |
master_ce, opvalid_alu, opvalid_mem, |
// |
alu_stall, mem_busy, op_pipe, mem_pipe_stalled, |
mem_we, |
// ((opvalid_alu)&&(alu_stall)) |
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// opA[23:20], opA[3:0], |
gie, sleep, |
wr_reg_ce, wr_reg_vl[4:0] |
/* |
i_rst, master_ce, (new_pc), |
((dcd_early_branch)&&(dcdvalid)), |
pf_valid, pf_illegal, |
op_ce, dcd_ce, dcdvalid, dcd_stalled, |
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err, |
pf_pc[7:0], pf_addr[7:0] |
*/ |
}; |
`endif |
|
endmodule |
/rtcdate.v
0,0 → 1,188
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: rtcdate.v |
// |
// Project: A Wishbone Controlled Real--time Clock Core |
// |
// Purpose: |
// This core provides a real-time date function that can be coupled with |
// a real-time clock. The date provided is in Binary Coded Decimal (bcd) |
// form, and available for reading and writing over the Wishbone Bus. |
// |
// WARNING: Race conditions exist when updating the date across the Wishbone |
// bus at or near midnight. (This should be obvious, but it bears |
// stating.) Specifically, if the update command shows up at the same |
// clock as the ppd clock, then the ppd clock will be ignored and the |
// new date will be the date of the day following midnight. However, |
// if the update command shows up one clock before the ppd, then the date |
// may be updated, but may have problems dealing with the last day of the |
// month or year. To avoid race conditions, update the date sometime |
// after the stroke of midnight and before 5 clocks before the next |
// midnight. If you are concerned that you might hit a race condition, |
// just read the clock again (5+ clocks later) to make certain you set |
// it correctly. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
module rtcdate(i_clk, i_ppd, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data); |
input i_clk; |
// A one part per day signal, i.e. basically a clock enable line that |
// controls when the beginning of the day happens. This line should |
// be high on the very last second of any day in order for the rtcdate |
// module to always have the right date. |
input i_ppd; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [31:0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output wire [31:0] o_wb_data; |
|
|
reg [5:0] r_day; |
reg [4:0] r_mon; |
reg [13:0] r_year; |
|
reg last_day_of_month, last_day_of_year, is_leap_year; |
always @(posedge i_clk) |
last_day_of_year <= (last_day_of_month) && (r_mon == 5'h12); |
always @(posedge i_clk) |
begin |
case(r_mon) |
5'h01: last_day_of_month <= (r_day >= 6'h31); // Jan |
5'h02: last_day_of_month <= (r_day >= 6'h29) |
||((~is_leap_year)&&(r_day == 6'h28)); |
5'h03: last_day_of_month <= (r_day >= 6'h31); // March |
5'h04: last_day_of_month <= (r_day >= 6'h30); // April |
5'h05: last_day_of_month <= (r_day >= 6'h31); // May |
5'h06: last_day_of_month <= (r_day >= 6'h30); // June |
5'h07: last_day_of_month <= (r_day >= 6'h31); // July |
5'h08: last_day_of_month <= (r_day >= 6'h31); // August |
5'h09: last_day_of_month <= (r_day >= 6'h30); // Sept |
5'h10: last_day_of_month <= (r_day >= 6'h31); // October |
5'h11: last_day_of_month <= (r_day >= 6'h30); // November |
5'h12: last_day_of_month <= (r_day >= 6'h31); // December |
default: last_day_of_month <= 1'b0; |
endcase |
end |
|
reg year_divisible_by_four, century_year, four_century_year; |
always @(posedge i_clk) |
year_divisible_by_four<= ((~r_year[0])&&(r_year[4]==r_year[1])); |
always @(posedge i_clk) |
century_year <= (r_year[7:0] == 8'h00); |
always @(posedge i_clk) |
four_century_year <= ((~r_year[8])&&((r_year[12]==r_year[9]))); |
always @(posedge i_clk) |
is_leap_year <= (year_divisible_by_four)&&((~century_year) |
||((century_year)&&(four_century_year))); |
|
|
// Adjust the day of month |
initial r_day = 6'h01; |
always @(posedge i_clk) |
begin |
if ((r_day == 0)||(r_day > 6'h31)||(r_day[3:0] > 4'h9)) |
r_day <= 6'h01; |
else if ((i_ppd)&&(last_day_of_month)) |
r_day <= 6'h01; |
else if ((i_ppd)&&(r_day[3:0] != 4'h9)) |
r_day[3:0] <= r_day[3:0] + 4'h1; |
else if (i_ppd) |
begin |
r_day[3:0] <= 4'h0; |
r_day[5:4] <= r_day[5:4] + 2'h1; |
end |
|
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_data[7:0]!=8'hff)) |
r_day <= i_wb_data[5:0]; |
end |
|
// Adjust the month of the year |
initial r_mon = 5'h01; |
always @(posedge i_clk) |
begin |
if ((r_mon == 0)||(r_mon > 5'h12)||(r_mon[3:0] > 4'h9)) |
r_mon <= 5'h01; |
else if ((i_ppd)&&(last_day_of_year)) |
r_mon <= 5'h01; |
else if ((i_ppd)&&(last_day_of_month)&&(r_mon[3:0] != 4'h9)) |
r_mon[3:0] <= r_mon[3:0] + 4'h1; |
else if ((i_ppd)&&(last_day_of_month)) |
begin |
r_mon[3:0] <= 4'h0; |
r_mon[4] <= 1; |
end |
|
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_data[15:8]!=8'hff)) |
r_mon <= i_wb_data[12:8]; |
end |
|
// Adjust the year |
initial r_year = 14'h2000; |
always @(posedge i_clk) |
begin |
// Deal with any out of bounds conditions |
if (r_year[3:0] > 4'h9) |
r_year[3:0] <= 4'h0; |
if (r_year[7:4] > 4'h9) |
r_year[7:4] <= 4'h0; |
if (r_year[11:8] > 4'h9) |
r_year[11:8] <= 4'h0; |
if ((i_ppd)&&(last_day_of_year)) |
begin |
if (r_year[3:0] != 4'h9) |
r_year[3:0] <= r_year[3:0] + 4'h1; |
else begin |
r_year[3:0] <= 4'h0; |
if (r_year[7:4] != 4'h9) |
r_year[7:4] <= r_year[7:4] + 4'h1; |
else begin |
r_year[7:4] <= 4'h0; |
if (r_year[11:8] != 4'h9) |
r_year[11:8] <= r_year[11:8]+4'h1; |
else begin |
r_year[11:8] <= 4'h0; |
r_year[13:12] <= r_year[13:12]+2'h1; |
end |
end |
end |
end |
|
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_data[31:16]!=16'hffff)) |
r_year <= i_wb_data[29:16]; |
end |
|
always @(posedge i_clk) |
o_wb_ack <= ((i_wb_cyc)&&(i_wb_stb)); |
assign o_wb_stall = 1'b0; |
assign o_wb_data = { 2'h0, r_year, 3'h0, r_mon, 2'h0, r_day }; |
endmodule |
/wbicapesimple.v
0,0 → 1,170
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbicapesimple.v |
// |
// Project: Wishbone to ICAPE_SPARTAN6 interface conversion |
// |
// Purpose: This is a companion project to the ICAPE2 conversion, instead |
// involving a conversion from a 32-bit WISHBONE bus to read |
// and write the ICAPE_SPARTAN6 program. Since this is a simple interface |
// only, the smarts have been stripped out of it. Therefore, if you wish |
// to write to or read from particular registers, you will need to do all |
// the sequencing yourself. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbicapesimple(i_clk, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, icap_dbg); |
input i_clk; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [15:0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [15:0] o_wb_data; |
output wire [25:0] icap_dbg; |
|
|
// Divide our clock by 8. Thus, a 100 MHz clock with a 10 ns period |
// gets divided down to an 80 ns period, which is greater than the |
// minimum 50 ns as per the data sheet. |
reg [2:0] clk_divider; |
initial clk_divider=0; |
always @(posedge i_clk) |
clk_divider <= clk_divider + 3'h1; |
|
reg icap_posedge, icap_preedge; |
initial icap_posedge = 0; |
always @(posedge i_clk) |
icap_posedge <= (clk_divider == 3'b011); |
initial icap_preedge = 0; |
always @(posedge i_clk) |
icap_preedge <= (clk_divider == 3'b010); |
// icap_posedge <= (&clk_divider); |
|
wire icap_clk; |
assign icap_clk = clk_divider[2]; |
|
reg icap_ce_n, icap_we_n; |
reg [15:0] icap_data_i; |
|
|
wire icap_busy; |
wire [15:0] icap_data_o; |
ICAP_SPARTAN6 icap_inst( |
.BUSY(icap_busy), // Active high, low during all writes |
.O(icap_data_o), |
.CE(icap_ce_n), |
.CLK(icap_clk), |
.I(icap_data_i), |
.WRITE(icap_we_n)); |
|
// assign o_wb_stall = (i_wb_cyc)&&((~icap_posedge)||((~icap_ce_n)&&(icap_busy))); |
|
wire [15:0] brev_i_wb_data; |
assign brev_i_wb_data[ 0] = i_wb_data[ 7]; |
assign brev_i_wb_data[ 1] = i_wb_data[ 6]; |
assign brev_i_wb_data[ 2] = i_wb_data[ 5]; |
assign brev_i_wb_data[ 3] = i_wb_data[ 4]; |
assign brev_i_wb_data[ 4] = i_wb_data[ 3]; |
assign brev_i_wb_data[ 5] = i_wb_data[ 2]; |
assign brev_i_wb_data[ 6] = i_wb_data[ 1]; |
assign brev_i_wb_data[ 7] = i_wb_data[ 0]; |
// |
assign brev_i_wb_data[ 8] = i_wb_data[15]; |
assign brev_i_wb_data[ 9] = i_wb_data[14]; |
assign brev_i_wb_data[10] = i_wb_data[13]; |
assign brev_i_wb_data[11] = i_wb_data[12]; |
assign brev_i_wb_data[12] = i_wb_data[11]; |
assign brev_i_wb_data[13] = i_wb_data[10]; |
assign brev_i_wb_data[14] = i_wb_data[ 9]; |
assign brev_i_wb_data[15] = i_wb_data[ 8]; |
// |
|
initial icap_data_i = 0; |
always @(posedge i_clk) |
if (icap_preedge) |
begin |
if (~i_wb_cyc) |
icap_data_i <= 16'hffff; |
else if ((icap_ce_n)||(~icap_busy)) |
icap_data_i <= brev_i_wb_data[15:0]; |
end |
|
initial icap_we_n = 1'b1; |
always @(posedge i_clk) |
if ((icap_preedge)&&((icap_ce_n)||(~icap_busy))) |
icap_we_n <= ~i_wb_we; |
initial icap_ce_n = 1'b1; |
always @(posedge i_clk) |
if ((icap_preedge)&&((icap_ce_n)||(~icap_busy))) |
icap_ce_n <= ~((i_wb_cyc)&&(i_wb_stb)); |
else if ((icap_preedge)&&(~i_wb_cyc)) |
icap_ce_n <= 1'b1; |
//initial r_wb_stall = 1'b0; |
//always @(posedge i_clk) |
//r_wb_stall <= (~icap_posedge)&&( |
//&&(icap_preedge)&&(~icap_busy)); |
// assign o_wb_stall = (i_wb_cyc)&&((~icap_posedge)||((~icap_ce_n)&&(icap_busy))); |
assign o_wb_stall = (~icap_posedge) |
||((i_wb_cyc)&&(~icap_ce_n)&&(icap_busy)); |
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= ((~icap_ce_n)&&(i_wb_cyc) |
&&(icap_preedge)&&(~icap_busy)); |
|
wire [15:0] brev_icap_data; |
assign brev_icap_data[ 0] = icap_data_o[ 7]; |
assign brev_icap_data[ 1] = icap_data_o[ 6]; |
assign brev_icap_data[ 2] = icap_data_o[ 5]; |
assign brev_icap_data[ 3] = icap_data_o[ 4]; |
assign brev_icap_data[ 4] = icap_data_o[ 3]; |
assign brev_icap_data[ 5] = icap_data_o[ 2]; |
assign brev_icap_data[ 6] = icap_data_o[ 1]; |
assign brev_icap_data[ 7] = icap_data_o[ 0]; |
// |
assign brev_icap_data[ 8] = icap_data_o[15]; |
assign brev_icap_data[ 9] = icap_data_o[14]; |
assign brev_icap_data[10] = icap_data_o[13]; |
assign brev_icap_data[11] = icap_data_o[12]; |
assign brev_icap_data[12] = icap_data_o[11]; |
assign brev_icap_data[13] = icap_data_o[10]; |
assign brev_icap_data[14] = icap_data_o[ 9]; |
assign brev_icap_data[15] = icap_data_o[ 8]; |
// |
initial o_wb_data = 16'h000; |
always @(posedge i_clk) |
if ((icap_posedge)&&((icap_ce_n)||(~icap_busy))) |
o_wb_data <= brev_icap_data; |
|
assign icap_dbg[25:0] = { |
i_wb_cyc,i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall, |
icap_posedge, icap_clk, icap_ce_n, icap_busy, icap_we_n, |
(icap_we_n)?icap_data_o : icap_data_i }; |
|
endmodule |
|
/wbicape6.v
0,0 → 1,304
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbicape6.v |
// |
// Project: Wishbone to ICAPE_SPARTAN6 interface conversion |
// |
// Purpose: This is a companion project to the ICAPE2 conversion, instead |
// involving a conversion from a 32-bit WISHBONE bus to read |
// and write the ICAPE_SPARTAN6 program. This is the 'non-simple' |
// portion of the interface, sporting all of the smarts necessary to run |
// the simple interface and make working with ICAPE as simple as |
// reading and writing from a wishbone bus. For example, register ID's |
// are given by bus addresses, even though they take extra cycles to |
// set and clear within the interface. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Following instructions on page 116-117 of the configuration guide ... |
// |
// W FFFF |
// W FFFF |
// W AA99 |
// W 5566 |
// W 2000 NOOP |
// W 2901 Write Type-1 packet header to read register 901?? |
// W 2000 NOOP |
// W 2000 NOOP |
// W 2000 NOOP |
// W 2000 NOOP |
// R vvvv Read register from previous packet header command |
// W 30A1 Write word to CMD register |
// W 000D DESYNC command |
// W 2000 NOOP |
// W 2000 NOOP |
// |
// Bits need to be bit-reversed within a byte |
// |
// |
// IPROG example |
// |
// W FFFF |
// W AA99 |
// W 5566 |
// W 3261 Write 1 words to GENERAL_1 |
// W xxxx write Multiboot start address [15:0] |
// W 3281 Write 1 words to GENERAL_2 |
// W xxxx write Opcode and multiboot start address [23:16] |
// W 32A1 Write 1 words to GENERAL_3 |
// W xxxx write Fallback start address |
// W 32C1 Write 1 words to GENERAL_4 |
// W xxxx write Opcode dne Fallback start address [23:16] |
// W 30A1 Write 1 word to CMD |
// W 000E IPGROG Cmd |
// W 2000 NOOP |
// |
// |
// |
// This fails when using wgregs on the XuLA2 board because the ICAPE port and |
// the JTAG port cannot both be active at the same time. |
// |
// |
`define ICAP_IDLE 5'h0 |
`define ICAP_START 5'h1 |
`define ICAP_CLOSE 5'hf |
module wbicape6(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, dbg_data); |
input i_clk; |
// Wishbone slave inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [5:0] i_wb_addr; |
input [31:0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output reg o_wb_stall; |
output wire [31:0] o_wb_data; |
output wire [31:0] dbg_data; |
|
// Interface to the lower level ICAPE port |
reg icap_cyc, icap_stb, icap_we; |
reg [15:0] icap_data_i; |
wire icap_ack, icap_stall; |
wire [15:0] icap_data_o; |
|
reg [4:0] state; |
reg r_we; |
reg [15:0] r_data; |
|
wire [25:0] icap_dbg; |
assign dbg_data = { i_wb_stb, state[3:0], r_we, icap_dbg }; |
|
reg stalled_state; |
reg [7:0] r_cmd_word; |
wire [15:0] w_cmd_word; |
assign w_cmd_word = { 3'b001, r_cmd_word, 5'h00 }; // Type-1 packet hdr |
initial icap_stb = 1'b0; |
initial icap_cyc = 1'b0; |
initial state = `ICAP_IDLE; |
always @(posedge i_clk) |
begin |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b0; |
if (stalled_state) |
state <= `ICAP_IDLE; |
else if ((~icap_stall)&&(state != `ICAP_IDLE)) |
state <= state + 1; |
case(state) |
`ICAP_IDLE: begin |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
state <= `ICAP_IDLE; |
r_data <= i_wb_data[15:0]; |
r_we <= i_wb_we; |
if ((i_wb_cyc)&&(i_wb_stb)) |
begin |
state <= `ICAP_START; |
icap_stb <= i_wb_stb; |
icap_cyc <= i_wb_cyc; |
icap_we <= 1'b1; |
icap_data_i <= 16'hffff; |
r_cmd_word <= { (i_wb_we)? 2'b10:2'b01, i_wb_addr }; |
o_wb_stall <= 1'b1; |
end end |
`ICAP_START: begin |
if (~icap_stall) |
icap_data_i <= 16'hffff; |
end |
5'h2: begin |
if (~icap_stall) |
icap_data_i <= 16'haa99; |
end |
5'h3: begin |
if (~icap_stall) |
icap_data_i <= 16'h5566; |
end |
5'h4: begin |
if (~icap_stall) |
icap_data_i <= 16'h2000; |
end |
5'h5: begin |
if (~icap_stall) |
begin |
icap_data_i <= w_cmd_word; // Includes address |
end end |
5'h6: begin // Write |
if (~icap_stall) |
begin |
if (r_we) |
icap_data_i <= r_data; |
else |
icap_data_i <= 16'h2000; |
end end |
5'h7: begin |
// Need to send four NOOPs before we can begin |
// reading. Send the four NOOPs for a write anyway. |
if (~icap_stall) |
icap_data_i <= 16'h2000; |
end |
5'h8: begin |
if (~icap_stall) |
icap_data_i <= 16'h2000; |
end |
5'h9: begin |
if (~icap_stall) |
begin |
icap_data_i <= 16'h2000; |
if (r_we) |
state <= `ICAP_CLOSE; |
end end |
5'ha: begin |
if (~icap_stall) |
begin |
// We now request the chip enable line be |
// dropped, so we can switch from writing to |
// reading |
icap_data_i <= 16'h2000; |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
end end |
5'hb: begin |
if (~icap_stall) |
begin |
// Switch the write line to read, must be done |
// w/the chip enable off (hence _cyc=0). O/w |
// the interface will abort. |
icap_data_i <= 16'h2000; |
icap_we <=1'b0; |
end end |
5'hc: begin |
if (~icap_stall) |
begin |
// We can finally issue our read command |
// Re-activate the interface, and read |
icap_data_i <= 16'h2000; |
icap_stb <= 1'b1; |
icap_cyc <= 1'b1; |
end end |
5'hd: begin |
if (~icap_stall) |
begin |
// De-activate the interface again so we can |
// switch back to write. |
icap_data_i <= 16'h2000; |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
end end |
5'he: begin |
if (~icap_stall) |
begin |
// Switch back to write while the interface |
// is deactivated. |
icap_we <= 1'b1; |
icap_data_i <= 16'h2000; |
end end |
`ICAP_CLOSE: begin |
if (~icap_stall) |
begin |
icap_we <= 1'b1; |
// Type 1: Write 1 word to CMD register |
icap_data_i <= 16'h30a1; |
r_data <= icap_data_o; |
icap_stb <= 1'b1; |
icap_cyc <= 1'b1; |
end end |
5'h10: begin // DESYNC Command |
if (~icap_stall) |
begin |
icap_data_i <= 16'h000d; |
end end |
5'h11: begin // DESYNC must be followed by two NOOPs |
if (~icap_stall) |
begin |
icap_data_i <= 16'h2000; |
end end |
5'h12: begin // NOOP |
if (~icap_stall) |
begin |
icap_data_i <= 16'h2000; |
state <= `ICAP_IDLE; |
o_wb_ack <= 1'b1; |
o_wb_stall <= 1'b0; |
end end |
default: begin |
// If we were in the middle of a bus cycle, and got |
// here then ... we just failed that cycle. Setting |
// the bus error flag would be appropriate, but we |
// have no such flag to our interface. Hence we just |
// drop things and depend upon a bus watchdog to |
// catch that we aren't answering. |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b0; |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
state <= `ICAP_IDLE; |
end |
endcase |
end |
|
wbicapesimple spartancfg(i_clk, icap_cyc, icap_stb, icap_we, |
icap_data_i, |
icap_ack, icap_stall, icap_data_o, |
icap_dbg); |
|
|
assign o_wb_data = { 16'h0000, r_data }; |
|
reg [3:0] last_state; |
initial last_state = `ICAP_IDLE; |
always @(posedge i_clk) |
last_state <= state; |
|
reg [11:0] reset_ctr; |
always @(posedge i_clk) |
if (last_state != state) |
reset_ctr <= 0; |
else if (state == `ICAP_IDLE) |
reset_ctr <= 0; |
else |
reset_ctr <= reset_ctr + 1; |
always @(posedge i_clk) |
stalled_state <= (&reset_ctr); |
|
endmodule |
/wbscopc.v
0,0 → 1,212
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbscopc.v |
// |
// Project: FPGA Library of Routines |
// |
// Purpose: This scope is identical in function to the wishbone scope |
// found in wbscope, save that the output is compressed and that (as a |
// result) it can only handle recording 31 bits at a time. This allows |
// the top bit to indicate an 'address difference'. Okay, there's |
// another difference as well: this version only works in a synchronous |
// fashion with the clock from the WB bus. You cannot have a separate |
// bus and data clock. |
// |
// Reading/decompressing the output of this scope works in this fashion: |
// Once the scope has stopped, read from the port. Any time the high |
// order bit is set, the other 31 bits tell you how many times to repeat |
// the last value. If the high order bit is not set, then the value |
// is a new data value. |
// |
// I've provided this version of a compressed scope to OpenCores for |
// discussion purposes. While wbscope.v works and works well by itself, |
// this compressed scope has a couple of fundamental flaw that I have |
// yet to fix. One of them is that it is impossible to know when the |
// trigger took place. The second problem is that it may be impossible |
// to know the state of the scope at the beginning of the buffer--should |
// the buffer begin with an address difference value instead of a data |
// value. |
// |
// Ideally, the first item read out of the scope should be a data value, |
// even if the scope was skipping values to a new address at the time. |
// If it was in the middle of a skip, the next item out of the scope |
// should be the skip length. This, though, violates the rule that there |
// are (1<<LGMEMLEN) items in the memory, and that the trigger took place |
// on the last item of memory ... so that portion of this compressed |
// scope is still to be defined. |
// |
// Like I said, this version is placed here for discussion purposes, |
// not because it runs well nor because I have recognized that it has any |
// particular value (yet). |
// |
// Well, I take that back. When dealing with an interface such as the |
// PS/2 interface, or even the 16x2 LCD interface, it is often true |
// that things change _very_ slowly. They could change so slowly that |
// the other approach to the scope doesn't work. This then gives you |
// a working scope, by only capturing the changes. You'll still need |
// to figure out (after the fact) when the trigge took place. Perhaps |
// you'll wish to add the trigger as another data line, so you can find |
// when it took place in your own data? |
// |
// Okay, I take that back twice: I'm finding this compressed scope very |
// valuable for evaluating the timing associated with a GPS PPS and |
// associated NMEA stream. I need to collect over a seconds worth of |
// data, and I don't have enough memory to handle one memory value per |
// clock, yet I still want to know exactly when the GPS PPS goes high, |
// when it goes low, when I'm adjusting my clock, and when the clock's |
// PPS output goes high. Did I synchronize them well? Oh, and when does |
// the NMEA time string show up when compared with the PPS? All of those |
// are valuable, but could never be done if the scope wasn't compressed. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
///////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbscopc(i_clk, i_ce, i_trigger, i_data, |
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_interrupt); |
parameter LGMEM = 5'd10, NELM=32, BUSW = 32, SYNCHRONOUS=1; |
// The input signals that we wish to record |
input i_clk, i_ce, i_trigger; |
input [(NELM-1):0] i_data; |
// The WISHBONE bus for reading and configuring this scope |
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we; |
input i_wb_addr; // One address line only |
input [(BUSW-1):0] i_wb_data; |
output wire o_wb_ack, o_wb_stall; |
output wire [(BUSW-1):0] o_wb_data; |
// And, finally, for a final flair --- offer to interrupt the CPU after |
// our trigger has gone off. This line is equivalent to the scope |
// being stopped. It is not maskable here. |
output wire o_interrupt; |
|
|
// Let's first see how far we can get by cheating. We'll use the |
// wbscope program, and suffer a lack of several features |
|
// When is the full scope reset? Capture that reset bit from any |
// write. |
wire lcl_reset; |
assign lcl_reset = (i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)&&(i_wb_we) |
&&(~i_wb_data[31]); |
|
// A big part of this scope is the 'address' of any particular |
// data value. As of this current version, the 'address' changed |
// in definition from an absolute time (which had all kinds of |
// problems) to a difference in time. Hence, when the address line |
// is high on decompression, the 'address' field will record an |
// address difference. |
// |
// To implement this, we set our 'address' to zero any time the |
// data changes, but increment it on all other clocks. Should the |
// address difference get to our maximum value, we let it saturate |
// rather than overflow. |
reg [(BUSW-2):0] ck_addr; |
reg [(NELM-1):0] lst_dat; |
initial ck_addr = 0; |
always @(posedge i_clk) |
if ((lcl_reset)||((i_ce)&&(i_data != lst_dat))) |
ck_addr <= 0; |
else if (&ck_addr) |
; // Saturated (non-overflowing) address diff |
else |
ck_addr <= ck_addr + 1; |
|
// |
// To do our compression, we keep track of two registers: the most |
// recent data to the device (imm_ prefix) and the data from one |
// clock ago. This allows us to suppress writes to the scope which |
// would otherwise be two address writes in a row. |
reg imm_adr, lst_adr; // Is this an address (1'b1) or data value? |
reg [(BUSW-2):0] lst_val, // Data for the scope, delayed by one |
imm_val; // Data to write to the scope |
initial lst_dat = 0; |
initial lst_adr = 1'b1; |
initial imm_adr = 1'b1; |
always @(posedge i_clk) |
if (lcl_reset) |
begin |
imm_val <= 31'h0; |
imm_adr <= 1'b1; |
lst_val <= 31'h0; |
lst_adr <= 1'b1; |
lst_dat <= 0; |
end else if ((i_ce)&&(i_data != lst_dat)) |
begin |
imm_val <= { {(BUSW-1-NELM){1'b0}}, i_data }; |
imm_adr <= 1'b0; |
lst_val <= imm_val; |
lst_adr <= imm_adr; |
lst_dat <= i_data; |
end else begin |
imm_val <= ck_addr; // Minimum value here is '1' |
imm_adr <= 1'b1; |
lst_val <= imm_val; |
lst_adr <= imm_adr; |
end |
|
// |
// Here's where we suppress writing pairs of address words to the |
// scope at once. |
// |
reg r_ce; |
reg [(BUSW-1):0] r_data; |
initial r_ce = 1'b0; |
always @(posedge i_clk) |
r_ce <= (~lst_adr)||(~imm_adr); |
always @(posedge i_clk) |
r_data <= ((~lst_adr)||(~imm_adr)) |
? { lst_adr, lst_val } |
: { {(32 - NELM){1'b0}}, i_data }; |
|
|
// |
// The trigger needs some extra attention, in order to keep triggers |
// that happen between events from being ignored. |
// |
wire w_trigger; |
assign w_trigger = (r_trigger)||(i_trigger); |
|
reg r_trigger; |
initial r_trigger = 1'b0; |
always @(posedge i_clk) |
if (lcl_reset) |
r_trigger <= 1'b0; |
else |
r_trigger <= w_trigger; |
|
// |
// Call the regular wishbone scope to do all of our real work, now |
// that we've compressed the input. |
// |
wbscope #(.SYNCHRONOUS(1), .LGMEM(LGMEM), |
.BUSW(BUSW)) cheatersscope(i_clk, r_ce, w_trigger, r_data, |
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, o_interrupt); |
endmodule |
/wbscope.v
0,0 → 1,333
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbscope.v |
// |
// Project: FPGA Library of Routines |
// |
// Purpose: This is a generic/library routine for providing a bus accessed |
// 'scope' or (perhaps more appropriately) a bus accessed logic |
// analyzer. The general operation is such that this 'scope' can |
// record and report on any 32 bit value transiting through the |
// FPGA. Once started and reset, the scope records a copy of the |
// input data every time the clock ticks with the circuit enabled. |
// That is, it records these values up until the trigger. Once |
// the trigger goes high, the scope will record for bw_holdoff |
// more counts before stopping. Values may then be read from the |
// buffer, oldest to most recent. After reading, the scope may |
// then be reset for another run. |
// |
// In general, therefore, operation happens in this fashion: |
// 1. A reset is issued. |
// 2. Recording starts, in a circular buffer, and continues until |
// 3. The trigger line is asserted. |
// The scope registers the asserted trigger by setting |
// the 'o_triggered' output flag. |
// 4. A counter then ticks until the last value is written |
// The scope registers that it has stopped recording by |
// setting the 'o_stopped' output flag. |
// 5. The scope recording is then paused until the next reset. |
// 6. While stopped, the CPU can read the data from the scope |
// 7. -- oldest to most recent |
// 8. -- one value per i_rd&i_clk |
// 9. Writes to the data register reset the address to the |
// beginning of the buffer |
// |
// Although the data width DW is parameterized, it is not very changable, |
// since the width is tied to the width of the data bus, as is the |
// control word. Therefore changing the data width would require changing |
// the interface. It's doable, but it would be a change to the interface. |
// |
// The SYNCHRONOUS parameter turns on and off meta-stability |
// synchronization. Ideally a wishbone scope able to handle one or two |
// clocks would have a changing number of ports as this SYNCHRONOUS |
// parameter changed. Other than running another script to modify |
// this, I don't know how to do that so ... we'll just leave it running |
// off of two clocks or not. |
// |
// |
// Internal to this routine, registers and wires are named with one of the |
// following prefixes: |
// |
// i_ An input port to the routine |
// o_ An output port of the routine |
// br_ A register, controlled by the bus clock |
// dr_ A register, controlled by the data clock |
// bw_ A wire/net, controlled by the bus clock |
// dw_ A wire/net, controlled by the data clock |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
///////////////////////////////////////////////////////////////////////////// |
module wbscope(i_clk, i_ce, i_trigger, i_data, |
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_interrupt); |
parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1; |
// The input signals that we wish to record |
input i_clk, i_ce, i_trigger; |
input [(BUSW-1):0] i_data; |
// The WISHBONE bus for reading and configuring this scope |
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we; |
input i_wb_addr; // One address line only |
input [(BUSW-1):0] i_wb_data; |
output wire o_wb_ack, o_wb_stall; |
output reg [(BUSW-1):0] o_wb_data; |
// And, finally, for a final flair --- offer to interrupt the CPU after |
// our trigger has gone off. This line is equivalent to the scope |
// being stopped. It is not maskable here. |
output wire o_interrupt; |
|
reg [(LGMEM-1):0] raddr; |
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)]; |
|
// Our status/config register |
wire bw_reset_request, bw_manual_trigger, |
bw_disable_trigger, bw_reset_complete; |
reg [22:0] br_config; |
wire [19:0] bw_holdoff; |
initial br_config = ((1<<(LGMEM-1))-4); |
always @(posedge i_wb_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)) |
begin |
if (i_wb_we) |
br_config <= { i_wb_data[31], |
(i_wb_data[27]), |
i_wb_data[26], |
i_wb_data[19:0] }; |
end else if (bw_reset_complete) |
br_config[22] <= 1'b1; |
assign bw_reset_request = (~br_config[22]); |
assign bw_manual_trigger = (br_config[21]); |
assign bw_disable_trigger = (br_config[20]); |
assign bw_holdoff = br_config[19:0]; |
|
wire dw_reset, dw_manual_trigger, dw_disable_trigger; |
generate |
if (SYNCHRONOUS > 0) |
begin |
assign dw_reset = bw_reset_request; |
assign dw_manual_trigger = bw_manual_trigger; |
assign dw_disable_trigger = bw_disable_trigger; |
assign bw_reset_complete = bw_reset_request; |
end else begin |
reg r_reset_complete; |
reg [2:0] r_iflags, q_iflags; |
|
// Resets are synchronous to the bus clock, not the data clock |
// so do a clock transfer here |
initial q_iflags = 3'b000; |
initial r_reset_complete = 1'b0; |
always @(posedge i_clk) |
begin |
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger }; |
r_iflags <= q_iflags; |
r_reset_complete <= (dw_reset); |
end |
|
assign dw_reset = r_iflags[2]; |
assign dw_manual_trigger = r_iflags[1]; |
assign dw_disable_trigger = r_iflags[0]; |
|
reg q_reset_complete, qq_reset_complete; |
// Pass an acknowledgement back from the data clock to the bus |
// clock that the reset has been accomplished |
initial q_reset_complete = 1'b0; |
initial qq_reset_complete = 1'b0; |
always @(posedge i_wb_clk) |
begin |
q_reset_complete <= r_reset_complete; |
qq_reset_complete <= q_reset_complete; |
end |
|
assign bw_reset_complete = qq_reset_complete; |
end endgenerate |
|
// |
// Set up the trigger |
// |
// |
// Write with the i-clk, or input clock. All outputs read with the |
// WISHBONE-clk, or i_wb_clk clock. |
reg dr_triggered, dr_primed; |
wire dw_trigger; |
assign dw_trigger = (dr_primed)&&( |
((i_trigger)&&(~dw_disable_trigger)) |
||(dr_triggered) |
||(dw_manual_trigger)); |
initial dr_triggered = 1'b0; |
always @(posedge i_clk) |
if (dw_reset) |
dr_triggered <= 1'b0; |
else if ((i_ce)&&(dw_trigger)) |
dr_triggered <= 1'b1; |
|
// |
// Determine when memory is full and capture is complete |
// |
// Writes take place on the data clock |
reg dr_stopped; |
reg [19:0] counter; // This is unsigned |
initial dr_stopped = 1'b0; |
initial counter = 20'h0000; |
always @(posedge i_clk) |
if (dw_reset) |
begin |
counter <= 0; |
dr_stopped <= 1'b0; |
end else if ((i_ce)&&(dr_triggered)) |
begin // MUST BE a < and not <=, so that we can keep this w/in |
// 20 bits. Else we'd need to add a bit to comparison |
// here. |
if (counter < bw_holdoff) |
counter <= counter + 20'h01; |
else |
dr_stopped <= 1'b1; |
end |
|
// |
// Actually do our writes to memory. Record, via 'primed' when |
// the memory is full. |
// |
// The 'waddr' address that we are using really crosses two clock |
// domains. While writing and changing, it's in the data clock |
// domain. Once stopped, it becomes part of the bus clock domain. |
// The clock transfer on the stopped line handles the clock |
// transfer for these signals. |
// |
reg [(LGMEM-1):0] waddr; |
initial waddr = {(LGMEM){1'b0}}; |
initial dr_primed = 1'b0; |
always @(posedge i_clk) |
if (dw_reset) // For simulation purposes, supply a valid value |
begin |
waddr <= 0; // upon reset. |
dr_primed <= 1'b0; |
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff))) |
begin |
// mem[waddr] <= i_data; |
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1}; |
dr_primed <= (dr_primed)||(&waddr); |
end |
always @(posedge i_clk) |
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff))) |
mem[waddr] <= i_data; |
|
// |
// Clock transfer of the status signals |
// |
wire bw_stopped, bw_triggered, bw_primed; |
generate |
if (SYNCHRONOUS > 0) |
begin |
assign bw_stopped = dr_stopped; |
assign bw_triggered = dr_triggered; |
assign bw_primed = dr_primed; |
end else begin |
// These aren't a problem, since none of these are strobe |
// signals. They goes from low to high, and then stays high |
// for many clocks. Swapping is thus easy--two flip flops to |
// protect against meta-stability and we're done. |
// |
reg [2:0] q_oflags, r_oflags; |
initial q_oflags = 3'h0; |
initial r_oflags = 3'h0; |
always @(posedge i_wb_clk) |
if (bw_reset_request) |
begin |
q_oflags <= 3'h0; |
r_oflags <= 3'h0; |
end else begin |
q_oflags <= { dr_stopped, dr_triggered, dr_primed }; |
r_oflags <= q_oflags; |
end |
|
assign bw_stopped = r_oflags[2]; |
assign bw_triggered = r_oflags[1]; |
assign bw_primed = r_oflags[0]; |
end endgenerate |
|
// Reads use the bus clock |
reg br_wb_ack; |
initial br_wb_ack = 1'b0; |
wire bw_cyc_stb; |
assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb)); |
always @(posedge i_wb_clk) |
begin |
if ((bw_reset_request) |
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we))) |
raddr <= 0; |
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped)) |
raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped |
|
if ((bw_cyc_stb)&&(~i_wb_we)) |
begin // Read from the bus |
br_wb_ack <= 1'b1; |
end else if ((bw_cyc_stb)&&(i_wb_we)) |
// We did this write above |
br_wb_ack <= 1'b1; |
else // Do nothing if either i_wb_cyc or i_wb_stb are low |
br_wb_ack <= 1'b0; |
end |
|
reg [31:0] nxt_mem; |
always @(posedge i_wb_clk) |
nxt_mem <= mem[raddr+waddr+ |
(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ? |
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )]; |
|
wire [4:0] bw_lgmem; |
assign bw_lgmem = LGMEM; |
always @(posedge i_wb_clk) |
if (~i_wb_addr) // Control register read |
o_wb_data <= { bw_reset_request, |
bw_stopped, |
bw_triggered, |
bw_primed, |
bw_manual_trigger, |
bw_disable_trigger, |
(raddr == {(LGMEM){1'b0}}), |
bw_lgmem, |
bw_holdoff }; |
else if (~bw_stopped) // read, prior to stopping |
o_wb_data <= i_data; |
else // if (i_wb_addr) // Read from FIFO memory |
o_wb_data <= nxt_mem; // mem[raddr+waddr]; |
|
assign o_wb_stall = 1'b0; |
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack); |
|
reg br_level_interrupt; |
initial br_level_interrupt = 1'b0; |
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger) |
&&(~br_level_interrupt); |
always @(posedge i_wb_clk) |
if ((bw_reset_complete)||(bw_reset_request)) |
br_level_interrupt<= 1'b0; |
else |
br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger); |
|
endmodule |