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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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  • This comparison shows the changes necessary to convert path
    /xulalx25soc/trunk/rtl
    from Rev 34 to Rev 37
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Rev 34 → Rev 37

/wbsdram.v
458,10 → 458,24
r_barrell_ack[(RDLY-1):0] <= 0;
end
 
 
`ifdef VERILATOR
// While I hate to build something that works one way under Verilator
// and another way in practice, this really isn't that. The problem
// Verilator is having is resolved in toplevel.v--one file that
// Verilator doesn't implement. In toplevel.v, there's not only a
// single clocked latch but two taking place. Here, we replicate one
// of those. The second takes place (somehow) within the sdramsim.cpp
// file.
reg [15:0] ram_data, last_ram_data;
always @(posedge i_clk)
ram_data <= i_ram_data;
always @(posedge i_clk)
last_ram_data <= ram_data;
`else
reg [15:0] last_ram_data;
always @(posedge i_clk)
last_ram_data <= i_ram_data;
`endif
assign o_wb_ack = r_barrell_ack[0];
assign o_wb_data = { last_ram_data, i_ram_data };
 

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