URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/rtl
- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/uartdev.v
44,7 → 44,7
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_rx_int, o_tx_int); |
parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd10417 }; |
parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 }; |
input i_clk, i_rx_uart; |
output wire o_tx_uart; |
input i_wb_cyc, i_wb_stb, i_wb_we; |
65,7 → 65,7
|
initial r_tx_stb = 1'b0; |
always @(posedge i_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b10)) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b11)) |
begin |
// Note: there's no check for overflow here. |
// You're on your own: verify that the device |
100,12 → 100,12
case(i_wb_addr) |
2'b00: o_wb_data <= { 2'b00, r_setup }; |
2'b01: o_wb_data <= { 2'b00, r_setup }; |
2'b10: o_wb_data <= { 31'h00,tx_busy }; |
2'b11: begin |
2'b10: begin |
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we)) |
rx_rdy <= rx_stb; |
o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data }; |
end |
2'b11: o_wb_data <= { 31'h00,tx_busy }; |
endcase |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); // Read or write, we ack |
end |