URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc/trunk/rtl
- from Rev 66 to Rev 67
- ↔ Reverse comparison
Rev 66 → Rev 67
/cpu/zipjiffies.v
67,7 → 67,7
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_int); |
parameter BW = 32, VW = (BW-2); |
parameter BW = 32; |
input i_clk, i_ce; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
104,13 → 104,13
|
initial new_set = 1'b0; |
always @(posedge i_clk) |
begin |
// Delay things by a clock to simplify our logic |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
begin |
new_set <= 1'b1; |
new_when<= i_wb_data; |
end else |
new_set <= 1'b0; |
new_set <= ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)); |
// new_when is a don't care when new_set = 0, so don't worry |
// about setting it at all times. |
new_when<= i_wb_data; |
end |
|
initial o_int = 1'b0; |
initial int_set = 1'b0; |
118,16 → 118,18
begin |
o_int <= 1'b0; |
if ((i_ce)&&(int_set)&&(r_counter == int_when)) |
begin // Interrupts are self-clearing |
o_int <= 1'b1; // Set the interrupt flag |
int_set <= 1'b0;// Clear the interrupt |
end |
// Interrupts are self-clearing |
o_int <= 1'b1; // Set the interrupt flag for one clock |
else if ((new_set)&&(till_wb <= 0)) |
o_int <= 1'b1; |
|
if ((new_set)&&(till_wb > 0)) |
int_set <= 1'b1; |
else if ((i_ce)&&(r_counter == int_when)) |
int_set <= 1'b0; |
|
if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set))) |
begin |
int_when <= new_when; |
int_set <= ((int_set)||(till_wb>0)); |
end |
end |
|
// |