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  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk/rtl
    from Rev 73 to Rev 74
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  •

Rev 73 → Rev 74

/sdspi.v
0,0 → 1,?rev2len?
link ../../../opencores/sdspi/trunk/rtl/export.v
sdspi.v Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: wbspiflash.v =================================================================== --- wbspiflash.v (revision 73) +++ wbspiflash.v (revision 74) @@ -91,7 +91,8 @@ o_wb_ack, o_wb_stall, o_wb_data, // Quad Spi connections to the external device o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso, - o_interrupt); + o_interrupt, + i_bus_grant); parameter AW=18, // Address width, -2 for 32-bit word access PW=6, // Page address width (256 bytes,64 words) SW=10; // Sector address width (4kB, 1kW) @@ -113,6 +114,9 @@ input i_spi_miso; // Interrupt line output reg o_interrupt; + // Do we own the bus? + input i_bus_grant; + // output wire [31:0] o_debug; reg spi_wr, spi_hold; @@ -127,7 +131,8 @@ spi_wr, spi_hold, spi_in, spi_len, spi_out, spi_valid, spi_busy, w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi, - i_spi_miso); + i_spi_miso, + i_bus_grant); // Erase status tracking reg write_in_progress, write_protect;
/Makefile
54,9 → 54,9
wbutohex.v
PERIPHERALS: wbgpio.v wbpwmaudio.v rxuart.v txuart.v uartdev.v \
rtcdate.v rtclight.v
SOURCES := busmaster.v wbscope.v wbsdram.v \
ioslave.v rtclight.v rtcdate.v \
wbspiflash.v lldspi.v \
SOURCES := busmaster.v wbscope.v wbsdram.v \
ioslave.v rtclight.v rtcdate.v \
wbspiflash.v lldspi.v sdspi.v spiarbiter.v \
$(CPUSOURCES) $(JTAGBUS) $(PERIPHERALS)
 
$(VDIRFB)/Vbusmaster__ALL.a: $(VDIRFB)/Vbusmaster.h $(VDIRFB)/Vbusmaster.cpp
/uartdev.v
43,7 → 43,7
module uartdev(i_clk, i_rx_uart, o_tx_uart,
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_rx_int, o_tx_int);
o_rx_int, o_tx_int, o_debug);
parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 };
input i_clk, i_rx_uart;
output wire o_tx_uart;
54,6 → 54,7
output wire o_wb_stall;
output reg [31:0] o_wb_data;
output wire o_rx_int, o_tx_int;
output wire [31:0] o_debug;
 
reg [29:0] r_setup;
reg r_tx_stb, rx_rdy;
113,5 → 114,11
assign o_wb_stall = 1'b0;
assign o_rx_int = rx_stb;
assign o_tx_int = ~tx_busy;
 
assign o_debug = { (~i_rx_uart)||(~o_tx_uart), tx_busy, i_wb_addr,
rx_break, rx_frame_err, rx_parity_err, rx_rdy,
i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack,
rx_stb, rx_data,
r_tx_stb, r_tx_data,
i_rx_uart, o_tx_uart };
endmodule
/lldspi.v
43,6 → 43,7
`define SPI_HOLDING 3'h4
`define SPI_STOP 3'h5
`define SPI_STOP_B 3'h6
`define SPI_WAIT 3'h7
 
// Modes
// `define SPI_MOD_SPI 2'b00
54,7 → 55,9
i_wr, i_hold, i_word, i_len,
o_word, o_valid, o_busy,
// QSPI interface
o_sck, o_cs_n, i_cs_n, o_mosi, i_miso);
o_sck, o_cs_n, i_cs_n, o_mosi, i_miso,
// Bus grant information
i_bus_grant);
input i_clk;
// Chip interface
// Can send info
72,6 → 75,8
input i_cs_n; // Feedback from the arbiter
output reg o_mosi;
input i_miso;
// Bus grant
input i_bus_grant;
 
reg [5:0] spi_len;
reg [31:0] r_word;
93,12 → 98,16
if (i_wr)
begin
r_word <= i_word;
state <= `SPI_START;
state <= `SPI_WAIT;
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
o_cs_n <= 1'b0;
o_busy <= 1'b1;
o_sck <= 1'b1;
end
end else if (state == `SPI_WAIT)
begin
if (i_bus_grant)
state <= `SPI_START;
end else if (state == `SPI_START)
begin // We come in here with sck high, stay here 'til sck is low
if (~i_cs_n) // Wait 'til the bus has been granted
/ioslave.v
68,12 → 68,14
output wire [(NGPO-1):0] o_gpio;
// Other registers
input [31:0] i_bus_err_addr;
input [5:0] brd_interrupts;
output wire [7:0] o_ints_to_zip_cpu;
input [6:0] brd_interrupts;
output wire [8:0] o_ints_to_zip_cpu;
output wire o_interrupt;
 
 
wire i_uart_rx_int, i_uart_tx_int, i_scop_int, i_flash_int,i_pwm_int;
wire i_sdcard_int, i_uart_tx_int, i_uart_rx_int, i_pwm_int,
i_scop_int, i_flash_int;
assign i_sdcard_int = brd_interrupts[6];
assign i_uart_tx_int = brd_interrupts[5];
assign i_uart_rx_int = brd_interrupts[4];
assign i_pwm_int = brd_interrupts[3];
191,7 → 193,8
 
//
//
assign o_ints_to_zip_cpu = { i_uart_tx_int, i_uart_rx_int,
assign o_ints_to_zip_cpu = { i_sdcard_int,
i_uart_tx_int, i_uart_rx_int,
i_pwm_int, gpio_int, i_scop_int, i_flash_int,
ck_int, o_interrupt };
endmodule
/busmaster.v
51,11 → 51,13
`define IMPLEMENT_ONCHIP_RAM
`ifndef VERILATOR
`ifndef XULA25
`define FANCY_ICAP_ACCESS
// `define FANCY_ICAP_ACCESS
`endif
`endif
`define FLASH_ACCESS
// `define SDCARD_ACCESS // Not built yet ...
`ifdef XULA25
`define SDCARD_ACCESS
`endif
//
 
 
73,15 → 75,23
// `define WBUS_SCOPE // Occupies the FLASH_SCOPE location, so both cannot be active
`endif
//
// Position #2: The ICAP configuration scope
// Position #2: The ICAP configuration scope, could also be the SDCard scope
// depending on how we configure ourselves here
//
`ifdef XULA25
`ifdef FANCY_ICAP_ACCESS
`define CFG_SCOPE // Only defined if we have the access ...
`else
`ifdef SDCARD_ACCESS
`define SDCARD_SCOPE
`endif
`endif
`endif
//
// Position #3: The SDRAM scope
// Position #3: The SDRAM scope / UART scope (never both)
//
`define SDRAM_SCOPE
// `define SDRAM_SCOPE
// `define UART_SCOPE
//
// Position #4: The Zip CPU scope
//
185,11 → 195,11
wire zip_ack, zip_stall, zip_err;
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
wire [31:0] dwb_addr, dwb_odata;
wire [7:0] w_ints_to_zip_cpu;
wire [8:0] w_ints_to_zip_cpu;
`ifdef INCLUDE_ZIPCPU
`ifdef XULA25
wire [31:0] zip_debug;
zipsystem #(24'h2000,ZA,8,1,8)
zipsystem #(24'h2000,ZA,8,1,9)
zippy(i_clk, 1'b0,
// Zippys wishbone interface
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
371,7 → 381,11
// zip_sel is not on the bus at this point
assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
`ifdef SDCARD_ACCESS
assign sdcard_sel=((wb_cyc)&&(wb_addr[31:2]== 30'h48));
`else
assign sdcard_sel=1'b0;
`endif
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
 
assign none_sel =((wb_cyc)&&(wb_stb)&&(~
414,7 → 428,7
if (wb_err)
bus_err_addr <= wb_addr;
 
wire flash_interrupt, scop_interrupt,
wire flash_interrupt, sdcard_interrupt, scop_interrupt,
uart_rx_int, uart_tx_int, pwm_int;
// The I/O processor, herein called an ioslave
ioslave #(NGPO, NGPI) runio(i_clk,
422,7 → 436,9
wb_data, io_ack, io_stall, io_data,
i_gpio, o_gpio,
bus_err_addr,
{ uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
{
sdcard_interrupt,
uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
flash_interrupt,
`ifdef XULA25
zip_cpu_int
440,11 → 456,13
//
// UART device
//
wire [31:0] uart_debug;
uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
wb_cyc, (wb_stb)&&(uart_sel), wb_we,
{ ~wb_addr[2], wb_addr[0]}, wb_data,
uart_ack, uart_stall, uart_data,
uart_rx_int, uart_tx_int);
uart_rx_int, uart_tx_int,
uart_debug);
 
//
// PWM (audio) device
455,11 → 473,7
// second parameter is zero or one, indicating whether or not the
// audio rate can be adjusted (1), or whether it is fixed within the
// build (0).
`ifdef XULA25
wbpwmaudio #(32'd1814,1) // 44.1 kHz, user adjustable
`else
wbpwmaudio #(32'h10000,0) // 8 kHz, fixed audio rate
`endif
wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
pwmdev(i_clk,
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
470,6 → 484,7
// FLASH MEMORY CONFIGURATION ACCESS
//
wire flash_cs_n, flash_sck, flash_mosi;
wire spi_user, sdcard_grant, flash_grant;
`ifdef FLASH_ACCESS
wbspiflash flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
476,7 → 491,7
wb_addr[17:0], wb_data,
flash_ack, flash_stall, flash_data,
flash_sck, flash_cs_n, o_sf_cs_n, flash_mosi, i_spi_miso,
flash_interrupt);
flash_interrupt, flash_grant);
`else
reg r_flash_ack;
initial r_flash_ack = 1'b0;
491,17 → 506,45
assign flash_cs_n = 1'b1;
assign flash_sck = 1'b1;
assign flash_mosi = 1'b1;
 
This is an error
`endif
 
//
// SDCARD ACCESS
//
wire sdcard_cs_n, sdcard_sck, sdcard_mosi;
wire [31:0] sdspi_scope;
`ifdef SDCARD_ACCESS
sdspi sdcard_controller(i_clk,
// Wishbone interface
wb_cyc, (wb_stb)&&(sdcard_sel), wb_we, wb_addr[1:0], wb_data,
// return
sdcard_ack, sdcard_stall, sdcard_data,
// SPI interface
sdcard_cs_n, sdcard_sck, sdcard_mosi, i_spi_miso,
sdcard_interrupt, sdcard_grant, sdspi_scope);
`else
reg r_sdcard_ack;
initial r_sdcard_ack = 1'b0;
always @(posedge i_clk)
r_sdcard_ack <= (wb_cyc)&&(wb_stb)&&(sdcard_sel);
assign sdcard_stall = 1'b0;
assign sdcard_ack = r_sdcard_ack;
assign sdcard_data = 32'h0000;
assign sdcard_interrupt= 1'b0;
`endif // SDCARD_ACCESS
 
 
`ifdef FLASH_ACCESS
`ifdef SDCARD_ACCESS
spiarbiter spichk(i_clk,
// Channel zero
flash_cs_n, flash_sck, flash_mosi,
// Channel one
sdcard_cs_n, sdcard_sck, sdcard_mosi,
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi);
This is an error
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi,
spi_user);
assign sdcard_grant = spi_user;
assign flash_grant = ~spi_user;
`else
// Flash access, but no SD card access
assign o_sf_cs_n = flash_cs_n;
508,6 → 551,7
assign o_sd_cs_n = 1'b1;
assign o_spi_sck = flash_sck;
assign o_spi_mosi = flash_mosi;
assign spi_user = 1'b0;
`endif // SDCARD_ACCESS && FLASH_ACCESS
`else // FLASH_ACCESS
`ifdef SDCARD_ACCESS
516,6 → 560,7
assign o_sd_cs_n = sdcard_cs_n;
assign o_spi_sck = sdcard_sck;
assign o_spi_mosi = sdcard_mosi;
assign spi_user = 1'b1;
`else
// No SPI access ...
assign o_sf_cs_n = 1'b1;
522,6 → 567,7
assign o_sd_cs_n = 1'b1;
assign o_spi_sck = 1'b1;
assign o_spi_mosi = 1'b1;
assign spi_user = 1'b0;
`endif // SDCARD_ACCESS, w/o FLASH_ACCESS
`endif // !FLASH_ACCESS
 
650,14 → 696,26
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
scop_cfg_interrupt);
`else
`ifdef SDCARD_SCOPE
wire scop_sd_trigger, scop_sd_ce;
assign scop_sd_trigger = (wb_cyc)&&(wb_stb)&&(sdcard_sel)&&(wb_we);
assign scop_sd_ce = 1'b1; // sdspi_scope[31];
wbscope #(5'h9) sdspiscope(i_clk, scop_sd_ce,
scop_sd_trigger, sdspi_scope,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
wb_we, wb_addr[0], wb_data,
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,scop_cfg_interrupt);
`else
assign scop_cfg_data = 32'h00;
assign scop_cfg_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01);
assign scop_cfg_stall = 1'b0;
assign scop_cfg_interrupt = 1'b0;
`endif
`endif
 
wire [31:0] scop_ram_data;
wire scop_ram_ack, scop_ram_stall, scop_ram_interrupt;
wire [31:0] scop_two_data;
wire scop_two_ack, scop_two_stall, scop_two_interrupt;
`ifdef SDRAM_SCOPE
wire sdram_trigger;
assign sdram_trigger = sdram_debug[18]; // sdram_sel;
668,14 → 726,27
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
wb_data,
scop_ram_ack, scop_ram_stall, scop_ram_data,
scop_ram_interrupt);
scop_two_ack, scop_two_stall, scop_two_data,
scop_two_interrupt);
`else
assign scop_ram_data = 32'h00;
assign scop_ram_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
assign scop_ram_stall = 1'b0;
assign scop_ram_interrupt = 1'b0;
`ifdef UART_SCOPE
wire uart_trigger;
assign uart_trigger = uart_debug[31];
// wbscopc #(5'ha) uartscope(i_clk,1'b1, uart_trigger, uart_debug[30:0],
wbscope #(5'ha) uartscope(i_clk, 1'b1, uart_trigger, uart_debug[31:0],
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
wb_data,
scop_two_ack, scop_two_stall, scop_two_data,
scop_two_interrupt);
`else
assign scop_two_data = 32'h00;
assign scop_two_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
assign scop_two_stall = 1'b0;
assign scop_two_interrupt = 1'b0;
`endif
`endif
 
wire [31:0] scop_zip_data;
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
682,7 → 753,7
`ifdef ZIP_SCOPE
wire zip_trigger;
assign zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
wbscope #(5'ha) zipscope(i_clk, 1'b1, zip_trigger,
wbscope #(5'h9) zipscope(i_clk, 1'b1, zip_trigger,
zip_debug,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
698,24 → 769,17
 
 
assign scop_interrupt = scop_flash_interrupt || scop_cfg_interrupt
|| scop_ram_interrupt || scop_zip_interrupt;
assign scop_ack = scop_cfg_ack | scop_flash_ack | scop_ram_ack | scop_zip_ack;
|| scop_two_interrupt || scop_zip_interrupt;
assign scop_ack = scop_cfg_ack | scop_flash_ack | scop_two_ack | scop_zip_ack;
assign scop_stall = ((~wb_addr[2])?
((wb_addr[1])?scop_flash_stall:scop_cfg_stall)
: ((wb_addr[1])?scop_ram_stall:scop_zip_stall));
: ((wb_addr[1])?scop_two_stall:scop_zip_stall));
assign scop_data = ((scop_cfg_ack)?scop_cfg_data
: ((scop_flash_ack) ? scop_flash_data
: ((scop_ram_ack) ? scop_ram_data
: ((scop_two_ack) ? scop_two_data
: scop_zip_data)));
 
 
reg r_sdcard_ack;
initial r_sdcard_ack = 1'b0;
always @(posedge i_clk)
r_sdcard_ack <= (wb_cyc)&&(wb_stb)&&(sdcard_sel);
assign sdcard_stall = 1'b0;
assign sdcard_ack = r_sdcard_ack;
assign sdcard_data = 32'h0000;
endmodule
 
// 0x8684 interrupts ...???

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