OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk/sw
    from Rev 111 to Rev 113
    ↔ Reverse comparison
  •

Rev 111 → Rev 113

/zipdbg.cpp
101,10 → 101,10
DEVBUS *m_fpga;
int m_cursor;
ZIPSTATE m_state;
bool m_user_break, m_show_users_timers;
bool m_user_break, m_show_users_timers, m_show_cc;
public:
ZIPPY(DEVBUS *fpga) : m_fpga(fpga), m_cursor(0), m_user_break(false),
m_show_users_timers(false) {}
m_show_users_timers(false), m_show_cc(false) {}
 
void read_raw_state(void) {
m_state.m_valid = false;
209,6 → 209,10
m_show_users_timers = v;
}
 
void toggle_cc(void) {
m_show_cc = !m_show_cc;
}
 
void showval(int y, int x, const char *lbl, unsigned int v, bool c) {
if (c)
mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
409,20 → 413,26
dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
 
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
(m_cursor == 26)?">":" ",
(cc&0x1000)?"FE":"", // Floating point exception
(cc&0x0800)?"DV":"", // Division by zero
(cc&0x0400)?"BE":"", // Bus Error
(cc&0x0200)?"TP":"", // Trap
(cc&0x0100)?"IL":"", // Illegal instruction
(cc&0x0080)?"BK":"", // Break
((gie==0)&&(cc&0x0010))?"HLT":""); // Halted
mvprintw(ln,54,"%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
if (m_show_cc) {
mvprintw(ln,40, " sCC :%16s", "");
dispreg(ln, 40, "sCC ", m_state.m_sR[14], (m_cursor==26));
} else {
mvprintw(ln,40, " sCC :%16s", "");
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
(m_cursor == 26)?">":" ",
(cc&0x1000)?"FE":"", // Floating point exception
(cc&0x0800)?"DV":"", // Division by zero
(cc&0x0400)?"BE":"", // Bus Error
(cc&0x0200)?"TP":"", // Trap
(cc&0x0100)?"IL":"", // Illegal instruction
(cc&0x0080)?"BK":"", // Break
((gie==0)&&(cc&0x0010))?"HLT":""); // Halted
mvprintw(ln,54,"%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
dispreg(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
ln++;
 
449,20 → 459,26
dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
cc = m_state.m_uR[14];
mvprintw(ln,40, "%suCC :%s%s%s%s%s%s%s",
(m_cursor == 42)?">":" ",
(cc&0x1000)?"FE":"", // Floating point Exception
(cc&0x0800)?"DV":"", // Division by zero
(cc&0x0400)?"BE":"", // Bus Error
(cc&0x0200)?"TP":"", // Trap
(cc&0x0100)?"IL":"", // Illegal instruction
(cc&0x0040)?"ST":"", // Single-step
((gie)&&(cc&0x0010))?"SL":""); // Sleep
mvprintw(ln,54,"%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
if (m_show_cc) {
mvprintw(ln,40, " uCC :%16s", "");
dispreg(ln, 40, "uCC ", m_state.m_uR[14], (m_cursor==42));
} else {
mvprintw(ln,40, " uCC :%16s", "");
mvprintw(ln,40, "%suCC :%s%s%s%s%s%s%s",
(m_cursor == 42)?">":" ",
(cc&0x1000)?"FE":"", // Floating point Exception
(cc&0x0800)?"DV":"", // Division by zero
(cc&0x0400)?"BE":"", // Bus Error
(cc&0x0200)?"TP":"", // Trap
(cc&0x0100)?"IL":"", // Illegal instruction
(cc&0x0040)?"ST":"", // Single-step
((gie)&&(cc&0x0010))?"SL":""); // Sleep
mvprintw(ln,54,"%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
 
attroff(A_BOLD);
637,6 → 653,9
while((!done)&&(!gbl_err)) {
chv = getch();
switch(chv) {
case 'c': case 'C':
zip->toggle_cc();
break;
case 'g': case 'G':
m_fpga->writeio(R_ZIPCTRL, CPU_GO);
// We just released the CPU, so we're now done.
/cpuscope.cpp
49,6 → 49,7
#include "port.h"
#include "llcomms.h"
#include "regdefs.h"
#include "scopecls.h"
 
#define WBSCOPE R_CPUSCOPE
#define WBSCOPEDATA R_CPUSCOPED
78,9 → 79,68
return r;
}
 
void decode(DEVBUS::BUSW val) {
}
const char *opcodestr[] = {
"SUB","AND","ADD","OR","XOR","LSR","LSL","ASR",
"MPY","LDILO","MPYUHI","MPYSHI","BREV","POPC","ROL","MOV",
"CMP","TEST","LOD","STO","DIVU","DIVS","LDI","LDI",
"NOOP","BREAK","LOCK","(rsrvd)","(rsrvd)","(rsrvd)","(rsrvd)","(rsrvd)"
};
const char *regstr[] = {
"R0","R1","R2","R3","R4","R5","R6","R7","R8","R9","RA","RB","RC",
"SP","CC","PC"
};
 
class CPUSCOPE : public SCOPE {
public:
CPUSCOPE(FPGA *fpga, unsigned addr, bool vecread)
: SCOPE(fpga, addr, false, false) {};
~CPUSCOPE(void) {}
virtual void decode(DEVBUS::BUSW val) const {
int i_wb_err, gie, alu_illegal, newpc, mem_busy, stb, we,
maddr, ins, pfval, alu_pc;
int pfcyc, pfstb, pfaddr;
 
i_wb_err = (val>>31)&1;
gie = (val>>30)&1;
alu_illegal = (val>>29)&1;
newpc = (val>>28)&1;
mem_busy = (val>>27)&1;
stb = (val>>26)&1;
we = (val>>25)&1;
maddr = (val>>16)&0x01ff;
ins = (val>>16)&0x07ff;
pfval = (val>>15)&1;
pfcyc = (val>>14)&1;
pfstb = (val>>13)&1;
pfaddr = (val & 0x1fff);
alu_pc = (val & 0x7fff);
 
printf("%s%s%s%s%s ",
(i_wb_err)?"E ":" ",
(gie)?"GIE":" ",
(alu_illegal)?"ILL":" ",
(newpc)?"NPC":" ",
(mem_busy)?"MBSY":" ");
if (mem_busy)
printf("M:%s%s@..%4x", (stb)?"STB":" ",(we)?"W":"R",
maddr);
else {
int inreg = (ins>>6)&0x0f;
int opcode = ((ins>>1)&0x1f);
const char *incode = opcodestr[opcode];
printf("I:%03x %5s,%s", (ins<<1), incode, regstr[inreg]);
}
 
if (pfval)
printf(" V: %04x%4s", alu_pc, "");
else
printf(" %s%s@%04x",
(pfcyc)?"CYC":" ",
(pfstb)?"STB":" ",
pfaddr);
}
};
 
int main(int argc, char **argv) {
int skp=0, port = FPGAPORT;
bool use_usb = true;
108,66 → 168,12
signal(SIGSTOP, closeup);
signal(SIGHUP, closeup);
 
unsigned v, lgln, scoplen;
v = m_fpga->readio(WBSCOPE);
if (0x60000000 != (v & 0x60000000)) {
CPUSCOPE *scope = new CPUSCOPE(m_fpga, WBSCOPE, false);
if (!scope->ready()) {
printf("Scope is not yet ready:\n");
printf("\tRESET:\t\t%s\n", (v&0x80000000)?"Ongoing":"Complete");
printf("\tSTOPPED:\t%s\n", (v&0x40000000)?"Yes":"No");
printf("\tTRIGGERED:\t%s\n", (v&0x20000000)?"Yes":"No");
printf("\tPRIMED:\t\t%s\n", (v&0x10000000)?"Yes":"No");
printf("\tMANUAL:\t\t%s\n", (v&0x08000000)?"Yes":"No");
printf("\tDISABLED:\t%s\n", (v&0x04000000)?"Yes":"No");
printf("\tZERO:\t\t%s\n", (v&0x02000000)?"Yes":"No");
exit(0);
} else printf("SCOPD = %08x\n", v);
 
lgln = (v>>20) & 0x1f;
scoplen = (1<<lgln);
 
DEVBUS::BUSW *buf;
buf = new DEVBUS::BUSW[scoplen];
 
bool compressed = false, vector_read = true;
DEVBUS::BUSW addrv = 0;
 
if (vector_read) {
m_fpga->readz(WBSCOPEDATA, scoplen, buf);
} else {
for(unsigned int i=0; i<scoplen; i++)
buf[i] = m_fpga->readio(WBSCOPEDATA);
}
 
if(compressed) {
for(int i=0; i<(int)scoplen; i++) {
if ((buf[i]>>31)&1) {
addrv += (buf[i]&0x7fffffff);
printf(" ** \n");
continue;
}
printf("%10d %08x: ", addrv++, buf[i]);
decode(buf[i]);
printf("\n");
}
} else {
for(int i=0; i<(int)scoplen; i++) {
if ((i>0)&&(buf[i] == buf[i-1])&&(i<(int)(scoplen-1))) {
if ((i>2)&&(buf[i] != buf[i-2]))
printf(" **** ****\n");
continue;
} printf("%9d %08x: ", i, buf[i]);
decode(buf[i]);
printf("\n");
}
}
 
if (m_fpga->poll()) {
printf("FPGA was interrupted\n");
m_fpga->clear();
m_fpga->writeio(R_ICONTROL, SCOPEN);
}
 
delete[] buf;
scope->decode_control();
} else
scope->read();
delete m_fpga;
}
 
/ttybus.cpp
69,17 → 69,20
const unsigned TTYBUS::MAXWRLEN = 32;
 
// #define DBGPRINTF printf
#define DBGPRINTF filedump
// #define DBGPRINTF filedump
#ifndef DBGPRINTF
#define DBGPRINTF null
#endif
 
void null(...) {}
 
#include <stdarg.h> // replaces the (defunct) varargs.h include file
void filedump(const char *fmt, ...) {
static FILE *dbgfp = NULL;
va_list args;
 
assert(0);
 
if (!dbgfp)
dbgfp = fopen("debug.txt", "w");
va_start(args, fmt);
/Makefile
55,8 → 55,10
$(CXX) $(CFLAGS) -c $< -o $@
$(OBJDIR)/zipdbg.o: zipdbg.cpp
$(CXX) $(CFLAGS) -I$(ZIPD) -c $< -o $@
$(OBJDIR)/cpuscope.o: cpuscope.cpp
$(OBJDIR)/cpuscope.o: cpuscope.cpp scopecls.h
$(CXX) $(CFLAGS) -I$(ZIPD) -c $< -o $@
$(OBJDIR)/scopecls.o: scopecls.cpp scopecls.h
$(CXX) $(CFLAGS) -I$(ZIPD) -c $< -o $@
 
.PHONY: clean
clean:
96,7 → 98,7
# ZIPOBJS := $(addprefix $(ZIPD)/$(OBJDIR)/,$(ZIPOBJS_RAW))
zipdbg: $(OBJDIR)/zipdbg.o $(BUSOBJS) $(ZIPSRCS) $(OBJDIR)/twoc.o
$(CXX) $(CFLAGS) $^ $(LIBS) -lncurses -o $@
cpuscope: $(OBJDIR)/cpuscope.o $(BUSOBJS) $(ZIPOBJS)
cpuscope: $(OBJDIR)/cpuscope.o $(OBJDIR)/scopecls.o $(BUSOBJS)
$(CXX) $(CFLAGS) $^ $(LIBS) -o $@
 
nothing:

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.