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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk
    from Rev 16 to Rev 17
    ↔ Reverse comparison
  •

Rev 16 → Rev 17

/sw/zipstate.cpp
0,0 → 1,150
////////////////////////////////////////////////////////////////////////////////
//
// Filename: zipstate.v
//
// Project: XuLA2 board
//
// Purpose: To get a quick (understandable) peek at what the ZipCPU
// is up to without stopping the CPU. This is basically
// identical to a "wbregs cpu" command, save that the bit fields of the
// result are broken out into something more human readable.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <strings.h>
#include <ctype.h>
#include <string.h>
#include <signal.h>
#include <assert.h>
 
#include "llcomms.h"
#include "usbi.h"
#include "port.h"
#include "regdefs.h"
 
FPGA *m_fpga;
void closeup(int v) {
m_fpga->kill();
exit(0);
}
 
unsigned int cmd_read(FPGA *fpga, int r) {
const unsigned int MAXERR = 1000;
unsigned int errcount = 0;
unsigned int s;
 
fpga->writeio(R_ZIPCTRL, CPU_HALT|(r&0x03f));
while((((s = fpga->readio(R_ZIPCTRL))&CPU_STALL)== 0)&&(errcount<MAXERR))
errcount++;
if (errcount >= MAXERR) {
printf("ERR: errcount(%d) >= MAXERR on cmd_read(a=%02x)\n",
errcount, r);
printf("ZIPCTRL = 0x%08x", s);
if ((s & 0x0200)==0) printf(" STALL");
if (s & 0x0400) printf(" HALTED");
if ((s & 0x03000)==0x01000)
printf(" SW-HALT");
else {
if (s & 0x01000) printf(" SLEEPING");
if (s & 0x02000) printf(" GIE(UsrMode)");
} printf("\n");
exit(EXIT_FAILURE);
} return fpga->readio(R_ZIPDATA);
}
 
void usage(void) {
printf("USAGE: zipstate\n");
}
 
int main(int argc, char **argv) {
int skp=0, port = FPGAPORT;
bool use_usb = true, long_state = false;
unsigned int v;
 
skp=1;
for(int argn=0; argn<argc-skp; argn++) {
if (argv[argn+skp][0] == '-') {
if (argv[argn+skp][1] == 'u')
use_usb = true;
else if (argv[argn+skp][1] == 'l')
long_state = true;
else if (argv[argn+skp][1] == 'p') {
use_usb = false;
if (isdigit(argv[argn+skp][2]))
port = atoi(&argv[argn+skp][2]);
}
skp++; argn--;
} else
argv[argn] = argv[argn+skp];
} argc -= skp;
 
if (use_usb)
m_fpga = new FPGA(new USBI());
else
m_fpga = new FPGA(new NETCOMMS(FPGAHOST, port));
 
if (!long_state) {
v = m_fpga->readio(R_ZIPCTRL);
 
printf("0x%08x: ", v);
if (v & 0x0080) printf("PINT ");
// if (v & 0x0100) printf("STEP "); // self resetting
if((v & 0x00200)==0) printf("STALL ");
if (v & 0x00400) printf("HALTED ");
if((v & 0x03000)==0x01000) {
printf("SW-HALT");
} else {
if (v & 0x01000) printf("SLEEPING ");
if (v & 0x02000) printf("GIE(UsrMode) ");
}
// if (v & 0x0800) printf("CLR-CACHE ");
printf("\n");
} else {
printf("Reading the long-state ...\n");
for(int i=0; i<14; i++) {
printf("sR%-2d: 0x%08x ", i, cmd_read(m_fpga, i));
if ((i&3)==3)
printf("\n");
} printf("sCC : 0x%08x ", cmd_read(m_fpga, 14));
printf("sPC : 0x%08x ", cmd_read(m_fpga, 15));
printf("\n\n");
 
for(int i=0; i<14; i++) {
printf("uR%-2d: 0x%08x ", i, cmd_read(m_fpga, i+16));
if ((i&3)==3)
printf("\n");
} printf("uCC : 0x%08x ", cmd_read(m_fpga, 14+16));
printf("uPC : 0x%08x ", cmd_read(m_fpga, 15+16));
printf("\n\n");
}
 
delete m_fpga;
}
 
/sw/wbsettime.cpp
46,11 → 46,12
#include <assert.h>
#include <time.h>
 
#include "llcomms.h"
#include "usbi.h"
#include "port.h"
#include "llcomms.h"
#include "regdefs.h"
 
DEVBUS *m_fpga;
FPGA *m_fpga;
void closeup(int v) {
m_fpga->kill();
exit(0);
58,9 → 59,29
 
int main(int argc, char **argv) {
bool set_time = true;
int skp=0, port = FPGAPORT;
bool use_usb = true;
 
FPGAOPEN(m_fpga);
skp=1;
for(int argn=0; argn<argc-skp; argn++) {
if (argv[argn+skp][0] == '-') {
if (argv[argn+skp][1] == 'u')
use_usb = true;
else if (argv[argn+skp][1] == 'p') {
use_usb = false;
if (isdigit(argv[argn+skp][2]))
port = atoi(&argv[argn+skp][2]);
}
skp++; argn--;
} else
argv[argn] = argv[argn+skp];
} argc -= skp;
 
if (use_usb)
m_fpga = new FPGA(new USBI());
else
m_fpga = new FPGA(new NETCOMMS(FPGAHOST, port));
 
signal(SIGSTOP, closeup);
signal(SIGHUP, closeup);
 
/sw/regdefs.cpp
81,11 → 81,6
{ R_CKALARM, "CKALARM" },
{ R_CKALARM, "ALARM" },
{ R_CKSPEED, "CKSPEED" },
{ R_TIMEHACK, "TIMEHACK" },
{ R_TIMEHACK, "HACK" },
{ R_HACKHI, "HACKHI" },
{ R_HACKLO, "HACKLO" },
{ R_TIMEHACK, "HACK" },
// Scopes are defined and come and go. Be aware, therefore, not all
// of these scopes may be defined at the same time.
{ R_QSCOPE, "SCOPE" },
95,8 → 90,6
{ R_CFGSCOPE, "CFGSCOPE" },
{ R_CFGSCOPE, "CFGSCOP" },
{ R_CFGSCOPED, "CFGSCOPD" },
{ R_CPUSCOPE, "CPUSCOPE" },
{ R_CPUSCOPE, "CPUSCOP" },
{ R_CPUSCOPED, "CPUSCOPD" },
{ R_RAMSCOPE, "MEMSCOPE" },
{ R_RAMSCOPE, "MEMSCOP" },
104,6 → 97,8
{ R_RAMSCOPE, "RAMSCOPE" },
{ R_RAMSCOPE, "RAMSCOP" },
{ R_RAMSCOPED, "RAMSCOPD" },
{ R_CPUSCOPE, "CPUSCOPE" },
{ R_CPUSCOPE, "CPUSCOP" },
//
// For working with the ICAPE interface ... if I can ever get a
// testing environment suitable to prove that it works.
/sw/cpuscope.cpp
62,7 → 62,6
signal(SIGHUP, closeup);
 
unsigned v, lgln, scoplen;
printf("Attempting to read address %08x\n", WBSCOPE);
v = m_fpga->readio(WBSCOPE);
if (0x60000000 != (v & 0x60000000)) {
printf("Scope is not yet ready:\n");
83,10 → 82,7
buf = new DEVBUS::BUSW[scoplen];
 
if (false) {
printf("Attempting vector read\n");
m_fpga->readz(WBSCOPEDATA, scoplen, buf);
 
printf("Vector read complete\n");
} else {
for(unsigned int i=0; i<scoplen; i++)
buf[i] = m_fpga->readio(WBSCOPEDATA);
/sw/regdefs.h
56,9 → 56,6
#define R_STOPWATCH 0x00000112
#define R_CKALARM 0x00000113
#define R_CKSPEED 0x00000114
#define R_TIMEHACK 0x00000115
#define R_HACKHI 0x00000116
#define R_HACKLO 0x00000117
 
// GPS registers
// 0x00000114
/sw/cfgscope.cpp
1,18 → 1,38
////////////////////////////////////////////////////////////////////////////////
//
// Filename: cfgscope.cpp
//
// Filename: cfgscope.cpp
// Project: XuLA2 board
//
// Project: FPGA library development (Basys-3 development board)
//
// Purpose: To read out, and decompose, the results of the wishbone scope
// as applied to the ICAPE2 interaction.
// as applied to the ICAPE interaction on a SPARTAN6.
//
// Creator: Dan Gisselquist
// Gisselquist Tecnology, LLC
//
// Copyright: 2015
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
22,8 → 42,9
#include <signal.h>
#include <assert.h>
 
#include "llcomms.h"
#include "usbi.h"
#include "port.h"
#include "llcomms.h"
#include "regdefs.h"
 
#define WBSCOPE R_CFGSCOPE
53,13 → 74,33
}
 
int main(int argc, char **argv) {
FPGAOPEN(m_fpga);
int skp=0, port = FPGAPORT;
bool use_usb = true;
 
skp=1;
for(int argn=0; argn<argc-skp; argn++) {
if (argv[argn+skp][0] == '-') {
if (argv[argn+skp][1] == 'u')
use_usb = true;
else if (argv[argn+skp][1] == 'p') {
use_usb = false;
if (isdigit(argv[argn+skp][2]))
port = atoi(&argv[argn+skp][2]);
}
skp++; argn--;
} else
argv[argn] = argv[argn+skp];
} argc -= skp;
 
if (use_usb)
m_fpga = new FPGA(new USBI());
else
m_fpga = new FPGA(new NETCOMMS(FPGAHOST, port));
 
signal(SIGSTOP, closeup);
signal(SIGHUP, closeup);
 
unsigned v, lgln, scoplen;
printf("Attempting to read address %08x\n", WBSCOPE);
v = m_fpga->readio(WBSCOPE);
if (0x60000000 != (v & 0x60000000)) {
printf("Scope is not yet ready:\n");
80,10 → 121,7
buf = new DEVBUS::BUSW[scoplen];
 
if (false) {
printf("Attempting vector read\n");
m_fpga->readz(WBSCOPEDATA, scoplen, buf);
 
printf("Vector read complete\n");
} else {
for(unsigned int i=0; i<scoplen; i++)
buf[i] = m_fpga->readio(WBSCOPEDATA);
117,7 → 155,6
if (m_fpga->poll()) {
printf("FPGA was interrupted\n");
m_fpga->clear();
m_fpga->writeio(R_ICONTROL, SCOPEN);
}
delete m_fpga;
}
/sw/Makefile
33,7 → 33,7
##
.PHONY: all
PROGRAMS := $(OBJDIR) usbtst wbregs netusb wbsettime dumpflash \
dumpsdram ziprun ramscope zipstate zipdbg
dumpsdram ziprun ramscope zipstate zipdbg cfgscope
all: $(PROGRAMS)
CXX := g++
LIBUSBINC := -I/usr/include/libusb-1.0/

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