OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/sw/ziprun.cpp
272,7 → 272,7
total_octets += phdr.p_memsz;
}
 
char *d = (char *)malloc(total_octets);
char *d = (char *)malloc(total_octets + sizeof(SECTION)+sizeof(SECTION *));
memset(d, 0, total_octets);
 
SECTION **r = sections = (SECTION **)d;
332,6 → 332,7
r[i]->m_data[j]);
}
 
r[i] = (SECTION *)(&d[current_offset]);
r[current_section]->m_start = 0;
r[current_section]->m_len = 0;
 
423,6 → 424,7
// zip-readelf will help with both of these ...
elfread(codef, entry, secpp);
 
/*
fprintf(stderr, "Secpp = %08lx\n", (unsigned long)secpp);
for(int i=0; secpp[i]->m_len; i++) {
secp = secpp[i];
429,7 → 431,7
fprintf(stderr, "Sec[%2d] - %08x - %08x\n",
i, secp->m_start,
secp->m_start+secp->m_len);
}
} */
#else
char tmpbuf[TMP_MAX], cmdbuf[256];
int unused_fd;
483,6 → 485,7
if ((secp->m_start >= RAMBASE)
&&(secp->m_start+secp->m_len
<= RAMBASE+MEMWORDS)) {
printf("Clearing Block ram\n");
FPGA::BUSW zbuf[128], a;
memset(zbuf, 0, 128*sizeof(FPGA::BUSW));
for(a=RAMBASE; a<RAMBASE+MEMWORDS; a+=128)
489,7 → 492,7
m_fpga->writei(a, 128, zbuf);
break;
}
}
} m_fpga->readio(R_VERSION); // Check for buserrors
 
if (clear_memory) for(int i=0; secpp[i]->m_len; i++) {
secp = secpp[i];
497,13 → 500,14
&&(secp->m_start+secp->m_len
<= SDRAMBASE+SDRAMWORDS)) {
FPGA::BUSW zbuf[128], a;
printf("Clearing SDRam\n");
memset(zbuf, 0, 128*sizeof(FPGA::BUSW));
for(a=SDRAMBASE; a<SDRAMBASE+SDRAMWORDS; a+=128)
m_fpga->writei(a, 128, zbuf);
break;
}
}
} m_fpga->readio(R_VERSION); // Check for buserrors
 
for(int i=0; secpp[i]->m_len; i++) {
bool inflash=false;
 
519,11 → 523,12
} else
m_fpga->writei(secp->m_start, secp->m_len, secp->m_data);
}
m_fpga->readio(R_ZIPCTRL);
m_fpga->readio(R_ZIPCTRL); // Check for bus errors
 
// Clear any buffers
printf("Clearing the cache\n");
m_fpga->writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT|CPU_CLRCACHE);
m_fpga->readio(R_VERSION);
 
if (clear_registers) {
printf("Clearing all registers to zero\n");
532,7 → 537,7
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|i);
m_fpga->writeio(R_ZIPDATA, 0);
}
}
} m_fpga->readio(R_VERSION); // Check for bus errors
 
// Start in interrupt mode
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|CPU_sCC);
541,6 → 546,9
// Set our entry point into our code
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|CPU_sPC);
m_fpga->writeio(R_ZIPDATA, entry);
 
printf("The CPU should be fully loaded, you may now start\n");
printf("it. To start the CPU, type wbregs cpu 0\n");
} catch(BUSERR a) {
fprintf(stderr, "XULA-BUS error\n");
m_fpga->writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT|CPU_CLRCACHE);

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