OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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    /xulalx25soc/trunk
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Rev 5 → Rev 6

/rtl/busmaster.v
115,7 → 115,7
wire w_interrupt;
// Oh, and the debug control for the ZIP CPU
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[31: 1]== 31'h083));
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]);
wire [31:0] zip_dbg_data;
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
/doc/wishbone.html
0,0 → 1,89
<HTML><HEAD><TITLE>XuLA2 Wishbone Bus</TITLE></HEAD>
<BODY>
<h1 align=center>XuLA2 Wishbone Address Space</H1>
<TABLE align=center>
<TR><TH>Wishbone Address</TH><TH align=center>Words</TH><TH align=left>Usage</TH></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0000_xxxx_xxxx</TT></TD><TH align=right>256</TH><TD>Undefined Memory (Bus Error)</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_000x</TT></TD><TH align=right>1</TH><TD>(Reserved)</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0010</TT></TD><TH align=right>1</TH><TD>Version</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0011</TT></TD><TH align=right>1</TH><TD>JTAG Accessible Interrupt Controller</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0100</TT></TD><TH align=right>1</TH><TD>Bus Error (Includes errors induced from JTAG-wishbone controller)</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0101</TT></TD><TH align=right>1</TH><TD>RTC Date</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0110</TT></TD><TH align=right>1</TH><TD>GPIO control</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0111</TT></TD><TH align=right>1</TH><TD>UART Control word</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_100x</TT></TD><TH align=right>2</TH><TD>PWM control</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1010</TT></TD><TH align=right>1</TH><TD>Receive UART RX value</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1011</TT></TD><TH align=right>1</TH><TD>Transmit UART port</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_11xx</TT></TD><TH align=right>4</TH><TD>Flash Control Words</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_0xxx</TT></TD><TH align=right>8</TH><TD>RTC Clock</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_1yyx</TT></TD><TH align=right>2</TH><TD>Scope #Y (0..3)</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>?</TH><TD>SD Card Control</TD></TR>
<TR><TD align=right><TT>0_0000_0000_0000_0001_01xx_xxxx</TT></TD><TH align=right>32</TH><TD>(ICAPE Access -- not yet proven)</TD></TR>
<TR><TD align=right><TT>0_0000_0000_001x_xxxx_xxxx_xxxx</TT></TD><TH align=right>8k</TH><TD>On Chip RAM</TD></TR>
<TR><TD align=right><TT>0_0000_01xx_xxxx_xxxx_xxxx_xxxx</TT></TD><TH align=right>256k</TH><TD>1 MB SPI Flash (256kW)</TD></TR>
<TR><TD align=right><TT>0_1rrr_rrrr_rrrr_rrbb_cccc_cccc</TT></TD><TH align=right>8M</TH><TD>32 MB SDRAM (8MW)</TD></TR>
<TR><TD align=right><TT>1_yyyy_yyyy_yyyy_yyyy_yyyy_yyyx</TT></TD><TH align=right>2</TH><TD>External Zip CPU control (y bits are don't cares, not accessible from ZipCPU)</TD></TR>
<!-- -->
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_xxxx</TT></TD><TH align=right>20</TH><TD>Zip System registers</TD></TR>
<!-- -->
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0000</TT></TD><TH align=right>1</TH><TD>Zip Programmable Interrupt Controller</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0001</TT></TD><TH align=right>1</TH><TD>Watchdog Timer</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0010</TT></TD><TH align=right>1</TH><TD>Address of last bus error, as seen by the Zip CPU</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0011</TT></TD><TH align=right>1</TH><TD>Secondary Interrupt Controller</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0100</TT></TD><TH align=right>1</TH><TD>Timer A</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0101</TT></TD><TH align=right>1</TH><TD>Timer B</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0110</TT></TD><TH align=right>1</TH><TD>Timer C</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0111</TT></TD><TH align=right>1</TH><TD>Jiffies</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1000</TT></TD><TH align=right>1</TH><TD>Master Task Clock Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1001</TT></TD><TH align=right>1</TH><TD>Master Stall Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1010</TT></TD><TH align=right>1</TH><TD>Master Pre-Fetch Stall Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1011</TT></TD><TH align=right>1</TH><TD>Master Instruction Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1100</TT></TD><TH align=right>1</TH><TD>User Task Clock Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1101</TT></TD><TH align=right>1</TH><TD>User Stall Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1110</TT></TD><TH align=right>1</TH><TD>User Pre-Fetch Stall Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1111</TT></TD><TH align=right>1</TH><TD>User Instruction Counter</TD></TR>
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0001_00xx</TT></TD><TH align=right>1</TH><TD>DMA Controller</TD></TR>
</TABLE>
<h1 align=center>Primary (ZipSystem) Interrupt Controller Assignments</H1>
<TABLE align=center>
<TR><TD><TH align=right>0</TH><TD>DMA controller</TD></TR>
<TR><TD><TH align=right>1</TH><TD>Jiffies</TD></TR>
<TR><TD><TH align=right>2</TH><TD>Timer C</TD></TR>
<TR><TD><TH align=right>3</TH><TD>Timer B</TD></TR>
<TR><TD><TH align=right>4</TH><TD>Timer A</TD></TR>
<TR><TD><TH align=right>5</TH><TD>Secondary Interrupt Controller</TD></TR>
<TR><TD><TH align=right>6</TH><TD>JTAG Accessible Interrupt Controller</TD></TR>
<TR><TD><TH align=right>7</TH><TD>RTC Clock</TD></TR>
<TR><TD><TH align=right>8</TH><TD>SPI Flash</TD></TR>
<TR><TD><TH align=right>9</TH><TD>Scope</TD></TR>
<TR><TD><TH align=right>10</TH><TD>GPIO</TD></TR>
<TR><TD><TH align=right>11</TH><TD>PWM</TD></TR>
<TR><TD><TH align=right>12</TH><TD>RX UART data available (with FIFO, becomes non-empty RX FIFO not empty)</TD></TR>
<TR><TD><TH align=right>13</TH><TD>TX UART idle (with FIFO, becomes TX FIFO empty)</TD></TR>
<TR><TD><TH align=right>14</TH><TD>(Unused/reserved)</TD></TR>
</TABLE>
<h1 align=center>Secondary (ZipSystem) Interrupt Controller Assignments</H1>
<TABLE align=center>
<TR><TD><TH align=right>0</TH><TD>User Instruction Counter</TD></TR>
<TR><TD><TH align=right>1</TH><TD>User Prefetch stall counter</TD></TR>
<TR><TD><TH align=right>2</TH><TD>User stall counter</TD></TR>
<TR><TD><TH align=right>3</TH><TD>User task counter</TD></TR>
<TR><TD><TH align=right>4</TH><TD>Master instruction counter rollover</TD></TR>
<TR><TD><TH align=right>5</TH><TD>Master prefetch stall counter rollover</TD></TR>
<TR><TD><TH align=right>6</TH><TD>Master stall counter rollover</TD></TR>
<TR><TD><TH align=right>7</TH><TD>Master task counter rollover</TD></TR>
<TR><TD><TH align=right>8-14</TH><TD>(Unused / reserved)</TD></TR>
</TABLE>
<h1 align=center>JTAG Accessible Interrupt Controller Assignments</H1>
<TABLE align=center>
<TR><TD><TH align=right>0</TH><TD>Zip CPU Halted</TD></TR>
<TR><TD><TH align=right>1</TH><TD>RTC Clock</TD></TR>
<TR><TD><TH align=right>2</TH><TD>SPI Flash</TD></TR>
<TR><TD><TH align=right>3</TH><TD>Scope</TD></TR>
<TR><TD><TH align=right>4</TH><TD>GPIO</TD></TR>
<TR><TD><TH align=right>5</TH><TD>PWM</TD></TR>
<TR><TD><TH align=right>6</TH><TD>RX UART</TD></TR>
<TR><TD><TH align=right>7</TH><TD>TX UART</TD></TR>
<TR><TD><TH align=right>8-14</TH><TD>(Unused / reserved)</TD></TR>
</TABLE>
</BODY></HTML>
/xula.ucf
0,0 → 1,145
#**********************************************************************
# Copyright (c) 1997-2014 by XESS Corp <http://www.xess.com>.
# All rights reserved.
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 3.0 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library. If not, see
# <http://www.gnu.org/licenses/>.
#**********************************************************************
 
NET i_clk_12mhz LOC = A9; # 12 MHz clock input.
 
##############################
# SDRAM
##############################
NET o_ram_cke LOC = J12;
NET o_ram_clk LOC = K11;
NET i_ram_feedback_clk LOC = K12;
NET o_ram_cs_n LOC = H4;
NET o_ram_ras_n LOC = L4;
NET o_ram_cas_n LOC = L3;
NET o_ram_we_n LOC = M3;
NET o_ram_ldqm LOC = M4;
NET o_ram_udqm LOC = L13;
NET o_ram_bs<0> LOC = H3;
NET o_ram_bs<1> LOC = G3;
NET o_ram_addr<0> LOC = E4;
NET o_ram_addr<1> LOC = E3;
NET o_ram_addr<2> LOC = D3;
NET o_ram_addr<3> LOC = C3;
NET o_ram_addr<4> LOC = B12;
NET o_ram_addr<5> LOC = A12;
NET o_ram_addr<6> LOC = D12;
NET o_ram_addr<7> LOC = E12;
NET o_ram_addr<8> LOC = G16;
NET o_ram_addr<9> LOC = G12;
NET o_ram_addr<10> LOC = F4;
NET o_ram_addr<11> LOC = G11;
NET o_ram_addr<12> LOC = H13;
NET io_ram_data<0> LOC = P6;
NET io_ram_data<1> LOC = T6;
NET io_ram_data<2> LOC = T5;
NET io_ram_data<3> LOC = P5;
NET io_ram_data<4> LOC = R5;
NET io_ram_data<5> LOC = N5;
NET io_ram_data<6> LOC = P4;
NET io_ram_data<7> LOC = N4;
NET io_ram_data<8> LOC = P12;
NET io_ram_data<9> LOC = R12;
NET io_ram_data<10> LOC = T13;
NET io_ram_data<11> LOC = T14;
NET io_ram_data<12> LOC = R14;
NET io_ram_data<13> LOC = T15;
NET io_ram_data<14> LOC = T12;
NET io_ram_data<15> LOC = P11;
 
##############################
# Flash
##############################
NET o_sd_cs_n LOC = T8;
NET o_sf_cs_n LOC = T3;
NET o_spi_sck LOC = R11;
NET o_spi_mosi LOC = T10;
NET i_spi_miso LOC = P10;
 
##############################
# Prototyping Header
##############################
# NET io_chan_clk LOC = T7; # L32N
NET i_rx_uart LOC = R7; # L32P
NET i_gpio<0> LOC = R15; # L49P
NET i_gpio<1> LOC = R16; # L49N
NET i_gpio<2> LOC = M15; # L46P
NET i_gpio<3> LOC = M16; # L46N
NET i_gpio<4> LOC = K15; # L44P
NET i_gpio<5> LOC = K16; # L44N
NET i_gpio<6> LOC = J16; # L43N
NET i_gpio<7> LOC = J14; # L43P
NET i_gpio<8> LOC = F15; # L35P
NET i_gpio<9> LOC = F16; # L35N
NET i_gpio<10> LOC = C16; # L33N
NET i_gpio<11> LOC = C15; # L33P
NET i_gpio<12> LOC = B16; # L29N
NET i_gpio<13> LOC = B15; # L29P
NET o_pwm LOC = T4; # L63N (No differential pair!)
NET o_tx_uart LOC = R2; # L32P
NET o_gpio<0> LOC = R1; # L32N
NET o_gpio<1> LOC = M2; # L35P
NET o_gpio<2> LOC = M1; # L35N
NET o_gpio<3> LOC = K3; # L42P
NET o_gpio<4> LOC = J4; # L42N
NET o_gpio<5> LOC = H1; # L39N
NET o_gpio<6> LOC = H2; # L39P
NET o_gpio<7> LOC = F1; # L41N
NET o_gpio<8> LOC = F2; # L41P
NET o_gpio<9> LOC = E1; # L46N
NET o_gpio<10> LOC = E2; # L46P
NET o_gpio<11> LOC = C1; # L50P
NET o_gpio<12> LOC = B1; # L50N
NET o_gpio<13> LOC = B2; # L52P
NET o_gpio<14> LOC = A2; # L52N
 
##############################
# I/O Drive
##############################
NET i_clk_12mhz IOSTANDARD = LVTTL;
NET o_ram_clk IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=8;
NET i_ram_feedback_clk IOSTANDARD = LVTTL;
NET o_ram_cke IOSTANDARD = LVTTL;
NET o_ram_cs_n IOSTANDARD = LVTTL;
NET o_ram_addr* IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_bs* IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_ras_n IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_cas_n IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_we_n IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET io_ram_data* IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_udqm IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_ldqm IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_sd_cs_n IOSTANDARD = LVTTL;
NET o_sf_cs_n IOSTANDARD = LVTTL;
NET o_spi_sck IOSTANDARD = LVTTL;
NET o_spi_mosi IOSTANDARD = LVTTL;
NET i_gpio* IOSTANDARD = LVTTL;
NET o_gpio* IOSTANDARD = LVTTL;
NET o_pwm IOSTANDARD = LVTTL;
NET o_tx_uart IOSTANDARD = LVTTL;
NET i_rx_uart IOSTANDARD = LVTTL;
 
##############################
# Clock Nets
##############################
NET "i_clk_12mhz" TNM_NET = "i_clk_12mhz";
NET "i_ram_feedback_clk" TNM_NET = "i_ram_feedback_clk";
TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
# TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 10.0 ns HIGH 50%;
TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 11.3 ns HIGH 50%;
/xilinx/Makefile
0,0 → 1,112
################################################################################
##
## Filename: Makefile
##
## Project: XuLA2 board
##
## Purpose: In case you don't want to fire up ISE, this Makefile attempts
## to coordinate the build process without it. While it works in
## testing, there are some problems to this approach. The first is that
## if you bust timing, you may never know it--nothing will tell you it
## failed. Second, the output file is different from the output file
## produced via ISE. Still ... for a command line make script, it is a
## (good) start.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http:##www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
DIR_SPACES := $(subst /, ,$(CURDIR))
DIR_NAME := $(word $(words $(DIR_SPACES)), $(DIR_SPACES))
PROJECT := xula
BRD := lx25
PART := xc6s$(BRD)-ftg256-2
OBJDIR := obj-xilinx
UCFFILE := ../xula.ucf
ifeq ($(shell uname),Linux)
MKDIR:=mkdir
else
MKDIR:=gmkdir
endif
SRCDIR := ../rtl
CPUDIR := ../rtl/cpu
JTAGBUS := wbufifo.v wbubus.v wbucompactlines.v wbucompress.v \
wbudecompress.v wbudeword.v wbuexec.v wbuidleint.v wbuinput.v \
wbuoutput.v wbureadcw.v wbusixchar.v wbutohex.v
PERIPHERALS: wbgpio.v wbpwmaudio.v rxuart.v txuart.v rtcdate.v rtclight.v
CPUSRC := zipsystem.v \
busdelay.v wbarbiter.v wbdblpriarb.v \
zipcpu.v cpuops.v pfcache.v idecode.v pipemem.v pipefetch.v div.v \
zipcounter.v zipjiffies.v ziptimer.v wbdmac.v wbwatchdog.v
SOURCES := toplevel.v jtagser.v busmaster.v \
ioslave.v memdev.v hexmap.v icontrol.v builddate.v \
wbspiflash.v lldspi.v \
wbsdramng.v wbscope.v wbscopc.v $(JTAGBUS)
 
RTLFILES := $(addprefix $(SRCDIR)/,$(SOURCES)) $(addprefix $(CPUDIR)/,$(CPUSRC))
 
 
all: objdir xula.bit
 
.PHONY: objdir
objdir:
@bash -c "if [ ! -e $(OBJDIR)/ ]; then $(MKDIR) -p $(OBJDIR)/; fi"
 
$(OBJDIR)/$(PROJECT).ngc: $(RTLFILES) $(PROJECT).xst
$(MKDIR) -p xst/projnav.tmp/
xst -intstyle ise -ifn $(PROJECT).xst -ofn $(OBJDIR)/$(PROJECT).syr
mv $(PROJECT).ngc $(OBJDIR)/$(PROJECT).ngc
mv $(PROJECT).ngr $(OBJDIR)/$(PROJECT).ngr
 
$(OBJDIR)/$(PROJECT).ngd: $(OBJDIR)/$(PROJECT).ngc
ngdbuild -intstyle ise -dd _ngo -nt timestamp \
-uc $(UCFFILE) -p $(PART) $(OBJDIR)/$(PROJECT).ngc $(OBJDIR)/$(PROJECT).ngd
 
PRVMAPOPTS := -w -detail -ir off -ignore_keep_hierarchy -pr b -timing \
-ol high -logic_opt on
MAPOPTS := -w -detail -logic_opt on -ol high -xe n -t 1 -xt 0 -r 4 \
-global_opt speed -equivalent_register_removal on -mt 2 -detail \
-ir off -ignore_keep_hierarchy -pr off -lc off -power xe
$(OBJDIR)/$(PROJECT).ncd: $(OBJDIR)/$(PROJECT).ngd
map -intstyle ise -p $(PART) $(MAPOPTS) \
-o $(OBJDIR)/$(PROJECT)_map.ncd $(OBJDIR)/$(PROJECT).ngd $(OBJDIR)/$(PROJECT).pcf
 
$(OBJDIR)/$(PROJECT).ncd: $(OBJDIR)/$(PROJECT)_map.ncd
par -w -intstyle ise -ol high -mt 4 $(OBJDIR)/$(PROJECT)_map.ncd $(OBJDIR)/$(PROJECT).ncd $(OBJDIR)/$(PROJECT).pcf
 
$(PROJECT).bit: $(OBJDIR)/$(PROJECT).ncd
bitgen -f $(PROJECT).ut $(OBJDIR)/$(PROJECT).ncd $(PROJECT).bit
 
timing: $(OBJDIR)/$(PROJECT).ncd $(OBJDIR)/$(PROJECT).pcf
trce -v 3 -s 2 -n 3 -fastpaths -xml $(OBJDIR)/$(PROJECT).twx -o $(OBJDIR)/$(PROJECT).ncd -o $(OBJDIR)/$(PROJECT).twr $(OBJDIR)/$(PROJECT).pcf
 
.PHONY: clean
clean:
@-rm -rf $(OBJDIR)
@-rm -f *.ngc *.ngd *.ncd *.pcf *.lso *.ngr *.bgn *.bld *.cmd_log
@-rm -f *.drc *.gise *.map *.mrp *.ngm *.syr *.xwbt *.xrpt
@-rm -f *.pad *.par *.psr *.ptwx *.unroutes *.xpi *.csv *.xml
@-rm -f *.html *.xrpt *.log *.stx *.tcl *.txt *.twr *.twx
@-rm -rf _ngo _xmsgs xlnx_* ipcore_dir iseconfig templates xst
@echo "All cleaned up"
/Makefile
0,0 → 1,50
.PHONY: all
all: datestamp verilated bit
# Could also depend upon load, if desired, but not necessary
BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
NOTES := `find . -name "*.txt"` `find . -name "*.html"`
SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
`find sw -name "*.sh"` `find sw -name "*.py"` \
`find sw -name "*.pl"` `find sw -name Makefile`
PROJ := xilinx/xula.prj xilinx/xula.xise xilinx/xula.xst \
xilinx/xula.ut xilinx/Makefile
BIN := `find xilinx -name "*.bit"`
CONSTRAINTS := xula.ucf
YYMMDD:=`date +%Y%m%d`
 
datestamp: $(YYMMDD)-build.v
$(YYMMDD)-build.v:
-rm -rf 2*-build.v
perl xilinx/mkdatev.pl > $(YYMMDD)-build.v
cd rtl; ln -fs ../$(YYMMDD)-build.v builddate.v
 
.PHONY: archive
archive:
tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
 
.PHONY: tare
tare:
echo tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
 
.PHONY: verilated
verilated:
cd rtl ; make
 
.PHONY: bit
bit:
cd xilinx ; make xula.bit
 
.PHONY: load
load: bit
xsload -b xula2-lx25 --fpga xilinx/xula.bit
.PHONY: xload
xload:
xsload -b xula2-lx25 --fpga xilinx/toplevel.bit
 
.PHONY: timing
timing:
cd xilinx ; make timing
 
 

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