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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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  • This comparison shows the changes necessary to convert path
    /xulalx25soc/trunk
    from Rev 70 to Rev 71
    Reverse comparison

Rev 70 → Rev 71

/rtl/toplevel.v
1,9 → 1,9
`timescale 10ns / 100ps
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Filename: toplevel.v
//
// Project: XuLA2 board
// Project: XuLA2-LX25 SoC based upon the ZipCPU
//
// Purpose: This is the _top_level_ verilog file for the XuLA2-LX25
// SoC project. Everything else fits underneath here (logically).
11,13 → 11,12
// to this file are the Xilinx primitives necessary to build for the
// XuLA2 board--with the only exception being the ICAPE_SPARTAN6 interface.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
29,11 → 28,16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// `define HELLO_WORLD
84,7 → 88,7
.CLKFX_DIVIDE(3),
.CLKFX_MULTIPLY(20),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(83.333333),
.CLKIN_PERIOD(82),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
/xula.ucf
76,7 → 76,7
# Prototyping Header
##############################
# NET io_chan_clk LOC = T7; # L32N
NET i_rx_uart LOC = R7; # L32P
NET i_rx_uart LOC = B15; # L32P
NET i_gpio<0> LOC = R15; # L49P
NET i_gpio<1> LOC = R16; # L49N
NET i_gpio<2> LOC = M15; # L46P
89,10 → 89,10
NET i_gpio<9> LOC = F16; # L35N
NET i_gpio<10> LOC = C16; # L33N
NET i_gpio<11> LOC = C15; # L33P
NET i_gpio<12> LOC = B16; # L29N
NET i_gpio<13> LOC = B15; # L29P
NET i_gpio<12> LOC = R2; # L29N
NET i_gpio<13> LOC = R7; # L29P
NET o_pwm LOC = T4; # L63N (No differential pair!)
NET o_tx_uart LOC = R2; # L32P
NET o_tx_uart LOC = B16; # L32P
NET o_gpio<0> LOC = R1; # L32N
NET o_gpio<1> LOC = M2; # L35P
NET o_gpio<2> LOC = M1; # L35N
140,6 → 140,7
##############################
NET "i_clk_12mhz" TNM_NET = "i_clk_12mhz";
NET "i_ram_feedback_clk" TNM_NET = "i_ram_feedback_clk";
TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 82 ns HIGH 50%;
# TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
# TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 10.0 ns HIGH 50%;
TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 11.3 ns HIGH 50%;

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