URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
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- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/bench/asm/memtest.S
File deleted
/trunk/bench/asm/memtest.s
0,0 → 1,182
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memtest.S |
// |
// Project: XuLA2 board |
// |
// Purpose: To test whether or not we can interface with the SDRAM on the |
// XuLA2 board. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
#define LFSRFILL 0x000001 |
// #define LFSRTAPS 0x004597f |
#define LFSRTAPS 0x0408b85 |
#define SDRAMBASE 0x0800000 |
// #define SDRAMLEN 0x0800000 |
#define SDRAMLEN 0x0800000 |
#define RAMSCOPE 0x011c |
#define ZIPSCOPE 0x011e |
master_entry: |
MOV user_entry(PC),uPC |
; LDI RAMSCOPE,R8 |
; LDI 0x04000000,R9 |
; STO R9,(R8) |
RTU |
; // Capture what just happened |
; LDI 0x8c000000,R9 |
; STO R9,(R8) |
; NOP |
; |
HALT |
|
user_entry: |
// #define CLEAR_MEMORY |
#ifdef CLEAR_MEMORY |
clear_memory: |
LDI SDRAMBASE,R0 |
LDI SDRAMLEN,R1 |
ADD R0,R1 |
CLR R2 |
clear_memory_loop: |
STO R2,(R0) |
ADD 1,R0 |
CMP R0,R1 |
BGT clear_memory_loop |
end_clear_memory: |
#endif |
|
LDI LFSRFILL,R2 |
LDI LFSRTAPS,R3 |
CLR R12 |
|
write_test: |
LDI SDRAMBASE,R0 |
LDI SDRAMLEN,R1 |
MOV R2,R7 ; Copy our initial fill |
CMP 0,R2 |
HALT.Z |
// #define WAIT_FOR_WRITE_SCOPE |
#ifdef WAIT_FOR_WRITE_SCOPE |
LDI RAMSCOPE,R8 |
LDI 0x01ffc,R9 |
STO R9,(R8) ; Reset the SDRAM scope |
NOP ; Give it a chance to reset |
LDI 0x10000000,R10 |
scope_not_ready: |
NOP |
LOD (R8),R9 |
TST R10,R9 |
BZ scope_not_ready |
#endif |
|
write_test_loop: |
LSR 1,R2 |
XOR.C R3,R2 |
MOV R2,R4 |
|
LSR 1,R2 |
XOR.C R3,R2 |
MOV R2,R5 |
|
LSR 1,R2 |
XOR.C R3,R2 ; wr_reg_ce = R2 |
|
STO R4,(R0) ; op = R4 |
STO R5,1(R0) ; dcdA = R5 |
STO R2,2(R0) ; instruction - R2 |
ADD 3,R0 |
SUB 3,R1 |
CMP 3,R1 |
BGE write_test_loop |
|
read_test: |
LDI SDRAMBASE,R0 |
LDI SDRAMLEN,R1 |
// #define WAIT_FOR_READ_SCOPE |
#ifdef WAIT_FOR_READ_SCOPE |
LDI RAMSCOPE,R8 |
LDI 0x01ffc,R9 |
STO R9,(R8) ; Reset the SDRAM scope |
NOP ; Give it a chance to reset |
LDI 0x10000000,R10 |
not_ready: |
NOP |
LOD (R8),R9 |
TST R10,R9 |
BZ not_ready |
#endif |
// |
// RAM[49072] = 0x02b39ba ... not RAM[0]. What's going on here? |
// |
read_test_loop: |
LOD (R0),R4 |
LOD 1(R0),R5 |
LOD 2(R0),R6 |
|
LSR 1,R7 |
XOR.C R3,R7 |
CMP R7,R4 |
TRAP.NZ 0 |
|
LSR 1,R7 |
XOR.C R3,R7 |
CMP R7,R5 |
TRAP.NZ 0 |
|
LSR 1,R7 |
XOR.C R3,R7 |
CMP R7,R6 |
TRAP.NZ 0 |
|
ADD 3,R0 |
SUB 3,R1 |
CMP 3,R1 |
|
BGE read_test_loop |
|
ADD 1,R12 |
BRA write_test |
; |
; |
; |
; 0x0408b85 |
; 0x060ce47 |
; 0x070eca6 |
; 0x0387653 |
; 0x05cb0ac |
; 0x02e5856 |
; 0x0172c2b |
; 0x04b1d90 |
; 0x0258ec8 |
; 0x012c764 |
; 0x00963b2 |
; 0x004b1d9 |
; 0x042d369 |
; 0x061e231 |
; 0x0707a9d |
; |
; |
/trunk/bench/asm/Makefile
52,7 → 52,7
|
.PHONY: memtest |
memtest: memtest.z |
memtest.z: memtest.S |
memtest.z: memtest.s |
$(ZASM) $< -o $@ |
memtest.txt: memtest.z |
$(ZDUMP) $< > $@ |