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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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Rev 99 → Rev 100

/trunk/rtl/sdspi.v
145,8 → 145,14
//
reg q_busy;
//
reg [7:0] fifo_a_mem[((1<<(LGFIFOLN+2))-1):0];
reg [7:0] fifo_b_mem[((1<<(LGFIFOLN+2))-1):0];
reg [7:0] fifo_a_mem_0[0:((1<<LGFIFOLN)-1)],
fifo_a_mem_1[0:((1<<LGFIFOLN)-1)],
fifo_a_mem_2[0:((1<<LGFIFOLN)-1)],
fifo_a_mem_3[0:((1<<LGFIFOLN)-1)],
fifo_b_mem_0[0:((1<<LGFIFOLN)-1)],
fifo_b_mem_1[0:((1<<LGFIFOLN)-1)],
fifo_b_mem_2[0:((1<<LGFIFOLN)-1)],
fifo_b_mem_3[0:((1<<LGFIFOLN)-1)];
reg [(LGFIFOLN-1):0] fifo_wb_addr;
reg [(LGFIFOLN+1):0] rd_fifo_sd_addr;
reg [(LGFIFOLN+1):0] wr_fifo_sd_addr;
525,15 → 531,15
always @(posedge i_clk)
begin
fifo_a_reg <= {
fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] };
fifo_a_mem_0[ fifo_wb_addr ],
fifo_a_mem_1[ fifo_wb_addr ],
fifo_a_mem_2[ fifo_wb_addr ],
fifo_a_mem_3[ fifo_wb_addr ] };
fifo_b_reg <= {
fifo_b_mem[{ fifo_wb_addr, 2'b00 }],
fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] };
fifo_b_mem_0[ fifo_wb_addr ],
fifo_b_mem_1[ fifo_wb_addr ],
fifo_b_mem_2[ fifo_wb_addr ],
fifo_b_mem_3[ fifo_wb_addr ] };
end
 
// Okay, now ... writing our FIFO ...
590,27 → 596,72
clear_fifo_crc <= (cmd_stb)&&(i_wb_data[15]);
end
 
reg fifo_a_wr, fifo_b_wr;
reg [3:0] fifo_a_wr_mask, fifo_b_wr_mask;
reg [(LGFIFOLN-1):0] fifo_a_wr_addr, fifo_b_wr_addr;
reg [31:0] fifo_a_wr_data, fifo_b_wr_data;
 
initial fifo_crc_err = 1'b0;
always @(posedge i_clk)
begin // One and only memory write allowed
fifo_a_wr <= 1'b0;
fifo_a_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
{fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] }
<= i_wb_data;
else if (pre_fifo_a_wr)
fifo_a_mem[{ ll_fifo_addr }] <= ll_out_dat;
begin
fifo_a_wr <= 1'b1;
fifo_a_wr_mask <= 4'b1111;
fifo_a_wr_addr <= fifo_wb_addr;
fifo_a_wr_data <= i_wb_data;
end else if (pre_fifo_a_wr)
begin
fifo_a_wr <= 1'b1;
fifo_a_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
case(ll_fifo_addr[1:0])
2'b00: fifo_a_wr_mask <= 4'b0001;
2'b01: fifo_a_wr_mask <= 4'b0010;
2'b10: fifo_a_wr_mask <= 4'b0100;
2'b11: fifo_a_wr_mask <= 4'b1000;
endcase
end
 
if ((fifo_a_wr)&&(fifo_a_wr_mask[0]))
fifo_a_mem_0[fifo_a_wr_addr] <= fifo_a_wr_data[7:0];
if ((fifo_a_wr)&&(fifo_a_wr_mask[1]))
fifo_a_mem_1[fifo_a_wr_addr] <= fifo_a_wr_data[15:8];
if ((fifo_a_wr)&&(fifo_a_wr_mask[2]))
fifo_a_mem_2[fifo_a_wr_addr] <= fifo_a_wr_data[23:16];
if ((fifo_a_wr)&&(fifo_a_wr_mask[3]))
fifo_a_mem_3[fifo_a_wr_addr] <= fifo_a_wr_data[31:24];
 
fifo_b_wr <= 1'b0;
fifo_b_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
{fifo_b_mem[{fifo_wb_addr, 2'b00 }],
fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] }
<= i_wb_data;
else if (pre_fifo_b_wr)
fifo_b_mem[{ ll_fifo_addr }] <= ll_out_dat;
begin
fifo_b_wr <= 1'b1;
fifo_b_wr_mask <= 4'b1111;
fifo_b_wr_addr <= fifo_wb_addr;
fifo_b_wr_data <= i_wb_data;
end else if (pre_fifo_b_wr)
begin
fifo_b_wr <= 1'b1;
fifo_b_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
case(ll_fifo_addr[1:0])
2'b00: fifo_b_wr_mask <= 4'b0001;
2'b01: fifo_b_wr_mask <= 4'b0010;
2'b10: fifo_b_wr_mask <= 4'b0100;
2'b11: fifo_b_wr_mask <= 4'b1000;
endcase
end
 
if ((fifo_b_wr)&&(fifo_b_wr_mask[0]))
fifo_b_mem_0[fifo_b_wr_addr] <= fifo_b_wr_data[7:0];
if ((fifo_b_wr)&&(fifo_b_wr_mask[1]))
fifo_b_mem_1[fifo_b_wr_addr] <= fifo_b_wr_data[15:8];
if ((fifo_b_wr)&&(fifo_b_wr_mask[2]))
fifo_b_mem_2[fifo_b_wr_addr] <= fifo_b_wr_data[23:16];
if ((fifo_b_wr)&&(fifo_b_wr_mask[3]))
fifo_b_mem_3[fifo_b_wr_addr] <= fifo_b_wr_data[31:24];
 
if (~r_cmd_busy)
ll_fifo_wr_complete <= 1'b0;
 
634,8 → 685,24
 
always @(posedge i_clk)
begin // Second memory read, this time for the FIFO
fifo_a_byte <= fifo_a_mem[ ll_fifo_addr ];
fifo_b_byte <= fifo_b_mem[ ll_fifo_addr ];
case(ll_fifo_addr[1:0])
2'b00: begin
fifo_a_byte<=fifo_a_mem_0[ll_fifo_addr[(LGFIFOLN+1):2]];
fifo_b_byte<=fifo_b_mem_0[ll_fifo_addr[(LGFIFOLN+1):2]];
end
2'b01: begin
fifo_a_byte<=fifo_a_mem_1[ll_fifo_addr[(LGFIFOLN+1):2]];
fifo_b_byte<=fifo_b_mem_1[ll_fifo_addr[(LGFIFOLN+1):2]];
end
2'b10: begin
fifo_a_byte<=fifo_a_mem_2[ll_fifo_addr[(LGFIFOLN+1):2]];
fifo_b_byte<=fifo_b_mem_2[ll_fifo_addr[(LGFIFOLN+1):2]];
end
2'b11: begin
fifo_a_byte<=fifo_a_mem_3[ll_fifo_addr[(LGFIFOLN+1):2]];
fifo_b_byte<=fifo_b_mem_3[ll_fifo_addr[(LGFIFOLN+1):2]];
end
endcase
end
 
reg [(LGFIFOLN-1):0] r_blklimit;

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