URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 101 to Rev 102
- ↔ Reverse comparison
Rev 101 → Rev 102
/trunk/rtl/wbusixchar.v
1,9 → 1,10
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbusixchar.v |
// |
// Project: XuLA2 board |
// Filename: wbusixchar.v |
// |
// Project: FPGA library |
// |
// Purpose: Supports a conversion from a six digit bus to a printable |
// ASCII character representing those six bits. The encoding is |
// as follows: |
22,7 → 23,7
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/trunk/rtl/wbucompactlines.v
2,7 → 2,7
// |
// Filename: wbucompactlines.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Removes 'end of line' characters placed at the end of every |
// deworded word, unless we're idle or the line is too long. |
15,7 → 15,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/trunk/rtl/wbufifo.v
2,7 → 2,7
// |
// Filename: wbufifo.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: This was once a FIFO for a UART ... but now it works as a |
// synchronous FIFO for JTAG-wishbone conversion 36-bit codewords. |
/trunk/rtl/wbudeword.v
2,7 → 2,7
// |
// Filename: wbudeword.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Once a word has come from the bus, undergone compression, had |
// idle cycles and interrupts placed in it, this routine converts |
16,7 → 16,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/trunk/rtl/wbutohex.v
2,7 → 2,7
// |
// Filename: wbutohex.v |
// |
// Project: XuLA2-LX25 SoC based upon the ZipCPU |
// Project: FPGA library |
// |
// Purpose: Supports a printable character conversion from a printable |
// ASCII character to six bits of valid data. The encoding is |
/trunk/rtl/wbubus.v
2,7 → 2,7
// |
// Filename: wbubus.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: This is the top level file for the entire JTAG-USB to Wishbone |
// bus conversion. (It's also the place to start debugging, should |
16,7 → 16,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
40,7 → 40,7
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, |
i_interrupt, |
o_tx_stb, o_tx_data, i_tx_busy); |
o_tx_stb, o_tx_data, i_tx_busy, o_dbg); |
parameter LGWATCHDOG=19; |
input i_clk; |
input i_rx_stb; |
53,7 → 53,7
output wire o_tx_stb; |
output wire [7:0] o_tx_data; |
input i_tx_busy; |
// output wire [31:0] o_dbg; |
output wire o_dbg; |
|
|
reg r_wdt_reset; |
94,7 → 94,6
o_wb_data[4:0], i_wb_data[4:0] }; |
assign o_dbg = cyc_debug; |
*/ |
|
/* |
wire [31:0] fif_debug; |
assign fif_debug = { |
133,5 → 132,7
r_wdt_reset <= 1'b0; |
end |
|
assign o_dbg = w_bus_reset; |
|
endmodule |
|
/trunk/rtl/wbuoutput.v
2,7 → 2,7
// |
// Filename: wbuoutput.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Converts 36-bit codewords into bytes to be placed on the serial |
// output port. The codewords themselves are the results of bus |
15,7 → 15,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/trunk/rtl/wbureadcw.v
2,7 → 2,7
// |
// Filename: wbureadcw.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Read bytes from a serial port (i.e. the jtagser) and translate |
// those bytes into a 6-byte codeword. This codeword may specify |
17,7 → 17,7
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/trunk/rtl/wbuidleint.v
2,7 → 2,7
// |
// Filename: wbuidleint.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Creates an output for the interface, inserting idle words and |
// words indicating an interrupt has taken place into the output |
16,7 → 16,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |