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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

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Rev 111 → Rev 112

/trunk/bench/cpp/uartsim.cpp
0,0 → 1,234
////////////////////////////////////////////////////////////////////////////////
//
// Filename: uartsim.cpp
//
// Project: XuLA2-LX25 SoC based upon the ZipCPU
//
// Purpose:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <poll.h>
#include <unistd.h>
#include <arpa/inet.h>
#include <signal.h>
 
#include "uartsim.h"
 
void UARTSIM::setup_listener(const int port) {
struct sockaddr_in my_addr;
 
signal(SIGPIPE, SIG_IGN);
 
printf("Listening on port %d\n", port);
 
m_skt = socket(AF_INET, SOCK_STREAM, 0);
if (m_skt < 0) {
perror("Could not allocate socket: ");
exit(-1);
}
 
// Set the reuse address option
{
int optv = 1, er;
er = setsockopt(m_skt, SOL_SOCKET, SO_REUSEADDR, &optv, sizeof(optv));
if (er != 0) {
perror("SockOpt Err:");
exit(-1);
}
}
 
memset(&my_addr, 0, sizeof(struct sockaddr_in)); // clear structure
my_addr.sin_family = AF_INET;
my_addr.sin_addr.s_addr = htonl(INADDR_ANY);
my_addr.sin_port = htons(port);
if (bind(m_skt, (struct sockaddr *)&my_addr, sizeof(my_addr))!=0) {
perror("BIND FAILED:");
exit(-1);
}
 
if (listen(m_skt, 1) != 0) {
perror("Listen failed:");
exit(-1);
}
}
 
UARTSIM::UARTSIM(const int port) {
m_con = m_skt = -1;
setup_listener(port);
setup(25);
m_rx_baudcounter = 0;
m_tx_baudcounter = 0;
m_rx_state = RXIDLE;
m_tx_state = TXIDLE;
}
 
void UARTSIM::kill(void) {
// Close any active connection
if (m_con >= 0) close(m_con);
if (m_skt >= 0) close(m_skt);
}
 
void UARTSIM::setup(unsigned isetup) {
if (isetup != m_setup) {
m_setup = isetup;
m_baud_counts = (isetup & 0x0ffffff);
m_nbits = 8-((isetup >> 28)&0x03);
m_nstop =((isetup >> 27)&1)+1;
m_nparity = (isetup >> 26)&1;
m_fixdp = (isetup >> 25)&1;
m_evenp = (isetup >> 24)&1;
}
}
 
int UARTSIM::tick(int i_tx) {
int o_rx = 1;
 
if (m_con < 0) {
// Can we accept a connection?
struct pollfd pb;
 
pb.fd = m_skt;
pb.events = POLLIN;
poll(&pb, 1, 0);
 
if (pb.revents & POLLIN) {
m_con = accept(m_skt, 0, 0);
 
if (m_con < 0)
perror("Accept failed:");
}
}
 
if ((!i_tx)&&(m_last_tx))
m_rx_changectr = 0;
else m_rx_changectr++;
m_last_tx = i_tx;
 
if (m_rx_state == RXIDLE) {
if (!i_tx) {
m_rx_state = RXDATA;
m_rx_baudcounter =m_baud_counts+m_baud_counts/2;
m_rx_baudcounter -= m_rx_changectr;
m_rx_busy = 0;
m_rx_data = 0;
}
} else if (m_rx_baudcounter <= 0) {
if (m_rx_busy >= (1<<(m_nbits+m_nparity+m_nstop-1))) {
m_rx_state = RXIDLE;
if (m_con > 0) {
char buf[1];
buf[0] = (m_rx_data >> (32-m_nbits-m_nstop-m_nparity))&0x0ff;
if (1 != send(m_con, buf, 1, 0)) {
close(m_con);
m_con = -1;
}
}
} else {
m_rx_busy = (m_rx_busy << 1)|1;
// Low order bit is transmitted first, in this
// order:
// Start bit (1'b1)
// bit 0
// bit 1
// bit 2
// ...
// bit N-1
// (possible parity bit)
// stop bit
// (possible secondary stop bit)
m_rx_data = ((i_tx&1)<<31) | (m_rx_data>>1);
} m_rx_baudcounter = m_baud_counts;
} else
m_rx_baudcounter--;
 
if (m_tx_state == TXIDLE) {
struct pollfd pb;
pb.fd = m_con;
pb.events = POLLIN;
if (poll(&pb, 1, 0) < 0)
perror("Polling error:");
if (pb.revents & POLLIN) {
char buf[1];
if (1 == recv(m_con, buf, 1, MSG_DONTWAIT)) {
m_tx_data = (-1<<(m_nbits+m_nparity+1))
// << nstart_bits
|((buf[0]<<1)&0x01fe);
if (m_nparity) {
int p;
if (m_fixdp)
p = m_evenp;
else {
int p = (m_tx_data >> 1)&0x0ff;
p = p ^ (p>>4);
p = p ^ (p>>2);
p = p ^ (p>>1);
p &= 1;
p ^= m_evenp;
}
m_tx_data |= (p<<(m_nbits+m_nparity));
}
m_tx_busy = (1<<(m_nbits+m_nparity+m_nstop+1))-1;
m_tx_state = TXDATA;
o_rx = 0;
m_tx_baudcounter = m_baud_counts;
}
}
} else if (m_tx_baudcounter == 0) {
m_tx_data >>= 1;
m_tx_busy >>= 1;
if (!m_tx_busy)
m_tx_state = TXIDLE;
else
m_tx_baudcounter = m_baud_counts;
o_rx = m_tx_data&1;
} else {
m_tx_baudcounter--;
o_rx = m_tx_data&1;
}
 
return o_rx;
}
 
/*
0x00 -> c0 = 1100 0000???
0x01 -> c0 = 1100 0000??
0x02 -> c0 = 1100 0000?
0x04 -> c1 = 1100 0001
0x20 -> c5 = 1100 0101
0x40 -> ca = 1100 1010
0x80 -> d4 = 1101 0100
*/
/trunk/bench/cpp/uartsim.h
0,0 → 1,78
////////////////////////////////////////////////////////////////////////////////
//
// Filename: uartsim.h
//
// Project: XuLA2-LX25 SoC based upon the ZipCPU
//
// Purpose:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef UARTSIM_H
#define UARTSIM_H
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <poll.h>
#include <unistd.h>
#include <arpa/inet.h>
#include <signal.h>
 
#define TXIDLE 0
#define TXDATA 1
#define RXIDLE 0
#define RXDATA 1
 
class UARTSIM {
int m_skt, m_con;
unsigned m_setup;
int m_nparity, m_fixdp, m_evenp, m_nbits, m_nstop, m_baud_counts;
int m_rx_baudcounter, m_rx_state, m_rx_busy,
m_rx_changectr, m_last_tx;
int m_tx_baudcounter, m_tx_state, m_tx_busy;
unsigned m_rx_data, m_tx_data;
 
void setup_listener(const int port);
int tick(const int i_tx);
 
public:
UARTSIM(const int port);
void kill(void);
void setup(unsigned isetup);
int operator()(int i_tx) {
return tick(i_tx); }
int operator()(int i_tx, unsigned isetup) {
setup(isetup); return tick(i_tx); }
};
 
#endif
/trunk/bench/cpp/busmaster_tb.cpp
42,6 → 42,7
//
#include <signal.h>
#include <time.h>
#include <ctype.h>
 
#include "verilated.h"
#include "Vbusmaster.h"
52,6 → 53,7
#include "qspiflashsim.h"
#include "sdramsim.h"
#include "sdspisim.h"
#include "uartsim.h"
 
#include "port.h"
 
72,8 → 74,9
unsigned m_last_led;
time_t m_start_time;
bool m_last_writeout;
UARTSIM m_uart;
 
BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) {
BUSMASTER_TB(void) : PIPECMDR(FPGAPORT), m_uart(FPGAPORT+1) {
m_start_time = time(NULL);
}
 
124,289 → 127,18
m_core->o_ram_we_n, m_core->o_ram_bs,
m_core->o_ram_addr, m_core->o_ram_drive_data,
m_core->o_ram_data);
 
m_core->i_rx_uart = m_uart(m_core->o_tx_uart,
m_core->v__DOT__serialport__DOT__r_setup);
PIPECMDR::tick();
 
bool writeout = false;
/*
if (m_core->v__DOT__sdram__DOT__r_pending)
writeout = true;
else if (m_core->v__DOT__sdram__DOT__bank_active[0])
writeout = true;
else if (m_core->v__DOT__sdram__DOT__bank_active[1])
writeout = true;
else if (m_core->v__DOT__sdram__DOT__bank_active[2])
writeout = true;
else if (m_core->v__DOT__sdram__DOT__bank_active[3])
writeout = true;
*/
 
if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
writeout = true;
/*
if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
writeout = true;
if (m_core->v__DOT__genbus__DOT__exec_stb)
writeout = true;
*/
 
#define v__DOT__wb_addr v__DOT__dwb_addr
#define v__DOT__dwb_stall v__DOT__wb_stall
#define v__DOT__dwb_ack v__DOT__wb_ack
#define v__DOT__wb_cyc v__DOT__dwb_cyc
#define v__DOT__wb_stb v__DOT__dwb_stb
#define v__DOT__wb_we v__DOT__dwb_we
#define v__DOT__dwb_idata v__DOT__wb_idata
#define v__DOT__wb_data v__DOT__dwb_odata
 
if (!m_core->v__DOT__zippy__DOT__cmd_halt)
writeout = true;
 
if (!m_core->o_sd_cs_n)
writeout = true;
else if (!m_core->v__DOT__sdcard_cs_n)
writeout = true;
else if ((((m_core->v__DOT__wb_addr ^ 0x0120)&(~0x03))==0)
&&(m_core->v__DOT__wb_cyc))
writeout = true;
 
/*
writeout = (writeout)||(m_core->i_rx_stb)
||((m_core->o_tx_stb)&&(!m_core->i_tx_busy));
writeout = (writeout)||(m_core->v__DOT____Vcellinp__genbus____pinNumber9);
writeout = (writeout)||(m_core->v__DOT__wb_stb);
writeout = (writeout)||(m_core->v__DOT__wb_err);
*/
 
if ((writeout)||(m_last_writeout)) {
printf("%08lx:", m_tickcount);
 
/*
printf("%d/%02x %d/%02x%s ",
m_core->i_rx_stb, m_core->i_rx_data,
m_core->o_tx_stb, m_core->o_tx_data,
m_core->i_tx_busy?"/BSY":" ");
*/
 
printf("(%d,%d->%d),(%c:%d,%d->%d)|%c[%08x/%08x]@%08x %c%c%c",
m_core->v__DOT__wbu_cyc,
m_core->v__DOT__dwb_cyc, // was zip_cyc
m_core->v__DOT__wb_cyc,
//
m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner?'Z':'j',
m_core->v__DOT__wbu_stb,
// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
m_core->v__DOT__wb_stb,
//
(m_core->v__DOT__wb_we)?'W':'R',
m_core->v__DOT__wb_data,
m_core->v__DOT__dwb_idata,
m_core->v__DOT__wb_addr,
(m_core->v__DOT__dwb_ack)?'A':
(m_core->v__DOT____Vcellinp__genbus____pinNumber9)?'a':' ',
(m_core->v__DOT__dwb_stall)?'S':
(m_core->v__DOT____Vcellinp__genbus____pinNumber10)?'s':' ',
(m_core->v__DOT__wb_err)?'E':'.');
 
printf(" RUNWB %d:%09lx %d@0x%08x %3x %3x %d %d/%d/%d %d:%09lx",
m_core->v__DOT__genbus__DOT__fifo_in_stb,
m_core->v__DOT__genbus__DOT__fifo_in_word,
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
m_core->v__DOT__wbu_addr,
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed,
m_core->v__DOT__genbus__DOT__runwb__DOT__w_eow,
m_core->v__DOT__genbus__DOT__runwb__DOT__last_read_request,
m_core->v__DOT__genbus__DOT__runwb__DOT__last_ack,
m_core->v__DOT__genbus__DOT__runwb__DOT__zero_acks,
m_core->v__DOT__genbus__DOT__exec_stb,
m_core->v__DOT__genbus__DOT__exec_word);
 
printf(" WBU[%d,%3d,%3d]",
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed);
 
/*
printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
(m_core->v__DOT__sdram_sel)?'!':' ',
m_core->o_ram_cs_n, m_core->o_ram_ras_n,
m_core->o_ram_cas_n, m_core->o_ram_we_n,
m_core->o_ram_bs, m_core->o_ram_data,
(m_core->o_ram_drive_data)?'D':'-',
m_core->o_ram_addr,
(m_core->o_ram_addr>>10)&1,
m_core->i_ram_data,
(m_core->o_ram_drive_data)?'-':'V');
 
printf(" SD[%d,%d-%3x%d]",
m_core->v__DOT__sdram__DOT__r_state,
m_sdram.pwrup(),
m_core->v__DOT__sdram__DOT__refresh_clk,
m_core->v__DOT__sdram__DOT__need_refresh);
 
printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
m_core->v__DOT__sdram__DOT__bank_active[0],
m_core->v__DOT__sdram__DOT__bank_row[0],
m_core->v__DOT__sdram__DOT__bank_active[1],
m_core->v__DOT__sdram__DOT__bank_row[1],
m_core->v__DOT__sdram__DOT__bank_active[2],
m_core->v__DOT__sdram__DOT__bank_row[2],
m_core->v__DOT__sdram__DOT__bank_active[3],
m_core->v__DOT__sdram__DOT__bank_row[3],
m_core->v__DOT__sdram__DOT__clocks_til_idle,
m_core->v__DOT__sdram__DOT__r_barrell_ack);
 
printf(" %s%s%c[%08x@%06x]",
(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
(m_core->v__DOT__sdram__DOT__r_we)
?(m_core->v__DOT__sdram__DOT__r_data)
:(m_core->v__DOT__sdram_data),
(m_core->v__DOT__sdram__DOT__r_addr));
*/
 
/*
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x %s%s %2d %2d",
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_halted)?"Z":"-",
(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_valid)?"V":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?"D":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"d":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_alu)?"A":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_ce)?"a":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)?"M":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_ce)?"m":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-",
(m_core->v__DOT__zippy__DOT__cmd_addr),
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ibus_err_flag)?"IB":" ",
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ubus_err_flag)?"UB":" ",
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__rdaddr,
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__wraddr);
 
printf(" PC0x%08x/%08x/%08x-%08x %s0x%08x",
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
m_core->v__DOT__zippy__DOT__thecpu__DOT__ipc,
m_core->v__DOT__zippy__DOT__thecpu__DOT__upc,
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":" ",
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc
);
 
printf(" %s[%02x]=%08x(%08x)",
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce?"WR":"--",
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl,
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_spreg_vl);
*/
 
/*
printf(" SDSPI[%d,%d(%d),(%d)]",
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy,
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
m_core->v__DOT__sdcard_controller__DOT__r_cmd_state,
m_core->v__DOT__sdcard_controller__DOT__r_rsp_state);
printf(" LL[%d,%2x->CK=%d/%2x,%s,ST=%2d,TX=%2x,RX=%2x->%d,%2x] ",
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_stb,
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_dat,
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_z_counter,
// (m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter==0)?1:0,
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter,
(m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_idle)?"IDLE":" ",
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_state,
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_byte,
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_ireg,
m_core->v__DOT__sdcard_controller__DOT__ll_out_stb,
m_core->v__DOT__sdcard_controller__DOT__ll_out_dat
);
printf(" CRC=%02x/%2d",
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc,
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc_cnt);
printf(" SPI(%d,%d,%d/%d,%d)->?",
m_core->o_sf_cs_n,
m_core->o_sd_cs_n,
m_core->o_spi_sck, m_core->v__DOT__sdcard_sck,
m_core->o_spi_mosi);
 
printf(" CK=%d,LN=%d",
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
m_core->v__DOT__sdcard_controller__DOT__r_lgblklen);
 
 
if (m_core->v__DOT__sdcard_controller__DOT__r_use_fifo){
printf(" FIFO");
if (m_core->v__DOT__sdcard_controller__DOT__r_fifo_wr)
printf("-WR(%04x,%d,%d,%d)",
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_reg,
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_stb,
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_pkt_state,
m_core->v__DOT__sdcard_controller__DOT__r_have_data_response_token);
else
printf("-RD(%04x,%d,%d,%d)",
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_reg,
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_stb,
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_state,
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_complete
);
}
 
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_rd)
printf(" LL-RD");
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr)
printf(" LL-WR");
if (m_core->v__DOT__sdcard_controller__DOT__r_have_start_token)
printf(" START-TOK");
printf(" %3d/%02x",
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_addr,
m_core->v__DOT__sdcard_controller__DOT__fifo_byte&0x0ff);
*/
 
 
/*
printf(" DMAC[%d]: %08x/%08x/%08x(%03x) -- (%d,%d,%c)%c%c:@%08x-[%4d,%4d/%4d,%4d-#%4d]%08x",
m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_waddr,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_raddr,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_len,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_blocklen_sub_one,
m_core->v__DOT__zippy__DOT__dc_cyc,
// m_core->v__DOT__zippy__DOT__dc_stb,
(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 2)?1:0,
 
((m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 4)
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 5)
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 6))?'W':'R',
//(m_core->v__DOT__zippy__DOT__dc_we)?'W':'R',
(m_core->v__DOT__zippy__DOT__dc_ack)?'A':' ',
(m_core->v__DOT__zippy__DOT__dc_stall)?'S':' ',
m_core->v__DOT__zippy__DOT__dc_addr,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__rdaddr,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nread,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nracks,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwacks,
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwritten,
m_core->v__DOT__zippy__DOT__dc_data);
 
printf(" %08x-PIC%08x",
m_core->v__DOT__zippy__DOT__main_int_vector,
m_core->v__DOT__zippy__DOT__pic_data);
*/
 
printf("\n"); fflush(stdout);
} m_last_writeout = writeout;
 
}
 
};
/trunk/bench/cpp/Makefile
65,10 → 65,13
$(OBJDIR)/:
@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
 
CLSHEADERS: qspiflashsim.h sdramsim.h sdspisim.h
CLSSOURCES: $(subst .h,.cpp,$(CLSHEADERS))
CLSOBJECTS: $(addprefix $(OBJDIR)/,$(subst .h,.o,$(CLSHEADERS)))
CLSHEADERS:= qspiflashsim.h sdramsim.h sdspisim.h uartsim.h
CLSSOURCES:= $(subst .h,.cpp,$(CLSHEADERS))
CLSOBJECTS:= $(addprefix $(OBJDIR)/,$(subst .h,.o,$(CLSHEADERS)))
 
SOURCES := $(CLSSOURCES)
HEADERS := $(CLSHEADERS)
 
$(OBJDIR)/%.o: %.cpp
$(CXX) $(CFLAGS) $< -o $@
$(OBJDIR)/busmaster_tb.o: busmaster_tb.cpp pipecmdr.h sdramsim.h
78,9 → 81,9
$(CXX) $(CFLAGS) $< -o $@
 
busmaster_tb: $(OBJDIR)/qspiflashsim.o $(OBJDIR)/sdspisim.o
busmaster_tb: $(OBJDIR)/verilated.o
busmaster_tb: $(VOBJDR)/Vbusmaster__ALL.a
busmaster_tb: $(OBJDIR)/busmaster_tb.o $(OBJDIR)/sdramsim.o
busmaster_tb: $(OBJDIR)/uartsim.o $(OBJDIR)/sdramsim.o
busmaster_tb: $(OBJDIR)/verilated.o $(VOBJDR)/Vbusmaster__ALL.a
busmaster_tb: $(OBJDIR)/busmaster_tb.o
$(CXX) -g -o $@ $^
 
define build-depends

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