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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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  • This comparison shows the changes necessary to convert path
    /xulalx25soc
    from Rev 13 to Rev 14
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Rev 13 → Rev 14

/trunk/rtl/wbudecompress.v
57,11 → 57,13
 
reg [31:0] compression_tbl [0:255];
always @(posedge i_clk)
if (i_stb)
compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
 
reg [35:0] r_word;
always @(posedge i_clk)
r_word <= i_word;
if (i_stb)
r_word <= i_word;
 
 
// Clock two, calculate the table address ... 1 is the smallest address
127,14 → 129,21
if (r_word[35:30] == 6'b101110)
o_word <= r_word;
else casez(r_word[35:30])
// Set address from something compressed ... unsigned
6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0] };
// Set a new address as a signed offset from the last (set) one
// (The last address is kept further down the chain,
// we just mark here that the address is to be set
// relative to it, and by how much.)
6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0]};
// Write a value to the bus, with the value given from our
// codeword table
6'b010???: o_word <=
{ 3'h3, cword[31:30], r_word[30], cword[29:0] };
6'b10????: o_word <= { 5'b11000, r_word[30],
20'h00, rd_len };
6'b11????: o_word <= { 5'b11000, r_word[30],
20'h00, rd_len };
// Read, highly compressed length (1 word)
6'b10????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
// Read, two word (3+9 bits) length
6'b11????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
default: o_word <= r_word;
endcase
endmodule

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