OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xulalx25soc
    from Rev 15 to Rev 16
    ↔ Reverse comparison
  •

Rev 15 → Rev 16

/trunk/bench/asm/cfgtest.s
0,0 → 1,138
////////////////////////////////////////////////////////////////////////////////
//
// Filename: cfgtest.s
//
// Project: XuLA2 board
//
// Purpose: To test whether or not the SPARTAN6_ICAPE interface works with
// the wbicape6.v / wbicapesimple.v modules.
//
// Normally, I'd do this test using wbregs only. In this case, that's
// not possible. wbregs requires the use of the JTAG port for the XuLA
// board. Further, JTAG and ICAPE cannot be used at the same time. So
// our goal instead will be to use wbregs and ziprun to start this program,
// to disconnect (i.e. stop using wbregs and ziprun, just leaving the CPU
// to run), to wait for an RTC alarm, to trigger the configuration port
// scope, and then to see how we did. That's a lot, but doing things in
// order is what a CPU is for--so let's see how we do.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include "dev.i"
#include "sys.i"
master_entry:
BRA end_of_data
external_data:
cfg_result:
WORD 0
status:
WORD 0
end_of_data:
; Set up our stacks--though I don't think we'll need them
MOV sys_stack(PC),SP
MOV user_stack(PC),uSP
;
; Clear our registers
CLR R0
CLR R1
CLR R2
CLR R3
CLR R4
CLR R5
CLR R6
CLR R7
CLR R8
CLR R9
CLR R10
CLR R11
MOV R0,uR0
MOV R0,uR1
MOV R0,uR2
MOV R0,uR3
MOV R0,uR4
MOV R0,uR5
MOV R0,uR6
MOV R0,uR7
MOV R0,uR8
MOV R0,uR9
MOV R0,uR10
MOV R0,uR12
 
;
; Reset and prime our scope
LDI dev.cfgscope,R12
LDI 0x03fc,R0
STO R0,(R12)
;
; Wait on an alarm
LDI sys.bus,R12
LDI 0x7fffffff,R0 // Clear and disable all interrupts
STO R0,(R12)
; LDI RTCINTEN|0x0ffff,R0 // Enable the RTC interrupt
LDI 0x8080ffff,R0
STO R0,(R12)
;
MOV user_idle(PC),uPC
RTU
;
LDI 0x0080ffff,R0
STO R0,(R12)
;
MOV user_entry(PC),uPC
MOV user_stack(PC),uSP
;
RTU
;
HALT
HALT
BUSY
HALT
 
user_idle:
WAIT
BRA user_idle
 
user_entry:
LDI dev.cfg,R1
LOD (R1),R0
ADD 5,R0
STO R0,cfg_result(PC)
LDI 14,R0
LDI dev.cfg.cmd,R1
STO R0,(R1)
NOOP
TRAP 0
 
user_end_of_stack:
FILL 512,0
user_stack:
sys_end_of_stack:
FILL 512,0
sys_stack:
WORD 0
 
;
;
/trunk/bench/asm/dev.i
1,20 → 1,60
////////////////////////////////////////////////////////////////////////////////
//
// Filename: dev.i
//
// Project: XuLA2 board
//
// Purpose: Defines where the various registers are on the board by name,
// so that henceforth they can be referenced by name.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
dev.base equ 0x0100
dev.version equ 2
dev.pic equ 3
dev.buserr equ 4
dev.rtc.date equ 5
dev.gpio equ 6
dev.uart.ctrl equ 7
dev.pwm equ 8
dev.uart.rx equ 10
dev.uart.tx equ 11
dev.qspi equ 12
dev.rtc.clock equ 16
dev.rtc.timer equ 17
dev.rtc.stopwatch equ 18
dev.rtc.alarm equ 19
dev.fscope equ 0x01c
dev.ramscope equ 0x01e
dev.version equ 0x0102
dev.pic equ 0x0103
dev.buserr equ 0x0104
; dev.rtc.date equ 0x0105
dev.gpio equ 0x0106
dev.uart.ctrl equ 0x0107
dev.pwm equ 0x0108
dev.uart.rx equ 0x010a
dev.uart.tx equ 0x010b
dev.qspi equ 0x010c
dev.rtc.clock equ 0x0110
dev.rtc.timer equ 0x0111
dev.rtc.stopwatch equ 0x0112
dev.rtc.alarm equ 0x0113
dev.scope equ 0x0118
dev.flashscope equ 0x011c
dev.cfgscope equ 0x011a
dev.ramscope equ 0x011c
dev.zipscope equ 0x011e
dev.cfg equ 0x0140
dev.cfg.cmd equ 0x0145
dev.cfg.wbstarlo equ 0x0153 // GENERAL 1, p134
dev.mem.base equ 0x0002000
dev.mem.last equ 0x0003fff
dev.flash.base equ 0x0040000
/trunk/bench/asm/sys.i
0,0 → 1,143
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename: sys.i
;
; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose: This is the beginnings of a system wide header file for the
; Zip System. It describes and declares the peripherals
; that will the be used and referenced by the assembly files.
;
; Status: As of August, 2015, I have no confidence that the preprocessor
; can properly include this file. It certainly cannot handle
; macros (yet).
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; License: GPL, v3, as defined and found on www.gnu.org,
; http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
sys.bus equ 0xc0000000
sys.breaken equ 0x080
sys.step equ 0x040
sys.gie equ 0x020
sys.sleep equ 0x010
sys.ccv equ 0x008
sys.ccn equ 0x004
sys.ccc equ 0x002
sys.ccz equ 0x001
sys.bus.pic equ 0x000
sys.bus.wdt equ 0x001
sys.bus.wdbus equ 0x002
sys.bus.apic equ 0x003
sys.bus.tma equ 0x004
sys.bus.tmb equ 0x005
sys.bus.tmc equ 0x006
sys.bus.jiffies equ 0x007
sys.mctr.task equ 0x008
sys.mctr.mstl equ 0x009
sys.mctr.pstl equ 0x00a
sys.mctr.icnt equ 0x00b
sys.uctr.task equ 0x00c
sys.uctr.mstl equ 0x00d
sys.uctr.pstl equ 0x00e
sys.uctr.icnt equ 0x00f
sys.dma equ 0x010
 
 
 
; Define the location(s) of our peripherals,
#define sys.base 0xc0000000
#struct sys
pic
wdt
cache
ctrpic
tma
tmb
tmc
jiffies
mtask
mstl
mpstl
mastl
utask
ustl
upstl
uastl
#endstruct
; and their associated interrupt vectors ...
#define DMAINT 0x0001
#define JIFFYINT 0x0002 ;
#define TMCINT 0x0004 ;
#define TMBINT 0x0008 ;
#define TMAINT 0x0010 ;
#define CTRPICINT 0x0020 ; The aux interrupt controller
#define RTCINT 0x0080 ;
#define FLASHINT 0x0100 ;
#define SCOPINT 0x0200 ;
#define GPIOINT 0x0400 ;
#define PWMINT 0x0800 ;
#define RXUARTINT 0x1000 ;
#define TXUARTINT 0x2000 ;
; Masks to send to enable those same vectors
#define ENABLE_INTS 0x80000000
#define DMAINTEN (ENABLE_INTS|(DMAINT<<16))
#define JIFFYINTEN (ENABLE_INTS|(JIFFYINT<<16))
#define TMCINTEN (ENABLE_INTS|(TMCINT<<16))
#define TMBINTEN (ENABLE_INTS|(TMBINT<<16))
#define TMAINTEN (ENABLE_INTS|(TMAINT<<16))
#define CTRPICEN (ENABLE_INTS|(CTRPICINT<<16))
#define RTCINTEN (ENABLE_INTS|(RTCINT<<16))
#define FLASHINTEN (ENABLE_INTS|(FLASHINT<<16))
#define SCOPINTEN (ENABLE_INTS|(SCOPINT<<16))
#define GPIOINTEN (ENABLE_INTS|(GPIOINT<<16))
#define PWMINTEN (ENABLE_INTS|(PWMINT<<16))
#define RXUARTINTEN (ENABLE_INTS|(RXUARTINT<<16))
#define TXUARTINTEN (ENABLE_INTS|(TXUARTINT<<16))
; And similar masks to disable them
#define DMAINTDIS (DMAINT<<16)
#define JIFFYINTDIS (JIFFYINT<<16)
#define TMCINTDIS (TMCINT<<16)
#define TMBINTDIS (TMBINT<<16)
#define TMAINTDIS (TMAINT<<16)
#define CTRPICDIS (ENABLE_INTS|(CTRPICINT<<16)
#define RTCINTDIS (RTCINT<<16)
#define FLASHINTDIS (FLASHINT<<16)
#define SCOPINTDIS (SCOPINT<<16)
#define GPIOINTDIS (GPIOINT<<16)
#define PWMINTDIS (PWMINT<<16)
#define RXUARTINTDIS (RXUARTINT<<16)
#define TXUARTINTDIS (TXUARTINT<<16)
 
; Define our condition code bits
#define CCZ 0x001
#define CCC 0x002
#define CCN 0x004
#define CCV 0x008
#define CCSLEEP 0x010
#define CCGIE 0x020
#define CCSTEP 0x040
#define CCUBRK 0x080
 
#define FJSR(LBL,RG) MOV __here__+2(PC),RG \
BRA LBL
#define FRET(RG) JMP RG
/trunk/bench/asm/Makefile
57,6 → 57,13
memtest.txt: memtest.z
$(ZDUMP) $< > $@
 
.PHONY: cfgtest
cfgtest: cfgtest.z
cfgtest.z: cfgtest.s dev.i sys.i
$(ZASM) $< -o $@
cfgtest.txt: cfgtest.z
$(ZDUMP) $< > $@
 
.PHONY:
clean:
@rm memtest.z memtest.txt

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.