URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/rtl/toplevel.v
82,7 → 82,7
DCM_SP #( |
.CLKDV_DIVIDE(2.0), |
.CLKFX_DIVIDE(3), |
.CLKFX_MULTIPLY(19), |
.CLKFX_MULTIPLY(20), |
.CLKIN_DIVIDE_BY_2("FALSE"), |
.CLKIN_PERIOD(83.333333), |
.CLKOUT_PHASE_SHIFT("NONE"), |
/trunk/rtl/rxuart.v
298,7 → 298,7
end |
end else begin |
o_wr <= 1'b0; // data_reg = data_reg |
baud_counter <= baud_counter - 1; |
baud_counter <= baud_counter - 28'd1; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end |
/trunk/rtl/builddate.v
1,7 → 298,7
link ../20160102-build.v |
link ../20160104-build.v |
/trunk/rtl/ioslave.v
160,8 → 160,9
wire [31:0] ck_data; |
wire ck_ppd; |
rtclight |
#(32'h388342) // 76 MHz clock (2^48 / 76e6) |
// #(32'h35afe5) // 80 MHz clock |
// #(32'h3ba6fe) // 72 MHz clock (2^48 / 72e6) |
// #(32'h388342) // 76 MHz clock (2^48 / 76e6) |
#(32'h35afe5) // 80 MHz clock |
// #(32'h2eaf36) // 92 MHz clock |
// #(32'h2af31d) // 100 MHz clock |
theclock(i_clk, i_wb_cyc, (i_wb_stb)&&(i_wb_addr[4]), |
/trunk/rtl/busmaster.v
44,11 → 44,15
`define IMPLEMENT_ONCHIP_RAM |
`define FANCY_ICAP_ACCESS |
`define FLASH_ACCESS |
// `define SDCARD_ACCESS // Not built yet ... |
// |
// |
// `define FLASH_SCOPE |
`ifdef FANCY_ICAP_ACCESS |
`define CFG_SCOPE |
`endif |
// `define SDRAM_SCOPE |
`define ZIP_SCOPE |
// `define SDCARD_ACCESS |
module busmaster(i_clk, i_rst, |
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy, |
// The SPI Flash lines |
539,7 → 543,7
`ifdef CFG_SCOPE |
wire scop_cfg_trigger; |
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel); |
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope, |
wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope, |
// Wishbone interface |
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)), |
wb_we, wb_addr[0], wb_data, |
/trunk/xilinx/toplevel.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/xilinx/Makefile
94,8 → 94,8
ngdbuild -intstyle ise -dd _ngo -nt timestamp \ |
-uc $(UCFFILE) -p $(PART) $(OBJDIR)/$(PROJECT).ngc $(OBJDIR)/$(PROJECT).ngd |
|
MAPOPTS := -w -detail -logic_opt on -ol high -xe n -t 1 -xt 0 -r 4 \ |
-global_opt area -equivalent_register_removal on -mt 2 -detail \ |
MAPOPTS := -w -logic_opt on -ol high -xe n -t 1 -xt 0 -r 4 \ |
-global_opt speed -equivalent_register_removal on -mt 2 -detail \ |
-ir off -ignore_keep_hierarchy -pr off -lc area -power off |
$(OBJDIR)/$(PROJECT).ncd: $(OBJDIR)/$(PROJECT).ngd |
map -intstyle ise -p $(PART) $(MAPOPTS) \ |
/trunk/Makefile
1,3 → 1,36
################################################################################ |
## |
## Filename: |
## |
## Project: XuLA2 board |
## |
## Purpose: |
## |
## |
## Creator: Dan Gisselquist, Ph.D. |
## Gisselquist Technology, LLC |
## |
################################################################################ |
## |
## Copyright (C) 2015, Gisselquist Technology, LLC |
## |
## This program is free software (firmware): you can redistribute it and/or |
## modify it under the terms of the GNU General Public License as published |
## by the Free Software Foundation, either version 3 of the License, or (at |
## your option) any later version. |
## |
## This program is distributed in the hope that it will be useful, but WITHOUT |
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## License: GPL, v3, as defined and found on www.gnu.org, |
## http:##www.gnu.org/licenses/gpl.html |
## |
## |
################################################################################ |
## |
## |
.PHONY: all |
all: datestamp verilated bit |
# Could also depend upon load, if desired, but not necessary |