Subversion Repositories xulalx25soc

/trunk/bench/asm/memtest.S

/trunk/bench/asm/dev.i

/trunk/bench/asm/genlrs.S

/trunk/bench/asm/Makefile

/trunk/bench/cpp/sdramsim.cpp

/trunk/bench/cpp/pipecmdr.cpp

/trunk/bench/cpp/qspiflashsim.cpp

/trunk/bench/cpp/sdramsim.h

/trunk/bench/cpp/testb.h

/trunk/bench/cpp/usbi.h

trunk/bench/cpp/usbi.h Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/cpp/pipecmdr.h =================================================================== --- trunk/bench/cpp/pipecmdr.h (nonexistent) +++ trunk/bench/cpp/pipecmdr.h (revision 4) @@ -0,0 +1,217 @@ +// +// +// Filename: pipecmdr.h +// +// Project: FPGA testbench utilities. +// +// Purpose: This program attaches to a Verilated Verilog IP core. +// It will not work apart from such a core. Once attached, +// it connects the simulated core to a controller via a +// pipe interface designed to act like a UART. Indeed, it +// is hoped that the final interface would be via UART. Until +// that point, however, this is just a simple test facility +// designed to verify that the IP core works prior to such +// actual hardware implementation. +// +// Creator: Dan Gisselquist +// Gisselquist Tecnology, LLC +// +// Copyright: 2015 +// +// +#ifndef PIPECMDR_H +#define PIPECMDR_H + +#include +#include +#include +#include +#include + +#include "testb.h" + +#define PIPEBUFLEN 256 + +// At 115200 Baud, 8 bits of data, no parity and one stop bit, there will +// bit ten bits per character and therefore 8681 clocks per transfer +// 8681 ~= 100 MHz / 115200 (bauds / second) * 10 bauds / character +// +// #define UARTLEN 8681 // Minimum ticks per character, 115200 Baud +// +// At 4MBaud, each bit takes 25 clocks. 10 bits would thus take 250 clocks +// +#define UARTLEN 250 // Minimum ticks per character, 4M Baud +// #define UARTLEN 8 // Minimum ticks per character + +template class PIPECMDR : public TESTB { + void setup_listener(const int port) { + struct sockaddr_in my_addr; + + printf("Listening on port %d\n", port); + + m_skt = socket(AF_INET, SOCK_STREAM, 0); + if (m_skt < 0) { + perror("Could not allocate socket: "); + exit(-1); + } + + // Set the reuse address option + { + int optv = 1, er; + er = setsockopt(m_skt, SOL_SOCKET, SO_REUSEADDR, &optv, sizeof(optv)); + if (er != 0) { + perror("SockOpt Err:"); + exit(-1); + } + } + + memset(&my_addr, 0, sizeof(struct sockaddr_in)); // clear structure + my_addr.sin_family = AF_INET; + my_addr.sin_addr.s_addr = htonl(INADDR_ANY); + my_addr.sin_port = htons(port); + + if (bind(m_skt, (struct sockaddr *)&my_addr, sizeof(my_addr))!=0) { + perror("BIND FAILED:"); + exit(-1); + } + + if (listen(m_skt, 1) != 0) { + perror("Listen failed:"); + exit(-1); + } + } + +public: + int m_skt, m_con; + char m_txbuf[PIPEBUFLEN], m_rxbuf[PIPEBUFLEN]; + int m_ilen, m_rxpos, m_txpos, m_uart_wait; + bool m_started_flag; + + PIPECMDR(const int port) : TESTB() { + m_con = m_skt = -1; + setup_listener(port); + m_rxpos = m_txpos = m_ilen = 0; + m_started_flag = false; + m_uart_wait = 0; + } + + virtual void kill(void) { + // Close any active connection + if (m_con >= 0) close(m_con); + if (m_skt >= 0) close(m_skt); + } + + virtual void tick(void) { + if (m_con < 0) { + // Can we accept a connection? + struct pollfd pb; + + pb.fd = m_skt; + pb.events = POLLIN; + poll(&pb, 1, 0); + + if (pb.revents & POLLIN) { + m_con = accept(m_skt, 0, 0); + + if (m_con < 0) + perror("Accept failed:"); + } + } + + TESTB::m_core->i_rx_stb = 0; + + if (m_uart_wait == 0) { + if (m_ilen > 0) { + // Is there a byte in our buffer somewhere? + TESTB::m_core->i_rx_stb = 1; + TESTB::m_core->i_rx_data = m_rxbuf[m_rxpos++]; + m_ilen--; + } else if (m_con > 0) { + // Is there a byte to be read here? + struct pollfd pb; + pb.fd = m_con; + pb.events = POLLIN; + if (poll(&pb, 1, 0) < 0) + perror("Polling error:"); + if (pb.revents & POLLIN) { + if ((m_ilen =recv(m_con, m_rxbuf, sizeof(m_rxbuf), MSG_DONTWAIT)) > 0) { + m_rxbuf[m_ilen] = '\0'; + if (m_rxbuf[m_ilen-1] == '\n') { + m_rxbuf[m_ilen-1] = '\0'; + printf("< \'%s\'\n", m_rxbuf); + m_rxbuf[m_ilen-1] = '\n'; + } else printf("< \'%s\'\n", m_rxbuf); + TESTB::m_core->i_rx_stb = 1; + TESTB::m_core->i_rx_data = m_rxbuf[0]; + m_rxpos = 1; m_ilen--; + m_started_flag = true; + } else if (m_ilen < 0) { + // An error occurred, close the connection + perror("Read error: "); + fprintf(stderr, "Closing connection\n"); + close(m_con); + m_con = -1; + } else { // the connection closed on us + close(m_con); + m_con = -1; + } + } + } m_uart_wait = (TESTB::m_core->i_rx_stb)?UARTLEN:0; + } else { + // Still working on transmitting a character + m_uart_wait = m_uart_wait - 1; + } + + /* + if (TESTB::m_core->i_rx_stb) { + putchar(TESTB::m_core->i_rx_data); + fflush(stdout); + } + */ + TESTB::tick(); + + if ((TESTB::m_core->o_tx_stb)&&(m_con > 0)) { + m_txbuf[m_txpos++] = TESTB::m_core->o_tx_data; + if ((TESTB::m_core->o_tx_data == '\n')||(m_txpos >= sizeof(m_txbuf))) { + int snt = 0; + snt = send(m_con, m_txbuf, m_txpos, 0); + + m_txbuf[m_txpos] = '\0'; + printf("> %s", m_txbuf); + if (snt < m_txpos) { + fprintf(stderr, "Only sent %d bytes!\n", + snt); + } + m_txpos = 0; + } + } + + /* + if((TESTB::m_core->o_wb_cyc)||(TESTB::m_core->o_wb_stb)){ + printf("BUS: %d,%d,%d %8x %8x\n", + TESTB::m_core->o_wb_cyc, + TESTB::m_core->o_wb_stb, + TESTB::m_core->o_wb_we, + TESTB::m_core->o_wb_addr, + TESTB::m_core->o_wb_data); + } else if (m_started_flag) { + printf("%02x,%c,%d,%d,%02x -> %d,%d,%d, %2x,%2x,%2x\n", + TESTB::m_core->i_rx_data, + (TESTB::m_core->i_rx_stb)?(TESTB::m_core->i_rx_data):' ', + TESTB::m_core->v__DOT__decodewb__DOT__r_valid, + TESTB::m_core->v__DOT__decodewb__DOT__rx_eol, + TESTB::m_core->v__DOT__decodewb__DOT__rx_six_bits, + // + TESTB::m_core->v__DOT__decodewb__DOT__o_rq_strobe, + TESTB::m_core->v__DOT__decodewb__DOT__o_rq_hold, + TESTB::m_core->v__DOT__decodewb__DOT__o_rq_we, + // + TESTB::m_core->v__DOT__decodewb__DOT__state, + TESTB::m_core->v__DOT__decodewb__DOT__nreg, + TESTB::m_core->v__DOT__decodewb__DOT__szreg); + } + */ + } +}; + +#endif Index: trunk/bench/cpp/qspiflashsim.h =================================================================== --- trunk/bench/cpp/qspiflashsim.h (nonexistent) +++ trunk/bench/cpp/qspiflashsim.h (revision 4) @@ -0,0 +1,81 @@ +/////////////////////////////////////////////////////////////////////////// +// +// Filename: spiflashsim.h +// +// Project: Wishbone Controlled Quad SPI Flash Controller +// +// Purpose: This library simulates the operation of a Quad-SPI commanded +// flash, such as the S25FL032P used on the Basys-3 development +// board by Digilent. As such, it is defined by 32 Mbits of +// memory (4 Mbyte). +// +// Creator: Dan Gisselquist +// Gisselquist Technology, LLC +// +/////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2015, Gisselquist Technology, LLC +// +// This program is free software (firmware): you can redistribute it and/or +// modify it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or (at +// your option) any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program. (It's in the $(ROOT)/doc directory, run make with no +// target there if the PDF file isn't present.) If not, see +// for a copy. +// +// License: GPL, v3, as defined and found on www.gnu.org, +// http://www.gnu.org/licenses/gpl.html +// +// +/////////////////////////////////////////////////////////////////////////// +#ifndef QSPIFLASHSIM_H +#define QSPIFLASHSIM_H + +#define QSPIF_WIP_FLAG 0x0001 +#define QSPIF_WEL_FLAG 0x0002 +#define QSPIF_DEEP_POWER_DOWN_FLAG 0x0200 +class QSPIFLASHSIM { + typedef enum { + QSPIF_IDLE, + QSPIF_QUAD_READ_IDLE, + QSPIF_RDSR, + QSPIF_RDCR, + QSPIF_WRSR, + QSPIF_CLSR, + QSPIF_RDID, + QSPIF_RELEASE, + QSPIF_FAST_READ, + QSPIF_QUAD_READ_CMD, + QSPIF_QUAD_READ, + QSPIF_SECTOR_ERASE, + QSPIF_PP, + QSPIF_QPP, + QSPIF_BULK_ERASE, + QSPIF_DEEP_POWER_DOWN, + QSPIF_INVALID + } QSPIF_STATE; + + QSPIF_STATE m_state; + char *m_mem, *m_pmem; + int m_last_sck; + unsigned m_write_count, m_ireg, m_oreg, m_sreg, m_addr, + m_count, m_config, m_mode_byte, m_creg; + bool m_quad_mode, m_debug; + +public: + QSPIFLASHSIM(void); + void load(const char *fname); + void debug(const bool dbg) { m_debug = dbg; } + bool debug(void) const { return m_debug; } + int operator()(const int csn, const int sck, const int dat); +}; + +#endif Index: trunk/bench/cpp/port.h =================================================================== --- trunk/bench/cpp/port.h (nonexistent) +++ trunk/bench/cpp/port.h (revision 4) @@ -0,0 +1 @@ +link ../../sw/port.h \ No newline at end of file

trunk/bench/cpp/port.h Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/cpp/busmaster_tb.cpp =================================================================== --- trunk/bench/cpp/busmaster_tb.cpp (nonexistent) +++ trunk/bench/cpp/busmaster_tb.cpp (revision 4) @@ -0,0 +1,217 @@ +// +// +// Filename: busmaster_tb.cpp +// +// Project: FPGA library development (XuLA2 development board) +// +// Purpose: This is piped version of the testbench for the busmaster +// verilog code. The busmaster code is designed to be a complete +// code set implementing all of the functionality of the XESS +// XuLA2 development board. If done well, the programs talking to +// this one should be able to talk to the board and apply the +// same tests to the board itself. +// +// Creator: Dan Gisselquist +// Gisselquist Tecnology, LLC +// +// Copyright: 2015 +// +// +#include +#include + +#include "verilated.h" +#include "Vbusmaster.h" + +#include "testb.h" +// #include "twoc.h" +#include "pipecmdr.h" +#include "qspiflashsim.h" +#include "sdramsim.h" + +#include "port.h" + +// Add a reset line, since Vbusmaster doesn't have one +class Vbusmasterr : public Vbusmaster { +public: + int i_rst; + virtual ~Vbusmasterr() {} +}; + +// No particular "parameters" need definition or redefinition here. +class BUSMASTER_TB : public PIPECMDR { +public: + unsigned long m_tx_busy_count; + QSPIFLASHSIM m_flash; + SDRAMSIM m_sdram; + unsigned m_last_led; + time_t m_start_time; + + BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) { + m_start_time = time(NULL); + } + + void reset(void) { + m_core->i_clk = 1; + m_core->eval(); + } + + void tick(void) { + if ((m_tickcount & ((1<<28)-1))==0) { + double ticks_per_second = m_tickcount; + ticks_per_second /= (double)(time(NULL) - m_start_time); + printf(" ******** %.6f TICKS PER SECOND\n", + ticks_per_second); + } + + // Set up the bus before any clock tick + m_core->i_clk = 1; + m_core->i_spi_miso = m_flash(m_core->o_sf_cs_n, + m_core->o_spi_sck, + m_core->o_spi_mosi)&0x02; + m_core->i_ram_data = m_sdram(1, + m_core->o_ram_cke, m_core->o_ram_cs_n, + m_core->o_ram_ras_n, m_core->o_ram_cas_n, + m_core->o_ram_we_n, m_core->o_ram_bs, + m_core->o_ram_addr, m_core->o_ram_drive_data, + m_core->o_ram_data); + PIPECMDR::tick(); + + bool writeout = false; + /* + if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__rx_stb) + writeout = true; + else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2iface__DOT__state != m_last_ps2_state) + writeout = true; + else if (m_core->v__DOT__runio__DOT__themouse__DOT__m_state != m_last_mouse_state) + writeout = true; + else if (m_core->i_ps2 != m_last_ps2) + writeout = true; + else if (m_core->o_ps2 != m_last_ops2) + writeout = true; + else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2_perr) + writeout = true; + else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2_ferr) + writeout = true; + */ + // if ((m_core->v__DOT__genbus__DOT__runwb__DOT__o_wb_cyc)||(m_core->v__DOT__bus_cyc)) + // writeout = true; + // else if (m_last_cyc) + // writeout = true; + if ((m_tickcount > 0x5010)&&(m_core->v__DOT__sdram__DOT__r_state != 0)) + writeout = true; + else if ((m_core->v__DOT__dwb_cyc)&&((m_core->v__DOT__wb_stb) + ||(m_core->v__DOT__dwb_stall) + ||(m_core->v__DOT__dwb_ack))) + writeout = true; + else if (m_core->v__DOT__dwb_cyc) + writeout = true; + else if (m_core->v__DOT__sdram__DOT__need_refresh) + writeout = true; + else if ((m_core->v__DOT__wbu_cyc)&&((m_core->v__DOT__wbu_addr == 0x106)||(m_core->v__DOT__wbu_addr == 0x0107))) + writeout = true; + if (m_tickcount < 0x05010) + writeout = false; + if (writeout) { + printf("%08lx:", m_tickcount); + + printf("(%d,%d->%d),(%d,%d->%d)|%c[%08x/%08x]@%08x %d%d%c", + m_core->v__DOT__wbu_cyc, + m_core->v__DOT__dwb_cyc, // was zip_cyc + m_core->v__DOT__wb_cyc, + // + m_core->v__DOT__wbu_stb, + // 0, // m_core->v__DOT__dwb_stb, // was zip_stb + m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl, + m_core->v__DOT__wb_stb, + // + (m_core->v__DOT__wb_we)?'W':'R', + m_core->v__DOT__wb_data, + m_core->v__DOT__dwb_idata, + m_core->v__DOT__wb_addr, + m_core->v__DOT__dwb_ack, + m_core->v__DOT__dwb_stall, + (m_core->v__DOT__wb_err)?'E':'.'); + + printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c", + (m_core->v__DOT__sdram_sel)?'!':' ', + m_core->o_ram_cs_n, m_core->o_ram_ras_n, + m_core->o_ram_cas_n, m_core->o_ram_we_n, + m_core->o_ram_bs, m_core->o_ram_data, + (m_core->o_ram_drive_data)?'D':'-', + m_core->o_ram_addr, + (m_core->o_ram_addr>>10)&1, + m_core->i_ram_data, + (m_core->o_ram_drive_data)?'-':'V'); + + printf(" SD[%d,%d-%3x%d]", + m_core->v__DOT__sdram__DOT__r_state, + m_sdram.pwrup(), + m_core->v__DOT__sdram__DOT__refresh_clk, + m_core->v__DOT__sdram__DOT__need_refresh); + + printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d", + m_core->v__DOT__sdram__DOT__bank_active[0], + m_core->v__DOT__sdram__DOT__bank_row[0], + m_core->v__DOT__sdram__DOT__bank_active[1], + m_core->v__DOT__sdram__DOT__bank_row[1], + m_core->v__DOT__sdram__DOT__bank_active[2], + m_core->v__DOT__sdram__DOT__bank_row[2], + m_core->v__DOT__sdram__DOT__bank_active[3], + m_core->v__DOT__sdram__DOT__bank_row[3], + m_core->v__DOT__sdram__DOT__clocks_til_idle, + m_core->v__DOT__sdram__DOT__r_barrell_ack); + + printf(" %s%s%c[%08x@%06x]", + (m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ", + (m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ", + (m_core->v__DOT__sdram__DOT__r_we)?'W':'R', + (m_core->v__DOT__sdram__DOT__r_data), + (m_core->v__DOT__sdram__DOT__r_addr)); + + printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x", + (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-", + (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-", + (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-", + (m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-", + (m_core->v__DOT__zippy__DOT__cpu_dbg_stall)?"Z":"-", + (m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdvalid)?"D":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"k":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-", + (m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-", + (m_core->v__DOT__zippy__DOT__cmd_addr)); + + printf("\n"); + } + + } + +}; + +BUSMASTER_TB *tb; + +void busmaster_kill(int v) { + tb->kill(); + exit(0); +} + +int main(int argc, char **argv) { + Verilated::commandArgs(argc, argv); + tb = new BUSMASTER_TB; + + // signal(SIGINT, busmaster_kill); + + tb->reset(); + + while(1) + tb->tick(); + + exit(0); +} + Index: trunk/bench/cpp/Makefile =================================================================== --- trunk/bench/cpp/Makefile (nonexistent) +++ trunk/bench/cpp/Makefile (revision 4) @@ -0,0 +1,43 @@ +.PHONY: all +CXX := g++ +OBJDIR := obj-pc +YYMMDD := `date +%Y%m%d` +VOBJDR := ../../rtl/obj_dir +VROOT := /usr/share/verilator +VINC := -I$(VROOT)/include -I$(VOBJDR) +CFLAGS := -c -g -Wall -I. $(VINC) +# +all: $(OBJDIR)/ programs archive + +# GFXFLAGS := `pkg-config gtkmm-3.0 --cflags` +# GFXLIBS := `pkg-config gtkmm-3.0 --cflags --libs` + +.PHONY: programs +programs: busmaster_tb + +.PHONY: clean +clean: + rm -f busmaster_rb $(OBJDIR)/*.o + +$(OBJDIR)/: + @bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi" + +$(OBJDIR)/sdramsim.o: sdramsim.cpp sdramsim.h + $(CXX) $(CFLAGS) $< -o $@ +$(OBJDIR)/qspiflashsim.o: qspiflashsim.cpp qspiflashsim.h + $(CXX) $(CFLAGS) $< -o $@ +$(OBJDIR)/busmaster_tb.o: busmaster_tb.cpp pipecmdr.h sdramsim.h +$(OBJDIR)/busmaster_tb.o: port.h $(VOBJDR)/Vbusmaster.h + $(CXX) $(CFLAGS) busmaster_tb.cpp -o $@ +$(OBJDIR)/verilated.o: $(VROOT)/include/verilated.cpp + $(CXX) $(CFLAGS) $< -o $@ + +busmaster_tb: $(OBJDIR)/qspiflashsim.o +busmaster_tb: $(OBJDIR)/verilated.o +busmaster_tb: $(VOBJDR)/Vbusmaster__ALL.a +busmaster_tb: $(OBJDIR)/busmaster_tb.o $(OBJDIR)/sdramsim.o + $(CXX) -g -o $@ $^ + +.PHONY: archive +archive: + tar --transform s,^,$(YYMMDD)-bench-cpp/, -chjf $(YYMMDD)-bench-cpp.tjz Makefile *.cpp *.h