URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 30 to Rev 31
- ↔ Reverse comparison
Rev 30 → Rev 31
/trunk/bench/cpp/busmaster_tb.cpp
169,7 → 169,7
(m_core->v__DOT__sdram__DOT__r_data), |
(m_core->v__DOT__sdram__DOT__r_addr)); |
|
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x", |
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x", |
(m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-", |
(m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-", |
(m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-", |
179,7 → 179,6
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-", |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-", |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-", |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdvalid)?"D":"-", |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"k":"-", |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-", |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-", |
/trunk/rtl/cpu/zipbones.v
0,0 → 1,195
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipbones.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: In the spirit of keeping the Zip CPU small, this implements a |
// Zip System with no peripherals: Any peripherals you wish will |
// need to be implemented off-module. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
`include "cpudefs.v" |
// |
module zipbones(i_clk, i_rst, |
// Wishbone master interface from the CPU |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, |
// Incoming interrupts |
i_ext_int, |
// Our one outgoing interrupt |
o_ext_int, |
// Wishbone slave interface for debugging purposes |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data |
`ifdef DEBUG_SCOPE |
, o_zip_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
LGICACHE=6, START_HALTED=0, |
AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
// Wishbone master |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
// Incoming interrupts |
input i_ext_int; |
// Outgoing interrupt |
output wire o_ext_int; |
// Wishbone slave |
input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr; |
input [31:0] i_dbg_data; |
output reg o_dbg_ack; |
output wire o_dbg_stall; |
output wire [31:0] o_dbg_data; |
// |
`ifdef DEBUG_SCOPE |
output wire [31:0] o_zip_debug; |
`endif |
|
// |
// |
// |
wire sys_cyc, sys_stb, sys_we; |
wire [4:0] sys_addr; |
wire [(AW-1):0] cpu_addr; |
wire [31:0] sys_data; |
wire sys_ack, sys_stall; |
|
// |
// The external debug interface |
// |
// We offer only a limited interface here, requiring a pre-register |
// write to set the local address. This interface allows access to |
// the Zip System on a debug basis only, and not to the rest of the |
// wishbone bus. Further, to access these registers, the control |
// register must first be accessed to both stop the CPU and to |
// set the following address in question. Hence all accesses require |
// two accesses: write the address to the control register (and halt |
// the CPU if not halted), then read/write the data from the data |
// register. |
// |
wire cpu_break, dbg_cmd_write; |
reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache; |
reg [4:0] cmd_addr; |
wire [3:0] cpu_dbg_cc; |
assign dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr); |
// |
// Always start us off with an initial reset |
// |
initial cmd_reset = 1'b1; |
always @(posedge i_clk) |
cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6])); |
// |
initial cmd_halt = START_HALTED; |
always @(posedge i_clk) |
if (i_rst) |
cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0; |
else if (dbg_cmd_write) |
cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8])); |
else if ((cmd_step)||(cpu_break)) |
cmd_halt <= 1'b1; |
|
initial cmd_clear_pf_cache = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
cmd_clear_pf_cache <= 1'b0; |
else if (dbg_cmd_write) |
cmd_clear_pf_cache <= i_dbg_data[11]; |
else |
cmd_clear_pf_cache <= 1'b0; |
// |
initial cmd_step = 1'b0; |
always @(posedge i_clk) |
cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]); |
// |
initial cmd_addr = 5'h0; |
always @(posedge i_clk) |
if (dbg_cmd_write) |
cmd_addr <= i_dbg_data[4:0]; |
|
wire cpu_reset; |
assign cpu_reset = (cmd_reset)||(i_rst); |
|
wire cpu_halt, cpu_dbg_stall; |
assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step)); |
wire [31:0] cmd_data; |
// Values: |
// 0x0003f -> cmd_addr mask |
// 0x00040 -> reset |
// 0x00080 -> PIC interrrupts enabled |
// 0x00100 -> cmd_step |
// 0x00200 -> cmd_stall |
// 0x00400 -> cmd_halt |
// 0x00800 -> cmd_clear_pf_cache |
// 0x01000 -> cc.sleep |
// 0x02000 -> cc.gie |
// 0x10000 -> External interrupt line is high |
assign cmd_data = { 7'h00, 8'h00, i_ext_int, |
cpu_dbg_cc, |
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0, |
1'b0, cpu_reset, 1'b0, cmd_addr }; |
|
// |
// The CPU itself |
// |
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_dbg_we, |
cpu_op_stall, cpu_pf_stall, cpu_i_count; |
wire [31:0] cpu_data; |
wire [31:0] cpu_dbg_data; |
assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb) |
&&(i_dbg_we)&&(i_dbg_addr)); |
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE) |
thecpu(i_clk, cpu_reset, i_ext_int, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
i_dbg_data, cpu_dbg_stall, cpu_dbg_data, |
cpu_dbg_cc, cpu_break, |
o_wb_cyc, o_wb_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, |
(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)), |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
`ifdef DEBUG_SCOPE |
, o_zip_debug |
`endif |
); |
|
// Return debug response values |
assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data; |
initial o_dbg_ack = 1'b0; |
always @(posedge i_clk) |
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall)); |
assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr); |
|
assign o_ext_int = (cmd_halt) && (~i_wb_stall); |
|
endmodule |
/trunk/rtl/cpu/cpudefs.v
90,7 → 90,9
// mode. |
// |
// |
`ifdef XULA25 |
`define OPT_DIVIDE |
`endif |
// |
// |
// |
188,7 → 190,9
// |
// If you have the fabric to support this option, I recommend including it. |
// |
`ifdef XULA25 |
`define OPT_TRADITIONAL_PFCACHE |
`endif |
// |
// |
// |
262,10 → 266,12
// whether or not the 8 accounting timers are also included. Set these to |
// include the respective peripherals, comment them out not to. |
// |
`ifdef XULA25 |
`define INCLUDE_DMA_CONTROLLER |
`define INCLUDE_ACCOUNTING_COUNTERS |
// |
// |
`define DEBUG_SCOPE |
`endif |
// |
`endif // CPUDEFS_H |
/trunk/rtl/builddate.v
1,10 → 266,12
link ../20160104-build.v |
link ../20160310-build.v |
/trunk/rtl/ioslave.v
82,7 → 82,7
|
// reg [31:0] pwrcount; |
// reg [31:0] rtccount; |
wire [31:0] ictrl_data, gpio_data, date_data; |
wire [31:0] ictrl_data, gpio_data, date_data, timer_data; |
|
reg [31:0] r_wb_data; |
reg r_wb_addr; |
104,9 → 104,10
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we)) |
begin |
casez(i_wb_addr[3:0]) |
4'h02: r_wb_data <= `DATESTAMP; |
4'h03: r_wb_data <= ictrl_data; |
4'h04: r_wb_data <= i_bus_err_addr; |
4'h01: r_wb_data <= `DATESTAMP; |
4'h02: r_wb_data <= ictrl_data; |
4'h03: r_wb_data <= i_bus_err_addr; |
4'h04: r_wb_data <= timer_data; |
4'h05: r_wb_data <= date_data; |
4'h06: r_wb_data <= gpio_data; |
default: r_wb_data <= 32'h0000; |
114,15 → 115,22
end |
end |
|
// The Zip Timer |
wire tm_int, tm_ack, tm_stall; |
ziptimer timer(i_clk, 1'b0, 1'b1, |
(i_wb_cyc),(i_wb_stb)&&(i_wb_addr==5'h04), |
i_wb_we, i_wb_data, |
tm_ack, tm_stall, timer_data, tm_int); |
|
// The interrupt controller |
wire ck_int; |
wire [7:0] interrupt_vector; |
assign interrupt_vector = { |
wire [8:0] interrupt_vector; |
assign interrupt_vector = { tm_int, |
i_uart_tx_int, i_uart_rx_int, i_pwm_int, gpio_int, |
i_scop_int, i_flash_int, ck_int, brd_interrupts[0] }; |
icontrol #(8) intcontroller(i_clk, 1'b0, |
icontrol #(9) intcontroller(i_clk, 1'b0, |
((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we) |
&&(i_wb_addr==5'h3)), i_wb_data, |
&&(i_wb_addr==5'h2)), i_wb_data, |
ictrl_data, interrupt_vector, |
o_interrupt); |
|
/trunk/rtl/busmaster.v
39,10 → 39,16
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// `define XULA25 |
|
`define INCLUDE_ZIPCPU |
// `define NO_ZIP_WBU_DELAY |
`define IMPLEMENT_ONCHIP_RAM |
`ifndef VERILATOR |
`ifndef XULA25 |
`define FANCY_ICAP_ACCESS |
`endif |
`endif |
`define FLASH_ACCESS |
// `define SDCARD_ACCESS // Not built yet ... |
// |
52,7 → 58,10
`define CFG_SCOPE |
`endif |
// `define SDRAM_SCOPE |
`ifdef XULA25 |
`define ZIP_SCOPE |
`endif |
|
module busmaster(i_clk, i_rst, |
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy, |
// The SPI Flash lines |
151,6 → 160,7
wire [31:0] dwb_addr, dwb_odata; |
wire [7:0] w_ints_to_zip_cpu; |
`ifdef INCLUDE_ZIPCPU |
`ifdef XULA25 |
wire [31:0] zip_debug; |
zipsystem #(24'h2000,ZA,8,1,8) |
zippy(i_clk, 1'b0, |
164,6 → 174,19
wbu_data, |
zip_dbg_ack, zip_dbg_stall, zip_dbg_data, |
zip_debug); |
`else |
zipbones #(24'h2000,ZA,8,1) |
zippy(i_clk, 1'b0, |
// Zippys wishbone interface |
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data, |
zip_ack, zip_stall, dwb_idata, zip_err, |
w_interrupt, zip_cpu_int, |
// Debug wishbone interface |
((wbu_cyc)&&(wbu_zip_sel)), |
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0], |
wbu_data, |
zip_dbg_ack, zip_dbg_stall, zip_dbg_data); |
`endif |
generate |
if (ZA < 32) |
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr }; |
304,13 → 327,21
// 001x xxxx Down-sampler taps (64 taps, 2 at a time) |
// 1xxx xxxx Up-sampler taps |
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps |
|
`ifndef SPEEDY_IO |
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop; |
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8); |
assign io_sel = (io_bank)&&(~flctl_sel) |
&&(~pwm_sel)&&(~uart_sel)&&(~scop_sel); |
assign pwm_sel =((io_bank)&&(wb_addr[4: 1]== 4'h4)); |
assign uart_sel =((io_bank)&&((wb_addr[4:1]== 4'h5)||(wb_addr[4:0]==5'h7))); |
assign flctl_sel=((io_bank)&&(wb_addr[4: 2]== 3'h3)); |
assign scop_sel =((io_bank)&&(wb_addr[4: 3]== 2'h3)); |
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop); |
assign io_sel = (io_bank)&&(pre_io); |
assign pre_pwm = (wb_addr[4: 1]== 4'h4); |
assign pwm_sel = (io_bank)&&(pre_pwm); |
assign pre_uart = (wb_addr[4: 1]== 4'h5)||(wb_addr[4:0]==5'h7); |
assign uart_sel = (io_bank)&&(pre_uart); |
assign pre_flctl= (wb_addr[4: 2]== 3'h3); |
assign flctl_sel= (io_bank)&&(pre_flctl); |
assign pre_scop = (wb_addr[4: 3]== 2'h3); |
assign scop_sel = (io_bank)&&(pre_scop); |
assign cfg_sel =((wb_cyc)&&(wb_addr[31: 6]== 26'h05)); |
// zip_sel is not on the bus at this point |
assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01)); |
317,7 → 348,36
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01)); |
assign sdcard_sel=1'b0; |
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01)); |
assign none_sel =((wb_cyc)&&(wb_stb)&&(~(io_sel||flctl_sel||scop_sel||cfg_sel||mem_sel||sdram_sel||sdcard_sel||flash_sel))); |
`else |
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[15:13] } |
|
assign sdram_sel =((wb_cyc)&&(io_vec[4])); |
assign flash_sel =((wb_cyc)&&(io_vec[4:3]==2'b01)); |
assign mem_sel =((wb_cyc)&&(io_vec[4:0]==5'h07)); |
assign cfg_sel =((wb_cyc)&&(io_vec[4:0]==5'h06)); |
assign sdcard_sel=((wb_cyc)&&(io_vec[4:0]==5'h05)); |
assign scop_sel =((wb_cyc)&&(io_vec[4:0]==5'h04)); |
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03)); |
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03)); |
assign puf_sel =((wb_cyc)&&(io_vec[4:0]==5'h02)); |
assign io_sel =((wb_cyc)&&(io_vec[4:0]==5'h01)); |
assign wb_err =((wb_cyc)&&(io_vec[4:0]==5'h00)); |
assign flctl_sel = (puf_sel)&&(wb_addr[2]); |
assign pwm_sel = (puf_sel)&&(wb_addr[2:1]==2'b01); |
assign sdcard_sel=1'b0;//((wb_cyc)&&({wb_addr[23],wb_addr[18]}==2'b01)); |
`endif |
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(~ |
(io_sel |
||uart_sel |
||pwm_sel |
||flctl_sel |
||scop_sel |
||cfg_sel |
||mem_sel |
||sdram_sel |
||sdcard_sel |
||flash_sel))); |
assign many_sel =((wb_cyc)&&(wb_stb)&&( |
{3'h0, io_sel} |
+{3'h0, uart_sel} |
335,6 → 395,7
{3'h0, io_ack} |
+{3'h0, uart_ack} |
+{3'h0, pwm_ack} |
// FLCTL acks through the flash, so one less check here |
+{3'h0, scop_ack} |
+{3'h0, cfg_ack} |
+{3'h0, mem_ack} |
355,7 → 416,13
i_gpio, o_gpio, |
bus_err_addr, |
{ uart_tx_int, uart_rx_int, pwm_int, scop_interrupt, |
flash_interrupt, zip_cpu_int }, |
flash_interrupt, |
`ifdef XULA25 |
zip_cpu_int |
`else |
1'b0 |
`endif |
}, |
w_ints_to_zip_cpu, |
w_interrupt); |
// 8684 |
/trunk/doc/wishbone.html
4,10 → 4,11
<TABLE align=center> |
<TR><TH>Wishbone Address</TH><TH align=center>Words</TH><TH align=left>Usage</TH></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0000_xxxx_xxxx</TT></TD><TH align=right>256</TH><TD>Undefined Memory (Bus Error)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_000x</TT></TD><TH align=right>1</TH><TD>(Reserved)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0010</TT></TD><TH align=right>1</TH><TD>Version</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0011</TT></TD><TH align=right>1</TH><TD>JTAG Accessible Interrupt Controller</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0100</TT></TD><TH align=right>1</TH><TD>Bus Error (Includes errors induced from JTAG-wishbone controller)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0000</TT></TD><TH align=right>1</TH><TD>(Reserved)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0001</TT></TD><TH align=right>1</TH><TD>Version</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0010</TT></TD><TH align=right>1</TH><TD>JTAG Accessible Interrupt Controller</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0011</TT></TD><TH align=right>1</TH><TD>Bus Error (Includes errors induced from JTAG-wishbone controller)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0100</TT></TD><TH align=right>1</TH><TD>ZipTimer</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0101</TT></TD><TH align=right>1</TH><TD>RTC Date</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0110</TT></TD><TH align=right>1</TH><TD>GPIO control</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0111</TT></TD><TH align=right>1</TH><TD>UART Control word</TD></TR> |
17,7 → 18,7
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_11xx</TT></TD><TH align=right>4</TH><TD>Flash Control Words</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_0xxx</TT></TD><TH align=right>8</TH><TD>RTC Clock</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_1yyx</TT></TD><TH align=right>2</TH><TD>Scope #Y (0..3)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>?</TH><TD>SD Card Control</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>?</TH><TD>SD Card Control (Not yet implemented)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_0000_0001_01xx_xxxx</TT></TD><TH align=right>32</TH><TD>(ICAPE Access -- not yet proven)</TD></TR> |
<TR><TD align=right><TT>0_0000_0000_001x_xxxx_xxxx_xxxx</TT></TD><TH align=right>8k</TH><TD>On Chip RAM</TD></TR> |
<TR><TD align=right><TT>0_0000_01xx_xxxx_xxxx_xxxx_xxxx</TT></TD><TH align=right>256k</TH><TD>1 MB SPI Flash (256kW)</TD></TR> |
44,6 → 45,10
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1111</TT></TD><TH align=right>1</TH><TD>User Instruction Counter</TD></TR> |
<TR><TD><TT>1100_0000_0000_0000_0000_0000_0001_00xx</TT></TD><TH align=right>1</TH><TD>DMA Controller</TD></TR> |
</TABLE> |
<!-- |
<h3 align=center>Speed-I/O assignments</H3> |
--> |
|
<h1 align=center>Primary (ZipSystem) Interrupt Controller Assignments</H1> |
<TABLE align=center> |
<TR><TD><TH align=right>0</TH><TD>DMA controller</TD></TR> |
84,6 → 89,7
<TR><TD><TH align=right>5</TH><TD>PWM</TD></TR> |
<TR><TD><TH align=right>6</TH><TD>RX UART</TD></TR> |
<TR><TD><TH align=right>7</TH><TD>TX UART</TD></TR> |
<TR><TD><TH align=right>8-14</TH><TD>(Unused / reserved)</TD></TR> |
<TR><TD><TH align=right>8</TH><TD>Bus Timer (A Zip Timer, just on the bus)</TD></TR> |
<TR><TD><TH align=right>9-14</TH><TD>(Unused / reserved)</TD></TR> |
</TABLE> |
</BODY></HTML> |
/trunk/sw/zipdbg.cpp
395,13 → 395,13
|
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s", |
(m_cursor == 26)?">":" ", |
(cc&0x1000)?"FE":"", |
(cc&0x0800)?"DE":"", |
(cc&0x0400)?"BE":"", |
(cc&0x0200)?"TP":"", |
(cc&0x0100)?"IL":"", |
(cc&0x0080)?"BK":"", |
((gie==0)&&(cc&0x0010))?"HLT":""); |
(cc&0x1000)?"FE":"", // Floating point exception |
(cc&0x0800)?"DV":"", // Division by zero |
(cc&0x0400)?"BE":"", // Bus Error |
(cc&0x0200)?"TP":"", // Trap |
(cc&0x0100)?"IL":"", // Illegal instruction |
(cc&0x0080)?"BK":"", // Break |
((gie==0)&&(cc&0x0010))?"HLT":""); // Halted |
mvprintw(ln,54,"%s%s%s%s", |
(cc&8)?"V":" ", |
(cc&4)?"N":" ", |
435,13 → 435,13
cc = m_state.m_uR[14]; |
mvprintw(ln,40, "%suCC :%s%s%s%s%s%s%s", |
(m_cursor == 42)?">":" ", |
(cc&0x1000)?"FE":"", |
(cc&0x0800)?"DE":"", |
(cc&0x0400)?"BE":"", |
(cc&0x0200)?"TP":"", |
(cc&0x0100)?"IL":"", |
(cc&0x0040)?"ST":"", |
((gie)&&(cc&0x0010))?"SL":""); |
(cc&0x1000)?"FE":"", // Floating point Exception |
(cc&0x0800)?"DV":"", // Division by zero |
(cc&0x0400)?"BE":"", // Bus Error |
(cc&0x0200)?"TP":"", // Trap |
(cc&0x0100)?"IL":"", // Illegal instruction |
(cc&0x0040)?"ST":"", // Single-step |
((gie)&&(cc&0x0010))?"SL":""); // Sleep |
mvprintw(ln,54,"%s%s%s%s", |
(cc&8)?"V":" ", |
(cc&4)?"N":" ", |
/trunk/sw/regdefs.cpp
56,12 → 56,17
{ R_GPIO, "GPIO" }, |
{ R_UART_CTRL, "UARTCTRL" }, |
{ R_UART_CTRL, "UART" }, |
{ R_PWM_INTERVAL,"PWMCTRL" }, |
{ R_PWM_INTERVAL,"PWMI" }, |
{ R_PWM_DATA, "PWMDATA" }, |
{ R_PWM_DATA, "PWM" }, |
{ R_PWM_DATA, "PWMAUDIO" }, |
{ R_PWM_DATA, "AUDIO" }, |
{ R_UART_RX, "UART-RX" }, |
{ R_UART_RX, "UARTRX" }, |
{ R_UART_RX, "RX" }, |
{ R_UART_TX, "UART-TX" }, |
{ R_UART_TX, "UARTTX" }, |
{ R_UART_TX, "TX" }, |
// |
{ R_SPIF_EREG, "SPIFEREG" }, |
/trunk/sw/regdefs.h
37,9 → 37,10
// #define R_RESET 0x00000100 |
// #define R_STATUS 0x00000101 |
// #define R_CONTROL 0x00000101 |
#define R_VERSION 0x00000102 |
#define R_ICONTROL 0x00000103 |
#define R_BUSERR 0x00000104 |
#define R_VERSION 0x00000101 |
#define R_ICONTROL 0x00000102 |
#define R_BUSERR 0x00000103 |
#define R_ITIMER 0x00000104 |
#define R_DATE 0x00000105 |
#define R_GPIO 0x00000106 |
#define R_UART_CTRL 0x00000107 |