URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 38 to Rev 39
- ↔ Reverse comparison
Rev 38 → Rev 39
/trunk/rtl/builddate.v
1,?rev1len? → ?rev2line?,?rev2len?
link ../20160310-build.v |
link ../20160315-build.v |
/trunk/rtl/wbsdram.v
461,8 → 461,8
`ifdef VERILATOR |
// While I hate to build something that works one way under Verilator |
// and another way in practice, this really isn't that. The problem |
// Verilator is having is resolved in toplevel.v--one file that |
// Verilator doesn't implement. In toplevel.v, there's not only a |
// \/erilator is having is resolved in toplevel.v---one file that |
// \/erilator doesn't implement. In toplevel.v, there's not only a |
// single clocked latch but two taking place. Here, we replicate one |
// of those. The second takes place (somehow) within the sdramsim.cpp |
// file. |
/trunk/Makefile
32,7 → 32,7
## |
## |
.PHONY: all |
all: datestamp verilated bit |
all: datestamp verilated bit sw |
# Could also depend upon load, if desired, but not necessary |
BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"` |
RTL := `find rtl -name "*.v"` `find rtl -name Makefile` |
46,27 → 46,26
CONSTRAINTS := xula.ucf |
YYMMDD:=`date +%Y%m%d` |
|
datestamp: $(YYMMDD)-build.v |
$(YYMMDD)-build.v: |
-rm -rf 2*-build.v |
perl xilinx/mkdatev.pl > $(YYMMDD)-build.v |
cd rtl; ln -fs ../$(YYMMDD)-build.v builddate.v |
.PHONY: datestamp |
datestamp: |
bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then perl xilinx/mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi' |
bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; ln -fs ../$(YYMMDD)-build.v builddate.v; fi' |
|
.PHONY: archive |
archive: |
tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS) |
|
.PHONY: tare |
tare: |
echo tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS) |
|
.PHONY: verilated |
verilated: |
cd rtl ; make |
cd rtl ; $(MAKE) --no-print-directory |
|
.PHONY: sw |
sw: |
cd sw ; $(MAKE) --no-print-directory |
|
.PHONY: bit |
bit: |
cd xilinx ; make xula.bit |
cd xilinx ; $(MAKE) --no-print-directory xula.bit |
|
.PHONY: load |
load: bit |
78,6 → 77,6
|
.PHONY: timing |
timing: |
cd xilinx ; make timing |
cd xilinx ; $(MAKE) --no-print-directory timing |
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