URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/rtl/wbgpio.v
4,9 → 4,24
// |
// Project: XuLA2 board |
// |
// Purpose: |
// Purpose: This extremely simple GPIO controller, although minimally |
// featured, is designed to control up to sixteen general purpose |
// input and sixteen general purpose output lines of a module from a |
// single address on a 32-bit wishbone bus. |
// |
// Input GPIO values are contained in the top 16-bits. Any change in |
// input values will generate an interrupt. |
// |
// Output GPIO values are contained in the bottom 16-bits. To change an |
// output GPIO value, writes to this port must also set a bit in the |
// upper sixteen bits. Hence, to set GPIO output zero, one would write |
// a 0x010001 to the port, whereas a 0x010000 would clear the bit. This |
// interface makes it possible to change only the bit of interest, without |
// needing to capture and maintain the prior bit values--something that |
// might be difficult from a interrupt context within a CPU. |
// |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/trunk/rtl/Makefile
52,7 → 52,8
wbucompress.v wbudecompress.v wbudeword.v wbuexec.v \ |
wbuidleint.v wbuinput.v wbuoutput.v wbureadcw.v wbusixchar.v \ |
wbutohex.v |
PERIPHERALS: wbgpio.v wbpwmaudio.v rxuart.v txuart.v rtcdate.v rtclight.v |
PERIPHERALS: wbgpio.v wbpwmaudio.v rxuart.v txuart.v uartdev.v \ |
rtcdate.v rtclight.v |
SOURCES := busmaster.v wbscope.v wbsdram.v \ |
ioslave.v rtclight.v rtcdate.v \ |
wbspiflash.v lldspi.v \ |
/trunk/rtl/uartdev.v
4,9 → 4,18
// |
// Project: XuLA2 board |
// |
// Purpose: |
// Purpose: This is a simple wrapper around the txuart and rxuart |
// modules. The purpose is to make both of those modules |
// configurable from a single wishbone address, and capable of receiving |
// (or transmitting) via reads (writes) from two other addresses. |
// |
// It also generates interrupts: a receive interrupt strobe on the clock |
// when data is made available, and a transmit not busy level interrupt |
// which is held high as long as the transmitter is idle. Both should be |
// able to work nicely with the programmable interrupt controllers found |
// in the ZipCPU project. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/trunk/rtl/rxuart.v
1,13 → 1,11
///////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: rxuart.v |
// |
// Project: FPGA library development (Spartan 3E development board) |
// Project: XuLA2 board |
// |
// Purpose: Receive and decode inputs from a single UART line. |
// |
// |
// To interface with this module, connect it to your system clock, |
// pass it the 32 bit setup register (defined below) and the UART |
// input. When data becomes available, the o_wr line will be asserted |
55,22 → 53,32
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity |
// 32'h005161 // For 9600 baud, 8 bit, no parity |
// |
// Creator: Dan Gisselquist |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
// Copyright: 2015 |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
///////////////////////////////////////////////////////////////////////// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This software is the ownership of Gisselquist Technology, LLC, and as |
// such it is proprietary. It is provided without any warrantees, either |
// express or implied, so that it may be tested. Upon completion, I ask |
// that working code be returned and not further distributed beyond those |
// that it is originally offered to. |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// Thank you. |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
|
// States: (@ baud counter == 0) |
// 0 First bit arrives |
/trunk/rtl/txuart.v
1,9 → 1,8
///////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: txuart.v |
// |
// Project: FPGA library development (Spartan 3E development board) |
// Project: XuLA2 board |
// |
// Purpose: Transmit outputs over a single UART line. |
// |
57,22 → 56,33
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity |
// 32'h005161 // For 9600 baud, 8 bit, no parity |
// |
// Creator: Dan Gisselquist |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
// Copyright: 2015 |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
///////////////////////////////////////////////////////////////////////// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This software is the ownership of Gisselquist Technology, LLC, and as |
// such it is proprietary. It is provided without any warrantees, either |
// express or implied, so that it may be tested. Upon completion, I ask |
// that working code be returned and not further distributed beyond those |
// that it is originally offered to. |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// Thank you. |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define TXU_BIT_ZERO 4'h0 |
`define TXU_BIT_ONE 4'h1 |
`define TXU_BIT_TWO 4'h2 |
/trunk/sw/wbsettime.cpp
5,7 → 5,10
// Project: XuLA2 board |
// |
// Purpose: To give a user access, via a command line program, to set the |
// real time clock within the FPGA. |
// real time clock within the FPGA. Note, however, that the RTC |
// clock device only sets the subseconds field when you program it at the |
// top of a minute. This program, therefore, will wait 'til the top of a |
// minute to set the clock. It can be annoying, but ... it works. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
54,10 → 57,8
} |
|
int main(int argc, char **argv) { |
DEVBUS::BUSW v; |
bool set_time = true; |
|
bool set_time = true, read_hack = false; |
|
FPGAOPEN(m_fpga); |
|
signal(SIGSTOP, closeup); |
91,7 → 92,7
sleepv = 59 - tmp->tm_sec; |
then += 60 - tmp->tm_sec; |
tmp = localtime(&then); |
// printf("Sleeping %d seconds (THEN->SEC = %d)\n", sleepv, tmp->tm_sec); |
printf("Sleeping for %d seconds, so as to set time at the top of the minute\n", sleepv); |
} |
|
// printf("ORIGINAL : %02d:%02d:%02d\n", tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
130,18 → 131,8
#endif // R_DATE |
|
now = then; |
} if (read_hack) { |
then = time(NULL) + 5; |
while(time(NULL) < then) |
; |
clockword = m_fpga->readio(R_CLOCK); |
printf("Hack : %08x\n", m_fpga->readio(R_TIMEHACK)); |
printf(" SUBS: %08x:%08x\n", m_fpga->readio(R_HACKHI), m_fpga->readio(R_HACKLO)); |
|
} |
|
if (m_fpga->poll()) |
printf("FPGA was interrupted\n"); |
delete m_fpga; |
} |
|
/trunk/sw/zipdbg.cpp
31,10 → 31,18
/////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
// BUGS: |
// - No ability to verify CPU functionality (3rd party simulator) |
// - No ability to set/clear breakpoints |
// |
// |
// |
#include <stdlib.h> |
#include <signal.h> |
#include <time.h> |
#include <unistd.h> |
#include <string.h> |
|
#include <ctype.h> |
#include <ncurses.h> |
59,18 → 67,103
#define KEY_RETURN 10 |
#define CTRL(X) ((X)&0x01f) |
|
#define MAXERR 1000 // 1k cycles |
class SPARSEMEM { |
public: |
bool m_valid; |
unsigned int m_a, m_d; |
}; |
|
bool gbl_err = false; |
class ZIPSTATE { |
public: |
bool m_valid, m_gie, m_last_pc_valid; |
unsigned int m_sR[16], m_uR[16]; |
unsigned int m_p[20]; |
unsigned int m_last_pc, m_pc, m_sp; |
SPARSEMEM m_smem[5]; |
SPARSEMEM m_imem[5]; |
ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {} |
|
void step(void) { |
m_last_pc_valid = true; |
m_last_pc = m_pc; |
} |
}; |
|
// No particular "parameters" need definition or redefinition here. |
class ZIPPY : public DEVBUS { |
static const int MAXERR; |
typedef DEVBUS::BUSW BUSW; |
DEVBUS *m_fpga; |
int m_cursor; |
ZIPSTATE m_state; |
bool m_user_break, m_show_users_timers; |
public: |
ZIPPY(DEVBUS *fpga) : m_fpga(fpga), m_cursor(0) {} |
ZIPPY(DEVBUS *fpga) : m_fpga(fpga), m_cursor(0), m_user_break(false), |
m_show_users_timers(false) {} |
|
void read_raw_state(void) { |
m_state.m_valid = false; |
for(int i=0; i<16; i++) |
m_state.m_sR[i] = cmd_read(i); |
for(int i=0; i<16; i++) |
m_state.m_uR[i] = cmd_read(i+16); |
for(int i=0; i<20; i++) |
m_state.m_p[i] = cmd_read(i+32); |
|
m_state.m_gie = (m_state.m_sR[14] & 0x020); |
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]); |
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]); |
|
if (m_state.m_last_pc_valid) |
m_state.m_imem[0].m_a = m_state.m_last_pc; |
else |
m_state.m_imem[0].m_a = m_state.m_pc - 1; |
try { |
m_state.m_imem[0].m_d = readio(m_state.m_imem[0].m_a); |
m_state.m_imem[0].m_valid = true; |
} catch(BUSERR be) { |
m_state.m_imem[0].m_valid = false; |
} |
m_state.m_imem[1].m_a = m_state.m_pc; |
try { |
m_state.m_imem[1].m_d = readio(m_state.m_imem[1].m_a); |
m_state.m_imem[1].m_valid = true; |
} catch(BUSERR be) { |
m_state.m_imem[1].m_valid = false; |
} |
|
for(int i=1; i<4; i++) { |
if (!m_state.m_imem[i].m_valid) { |
m_state.m_imem[i+1].m_valid = false; |
m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1; |
continue; |
} |
m_state.m_imem[i+1].m_a = zop_early_branch( |
m_state.m_imem[i].m_a, |
m_state.m_imem[i].m_d); |
try { |
m_state.m_imem[i+1].m_d = readio(m_state.m_imem[i+1].m_a); |
m_state.m_imem[i+1].m_valid = true; |
} catch(BUSERR be) { |
m_state.m_imem[i+1].m_valid = false; |
} |
} |
|
m_state.m_smem[0].m_a = m_state.m_sp; |
for(int i=1; i<5; i++) |
m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1; |
for(int i=0; i<5; i++) { |
try { |
m_state.m_smem[i].m_d = readio(m_state.m_smem[i].m_a); |
m_state.m_smem[i].m_valid = true; |
} catch(BUSERR be) { |
m_state.m_smem[i].m_valid = false; |
} |
} |
m_state.m_valid = true; |
} |
|
void kill(void) { m_fpga->kill(); } |
void close(void) { m_fpga->close(); } |
void writeio(const BUSW a, const BUSW v) { m_fpga->writeio(a, v); } |
91,11 → 184,15
void clear(void) { m_fpga->clear(); } |
|
void reset(void) { writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT); } |
void step(void) { writeio(R_ZIPCTRL, CPU_STEP); } |
void step(void) { writeio(R_ZIPCTRL, CPU_STEP); m_state.step(); } |
void go(void) { writeio(R_ZIPCTRL, CPU_GO); } |
void halt(void) { writeio(R_ZIPCTRL, CPU_HALT); } |
bool stalled(void) { return ((readio(R_ZIPCTRL)&CPU_STALL)==0); } |
|
void show_user_timers(bool v) { |
m_show_users_timers = v; |
} |
|
void showval(int y, int x, const char *lbl, unsigned int v, bool c) { |
if (c) |
mvprintw(y,x, ">%s> 0x%08x<", lbl, v); |
111,57 → 208,102
mvprintw(y, x, " %s: 0x%08x ", n, v); |
} |
|
void showins(int y, const char *lbl, |
const int gie, const unsigned int pc) { |
char line[80]; |
unsigned int v; |
int showins(int y, const char *lbl, const unsigned int pcidx) { |
char la[80], lb[80]; |
int r = y-1; |
|
mvprintw(y, 0, "%s: 0x%08x", lbl, pc); |
mvprintw(y, 0, "%s0x%08x", lbl, m_state.m_imem[pcidx].m_a); |
|
if (gie) attroff(A_BOLD); |
if (m_state.m_gie) attroff(A_BOLD); |
else attron(A_BOLD); |
|
line[0] = '\0'; |
try { |
v= readio(pc); |
zipi_to_string(v, line); |
printw(" 0x%08x", v); |
printw(" %-24s", &line[1]); |
} catch(BUSERR b) { |
printw(" 0x%08x %-24s", b.addr, "(Bus Error)"); |
la[0] = '\0'; |
lb[0] = '\0'; |
if (m_state.m_imem[pcidx].m_valid) { |
zipi_to_string(m_state.m_imem[pcidx].m_d, la, lb); |
printw(" 0x%08x", m_state.m_imem[pcidx].m_d); |
printw(" %-25s", la); |
if (lb[0]) { |
mvprintw(y-1, 0, "%s", lbl); |
mvprintw(y-1, strlen(lbl)+10+3+8+2, "%-25s", lb); |
r--; |
} |
} else { |
printw(" 0x-------- %-25s", "(Bus Error)"); |
} |
attroff(A_BOLD); |
|
return r; |
} |
|
void showstack(int y, const char *lbl, const unsigned int idx) { |
mvprintw(y, 27+26, "%s%08x ", lbl, m_state.m_smem[idx].m_a); |
|
if (m_state.m_gie) attroff(A_BOLD); |
else attron(A_BOLD); |
|
if (m_state.m_smem[idx].m_valid) |
printw("0x%08x", m_state.m_smem[idx].m_d); |
else |
printw("(Bus Err)"); |
attroff(A_BOLD); |
} |
|
unsigned int cmd_read(unsigned int a) { |
int errcount = 0; |
int errcount = 0; |
unsigned int s; |
|
if (gbl_err) |
return 0; |
|
writeio(R_ZIPCTRL, CMD_HALT|(a&0x3f)); |
while(((readio(R_ZIPCTRL) & CPU_STALL) == 0)&&(errcount < MAXERR)) |
while((((s=readio(R_ZIPCTRL))&CPU_STALL)== 0)&&(errcount<MAXERR) |
&&(!m_user_break)) |
errcount++; |
if (errcount < MAXERR) |
return readio(R_ZIPDATA); |
else { |
gbl_err = true; |
return 0; |
if (m_user_break) { |
endwin(); |
exit(EXIT_SUCCESS); |
} else if (errcount >= MAXERR) { |
endwin(); |
printf("ERR: errcount(%d) >= MAXERR on cmd_read(a=%2x)\n", errcount, a); |
printf("ZIPCTRL = 0x%08x", s); |
if ((s & 0x0200)==0) printf(" STALL"); |
if (s & 0x0400) printf(" HALTED"); |
if ((s & 0x03000)==0x01000) |
printf(" SW-HALT"); |
else { |
if (s & 0x01000) printf(" SLEEPING"); |
if (s & 0x02000) printf(" GIE(UsrMode)"); |
} printf("\n"); |
exit(EXIT_FAILURE); |
} |
return readio(R_ZIPDATA); |
} |
|
void cmd_write(unsigned int a, int v) { |
if (gbl_err) |
return; |
int errcount = 0; |
unsigned int s; |
|
int errcount = 0; |
writeio(R_ZIPCTRL, CMD_HALT|(a&0x3f)); |
while(((readio(R_ZIPCTRL) & CPU_STALL) == 0)&&(errcount < MAXERR)) |
while((((s=readio(R_ZIPCTRL))&CPU_STALL)== 0)&&(errcount<MAXERR) |
&&(!m_user_break)) |
errcount++; |
if (errcount < MAXERR) |
writeio(R_ZIPDATA, (unsigned int)v); |
else |
gbl_err = true; |
if (m_user_break) { |
endwin(); |
exit(EXIT_SUCCESS); |
} else if (errcount >= MAXERR) { |
endwin(); |
printf("ERR: errcount(%d) >= MAXERR on cmd_read(a=%2x)\n", errcount, a); |
printf("ZIPCTRL = 0x%08x", s); |
if ((s & 0x0200)==0) printf(" STALL"); |
if (s & 0x0400) printf(" HALTED"); |
if ((s & 0x03000)==0x01000) |
printf(" SW-HALT"); |
else { |
if (s & 0x01000) printf(" SLEEPING"); |
if (s & 0x02000) printf(" GIE(UsrMode)"); |
} printf("\n"); |
exit(EXIT_FAILURE); |
} |
|
writeio(R_ZIPDATA, (unsigned int)v); |
} |
|
void read_state(void) { |
168,6 → 310,8
int ln= 0; |
bool gie; |
|
read_raw_state(); |
|
if (m_cursor < 0) |
m_cursor = 0; |
else if (m_cursor >= 44) |
174,42 → 318,55
m_cursor = 43; |
|
mvprintw(ln,0, "Peripherals"); |
mvprintw(ln,40,"%-40s", "CPU State: "); |
mvprintw(ln,30,"%-50s", "CPU State: "); |
{ |
unsigned int v = readio(R_ZIPCTRL); |
mvprintw(ln,51, ""); |
if (v & 0x010000) |
printw("EXT-INT "); |
mvprintw(ln,41, "0x%08x ", v); |
// if (v & 0x010000) |
// printw("INT "); |
if ((v & 0x003000) == 0x03000) |
printw("Sleeping "); |
else if (v & 0x001000) |
printw("Halted "); |
else if (v & 0x001000) |
printw("Sleeping "); |
else if (v & 0x002000) |
printw("Supervisor Mod "); |
if (v & 0x008000) |
printw("Break-Enabled "); |
if (v & 0x000080) |
printw("PIC Enabled "); |
printw("User Mode "); |
else |
printw("Supervisor mode "); |
if (v& 0x0200) { |
v = m_state.m_sR[15]; |
|
} else printw("Stalled "); |
// if (v & 0x008000) |
// printw("Break-Enabled "); |
// if (v & 0x000080) |
// printw("PIC Enabled "); |
} ln++; |
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0)); |
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1)); |
showval(ln,40, "WBUS", cmd_read(32+ 2), (m_cursor==2)); |
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3)); |
showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0)); |
showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1)); |
showval(ln,40, "WBUS", m_state.m_p[2], (m_cursor==2)); |
showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3)); |
ln++; |
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4)); |
showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5)); |
showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6)); |
showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7)); |
showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4)); |
showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5)); |
showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6)); |
showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7)); |
|
ln++; |
showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8)); |
showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9)); |
showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10)); |
showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11)); |
if (!m_show_users_timers) { |
showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8)); |
showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9)); |
showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10)); |
showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11)); |
} else { |
showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8)); |
showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9)); |
showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10)); |
showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11)); |
} |
|
ln++; |
ln++; |
unsigned int cc = cmd_read(14); |
unsigned int cc = m_state.m_sR[14]; |
gie = (cc & 0x020); |
if (gie) |
attroff(A_BOLD); |
218,35 → 375,39
mvprintw(ln, 0, "Supervisor Registers"); |
ln++; |
|
dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12)); |
dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13)); |
dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14)); |
dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++; |
dispreg(ln, 0, "sR0 ", m_state.m_sR[0], (m_cursor==12)); |
dispreg(ln,20, "sR1 ", m_state.m_sR[1], (m_cursor==13)); |
dispreg(ln,40, "sR2 ", m_state.m_sR[2], (m_cursor==14)); |
dispreg(ln,60, "sR3 ", m_state.m_sR[3], (m_cursor==15)); ln++; |
|
dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16)); |
dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17)); |
dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18)); |
dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++; |
dispreg(ln, 0, "sR4 ", m_state.m_sR[4], (m_cursor==16)); |
dispreg(ln,20, "sR5 ", m_state.m_sR[5], (m_cursor==17)); |
dispreg(ln,40, "sR6 ", m_state.m_sR[6], (m_cursor==18)); |
dispreg(ln,60, "sR7 ", m_state.m_sR[7], (m_cursor==19)); ln++; |
|
dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20)); |
dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21)); |
dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22)); |
dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++; |
dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20)); |
dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21)); |
dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22)); |
dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++; |
|
dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24)); |
dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25)); |
dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24)); |
dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25)); |
|
mvprintw(ln,40, "%csCC :%s%s%s%s%s%s%s%s", |
(m_cursor==26)?'>':' ', |
(cc & 0x100)?"TP":" ", |
(cc & 0x040)?"ST":" ", |
(cc & 0x020)?"IE":" ", |
(cc & 0x010)?"SL":" ", |
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s", |
(m_cursor == 26)?">":" ", |
(cc&0x1000)?"FE":"", |
(cc&0x0800)?"DE":"", |
(cc&0x0400)?"BE":"", |
(cc&0x0200)?"TP":"", |
(cc&0x0100)?"IL":"", |
(cc&0x0080)?"BK":"", |
((gie==0)&&(cc&0x0010))?"HLT":""); |
mvprintw(ln,54,"%s%s%s%s", |
(cc&8)?"V":" ", |
(cc&4)?"N":" ", |
(cc&2)?"C":" ", |
(cc&1)?"Z":" "); |
dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27)); |
dispreg(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27)); |
ln++; |
|
if (gie) |
254,45 → 415,51
else |
attroff(A_BOLD); |
mvprintw(ln, 0, "User Registers"); ln++; |
dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28)); |
dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29)); |
dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30)); |
dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++; |
dispreg(ln, 0, "uR0 ", m_state.m_uR[0], (m_cursor==28)); |
dispreg(ln,20, "uR1 ", m_state.m_uR[1], (m_cursor==29)); |
dispreg(ln,40, "uR2 ", m_state.m_uR[2], (m_cursor==30)); |
dispreg(ln,60, "uR3 ", m_state.m_uR[3], (m_cursor==31)); ln++; |
|
dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32)); |
dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33)); |
dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34)); |
dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++; |
dispreg(ln, 0, "uR4 ", m_state.m_uR[4], (m_cursor==32)); |
dispreg(ln,20, "uR5 ", m_state.m_uR[5], (m_cursor==33)); |
dispreg(ln,40, "uR6 ", m_state.m_uR[6], (m_cursor==34)); |
dispreg(ln,60, "uR7 ", m_state.m_uR[7], (m_cursor==35)); ln++; |
|
dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36)); |
dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37)); |
dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38)); |
dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++; |
dispreg(ln, 0, "uR8 ", m_state.m_uR[8], (m_cursor==36)); |
dispreg(ln,20, "uR9 ", m_state.m_uR[9], (m_cursor==37)); |
dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38)); |
dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++; |
|
dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40)); |
dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41)); |
cc = cmd_read(30); |
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s", |
(m_cursor == 42)?'>':' ', |
(cc&0x100)?"TP":" ", |
(cc&0x040)?"ST":" ", |
(cc&0x020)?"IE":" ", |
(cc&0x010)?"SL":" ", |
dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40)); |
dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41)); |
cc = m_state.m_uR[14]; |
mvprintw(ln,40, "%suCC :%s%s%s%s%s%s%s", |
(m_cursor == 42)?">":" ", |
(cc&0x1000)?"FE":"", |
(cc&0x0800)?"DE":"", |
(cc&0x0400)?"BE":"", |
(cc&0x0200)?"TP":"", |
(cc&0x0100)?"IL":"", |
(cc&0x0040)?"ST":"", |
((gie)&&(cc&0x0010))?"SL":""); |
mvprintw(ln,54,"%s%s%s%s", |
(cc&8)?"V":" ", |
(cc&4)?"N":" ", |
(cc&2)?"C":" ", |
(cc&1)?"Z":" "); |
dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43)); |
dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43)); |
|
attroff(A_BOLD); |
ln+=2; |
ln+=3; |
|
ln+=3; |
BUSW pc = cmd_read((gie)?31:15); |
showins(ln, "I ", gie, pc+2); ln++; |
showins(ln, "Dc", gie, pc+1); ln++; |
showins(ln, "Op", gie, pc ); ln++; |
showins(ln, "Al", gie, pc-1); ln++; |
showins(ln+4, " ", 0); |
{ |
int lclln = ln+3; |
for(int i=1; i<5; i++) |
lclln = showins(lclln, (i==1)?">":" ", i); |
for(int i=0; i<5; i++) |
showstack(ln+i, (i==0)?">":" ", i); |
} |
} |
|
void cursor_up(void) { |
314,6 → 481,8
int cursor(void) { return m_cursor; } |
}; |
|
const int ZIPPY::MAXERR = 100000; |
|
FPGA *m_fpga; |
|
void get_value(ZIPPY *zip) { |
336,6 → 505,8
bool done = false; |
char str[16]; |
int pos = 0; str[pos] = '\0'; |
attron(A_NORMAL | A_UNDERLINE); |
mvprintw(wy, wx, "%-8s", ""); |
while(!done) { |
int chv = getch(); |
switch(chv) { |
396,6 → 567,11
exit(-2); |
} |
|
void stall_screen(void) { |
erase(); |
mvprintw(0,0, "CPU is stalled. (Q to quit)\n"); |
} |
|
int main(int argc, char **argv) { |
// FPGAOPEN(m_fpga); |
ZIPPY *zip; // |
440,6 → 616,8
; |
if (!zip->stalled()) |
zip->read_state(); |
else |
stall_screen(); |
while((!done)&&(!gbl_err)) { |
chv = getch(); |
switch(chv) { |
450,6 → 628,8
break; |
case 'l': case 'L': case CTRL('L'): |
redrawwin(stdscr); |
case 'm': case 'M': |
zip->show_user_timers(false); |
break; |
case 'q': case 'Q': case CTRL('C'): |
case KEY_CANCEL: case KEY_CLOSE: case KEY_EXIT: |
460,10 → 640,14
zip->reset(); |
erase(); |
break; |
case 't': case 'T': |
case 's': case 'S': |
zip->step(); |
zip->read_state(); |
break; |
case 'u': case 'U': |
zip->show_user_timers(true); |
break; |
case '\r': case '\n': |
case KEY_IC: case KEY_ENTER: |
get_value(zip); |
break; |
484,10 → 668,12
; |
} |
|
if ((!done)&&(!gbl_err)) { |
if (zip->stalled()) |
erase(); |
} |
if ((done)||(gbl_err)) |
break; |
else if (zip->stalled()) |
stall_screen(); |
else |
zip->read_state(); |
} |
|
endwin(); |
/trunk/xilinx/Makefile
12,7 → 12,17
## produced via ISE. Still ... for a command line make script, it is a |
## (good) start. |
## |
## Makefile targets: |
## |
## xula.bit The FPGA bitfile or configuration file |
## |
## objdir Makes a directory for temporary build files, which can |
## then be removed later with a clean target. While a |
## great idea in principle, this doesn't work well in |
## practice since Xilinx's ISE never uses it. |
## |
## clean Removes intermediate build files. |
## |
## Creator: Dan Gisselquist, Ph.D. |
## Gisselquist Technology, LLC |
## |
54,7 → 64,8
JTAGBUS := wbufifo.v wbubus.v wbucompactlines.v wbucompress.v \ |
wbudecompress.v wbudeword.v wbuexec.v wbuidleint.v wbuinput.v \ |
wbuoutput.v wbureadcw.v wbusixchar.v wbutohex.v |
PERIPHERALS: wbgpio.v wbpwmaudio.v rxuart.v txuart.v rtcdate.v rtclight.v |
PERIPHERALS: wbgpio.v wbpwmaudio.v rxuart.v txuart.v uartdev.v \ |
rtcdate.v rtclight.v |
CPUSRC := zipsystem.v \ |
busdelay.v wbarbiter.v wbdblpriarb.v \ |
zipcpu.v cpuops.v pfcache.v idecode.v pipemem.v pipefetch.v div.v \ |