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URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

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    /xulalx25soc
    from Rev 60 to Rev 61
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Rev 60 → Rev 61

/trunk/rtl/cpu/div.v
44,6 → 44,10
output reg [(BW-1):0] o_quotient;
output wire [3:0] o_flags;
 
// r_busy is an internal busy register. It will clear one clock
// before we are valid, so it can't be o_busy ...
//
reg r_busy;
reg [(2*BW-2):0] r_divisor;
reg [(BW-1):0] r_dividend;
wire [(BW):0] diff; // , xdiff[(BW-1):0];
50,26 → 54,35
assign diff = r_dividend - r_divisor[(BW-1):0];
// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
 
reg r_sign, pre_sign, r_z, r_c;
reg [(LGBW):0] r_bit;
reg r_sign, pre_sign, r_z, r_c, last_bit;
reg [(LGBW-1):0] r_bit;
 
initial r_busy = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
r_busy <= 1'b0;
else if (i_wr)
r_busy <= 1'b1;
else if ((last_bit)||(o_err))
r_busy <= 1'b0;
 
initial o_busy = 1'b0;
always @(posedge i_clk)
if (i_rst)
o_busy <= 1'b0;
end else if (i_wr)
begin
else if (i_wr)
o_busy <= 1'b1;
end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
else if (((last_bit)||(o_err))&&(~r_sign))
o_busy <= 1'b0;
// else busy is zero and stays at zero
else if (~r_busy)
o_busy <= 1'b0;
 
always @(posedge i_clk)
if ((i_rst)||(i_wr))
o_valid <= 1'b0;
else if (o_busy)
else if (r_busy)
begin
if ((r_bit == 6'h0)||(o_err))
if ((last_bit)||(o_err))
o_valid <= (o_err)||(~r_sign);
end else if (r_sign)
begin
85,12 → 98,26
else if (o_busy)
o_err <= (r_divisor == 0);
 
initial last_bit = 1'b0;
always @(posedge i_clk)
if ((i_wr)||(pre_sign)||(i_rst))
last_bit <= 1'b0;
else if (r_busy)
last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1});
 
always @(posedge i_clk)
// if (i_rst) r_busy <= 1'b0;
// else
if (i_wr)
begin
//
// Set our values upon an initial command. Here's
// where we come in and start.
//
// r_busy <= 1'b1;
//
o_quotient <= 0;
// r_bit <= { 1'b1, {(LGBW){1'b0}} };
r_bit <= { 1'b0, {(LGBW){1'b1}} };
r_bit <= {(LGBW){1'b1}};
r_divisor <= { i_denominator, {(BW-1){1'b0}} };
r_dividend <= i_numerator;
r_sign <= 1'b0;
98,22 → 125,49
r_z <= 1'b1;
end else if (pre_sign)
begin
// r_bit <= r_bit - 1;
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));;
//
// Note that we only come in here, for one clock, if
// our initial value may have been signed. If we are
// doing an unsigned divide, we then skip this step.
//
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
// Negate our dividend if necessary so that it becomes
// a magnitude only value
if (r_dividend[BW-1])
r_dividend <= -r_dividend;
// Do the same with the divisor--rendering it into
// a magnitude only.
if (r_divisor[(2*BW-2)])
r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
//
// We only do this stage for a single clock, so go on
// with the rest of the divide otherwise.
pre_sign <= 1'b0;
end else if (o_busy)
end else if (r_busy)
begin
r_bit <= r_bit + {(LGBW+1){1'b1}}; // r_bit = r_bit - 1;
// While the divide is taking place, we examine each bit
// in turn here.
//
r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1;
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
if (|r_divisor[(2*BW-2):(BW)])
begin
end else if (diff[BW])
begin
//
// diff = r_dividend - r_divisor[(BW-1):0];
//
// If this value was negative, there wasn't
// enough value in the dividend to support
// pulling off a bit. We'll move down a bit
// therefore and try again.
//
end else begin
//
// Put a '1' into our output accumulator.
// Subtract the divisor from the dividend,
// and then move on to the next bit
//
r_dividend <= diff[(BW-1):0];
o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
r_z <= 1'b0;
127,7 → 181,7
// Set Carry on an exact divide
wire w_n;
always @(posedge i_clk)
r_c <= (o_busy)&&((diff == 0)||(r_dividend == 0));
r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
assign w_n = o_quotient[(BW-1)];
 
assign o_flags = { 1'b0, w_n, r_c, r_z };

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