URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/xulalx25soc
- from Rev 88 to Rev 89
- ↔ Reverse comparison
Rev 88 → Rev 89
/trunk/rtl/cpu/zipcpu.v
71,7 → 71,7
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
292,6 → 292,9
`endif |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`else |
wire op_illegal; |
assign op_illegal = 1'b0; |
`endif |
reg op_break; |
wire op_lock; |
347,10 → 350,12
&&(set_cond); |
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these |
wire adf_ce; |
assign adf_ce = (master_ce)&&(~clear_pipeline)&&(opvalid) |
wire adf_ce, adf_ce_unconditional; |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid) |
&&(~opvalid_mem)&&(~mem_rdbusy)&&(~div_busy) |
&&(~fpu_busy)&&(set_cond); |
&&(~fpu_busy); |
assign adf_ce = (adf_ce_unconditional)&&(set_cond); |
|
// |
// |
// PIPELINE STAGE #5 :: Write-back |
461,8 → 466,7
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal)) |
&&(~alu_stall) |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall) |
&&(~clear_pipeline); |
`else |
assign alu_stall = ((~master_ce)&&(opvalid_alu)) |
843,7 → 847,7
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
`endif |
end else if ((clear_pipeline)||(adf_ce)||(mem_ce)) |
end else if ((clear_pipeline)||(adf_ce_unconditional)||(mem_ce)) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
1133,7 → 1137,7
always @(posedge i_clk) |
if (i_rst) |
r_alu_phase <= 1'b0; |
else if ((adf_ce)||(mem_ce)) |
else if ((adf_ce_unconditional)||(mem_ce)) |
r_alu_phase <= op_phase; |
assign alu_phase = r_alu_phase; |
`else |
1141,7 → 1145,7
`endif |
|
always @(posedge i_clk) |
if (adf_ce) |
if (adf_ce_unconditional) |
alu_reg <= opR; |
else if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
1157,10 → 1161,10
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
always @(posedge i_clk) |
if ((adf_ce)||(mem_ce)) |
if ((adf_ce_unconditional)||(mem_ce)) |
alu_gie <= op_gie; |
always @(posedge i_clk) |
if ((adf_ce) |
if ((adf_ce_unconditional) |
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline) |
&&(~mem_stalled))) |
alu_pc <= op_pc; |
1181,7 → 1185,7
always @(posedge i_clk) |
if (i_rst) |
r_alu_pc_valid <= 1'b0; |
else if (adf_ce) // Includes && (~alu_clear_pipeline) |
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline) |
r_alu_pc_valid <= 1'b1; |
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline)) |
r_alu_pc_valid <= 1'b0; |