OpenCores
URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

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    /y80e/trunk/rtl
    from Rev 6 to Rev 8
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Rev 6 → Rev 8

/defines.v
3,7 → 3,7
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** define file to make the code more readable Rev 0.0 06/13/2012 **/
/** define file to make the code more readable Rev 0.0 06/18/2012 **/
/** **/
/*******************************************************************************************/
 
288,6 → 288,7
`define ALUB_DINH 13'h0101 //Select data input register high byte
`define ALUB_IO 13'h0200 //Select i/o address
`define ALUB_TMP 13'h0400 //Select TMP register
`define ALUB_TMPH 13'h0401 //Select TMP register high byte
`define ALUB_PC 13'h1800 //Select PC register
`define ALUB_PCH 13'h1801 //Select PC register high byte
 
/control.v
3,7 → 3,7
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** control module Rev 0.0 06/13/2012 **/
/** control module Rev 0.0 06/18/2012 **/
/** **/
/*******************************************************************************************/
module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
109,7 → 109,7
reg [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
reg [`TTYPE_IDX:0] tran_sel; /* transaction type */
reg [`WREG_IDX:0] wr_addr; /* register write address bus */
 
/*****************************************************************************************/
/* */
/* refresh register control */
474,129 → 474,147
`IF2B: state_nxt = `sDEC2;
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b001000110110,
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b010011100001,
12'b010011100011,
12'b010011100101,
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sADR2;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b001000110xxx,
12'b001000000xxx,
12'b001000001xxx,
12'b001000010xxx,
12'b001000011xxx,
12'b001000100xxx,
12'b001000101xxx,
12'b001000111xxx,
12'b001001xxxxxx,
12'b001010xxxxxx,
12'b001011xxxxxx,
12'b010000100011,
12'b010000101011,
12'b010000xx1001,
12'b010011111001,
12'b010100100011,
12'b010100101011,
12'b010100xx1001,
12'b010111111001,
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
12'b1xxx01001111,
12'b1xxx01010110,
12'b1xxx01010111,
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx0010,
12'b1xxx01xx1010,
12'b1xxx01xx1100: state_nxt = `sIF1B;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b010011100001,
12'b010011100011,
12'b010011100101,
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx0111,
12'b1xxx00xx1111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = `sADR2;
12'b001000000xxx,
12'b001000001xxx,
12'b001000010xxx,
12'b001000011xxx,
12'b001000100xxx,
12'b001000101xxx,
12'b001000110xxx,
12'b001000111xxx,
12'b001001xxxxxx,
12'b001010xxxxxx,
12'b001011xxxxxx,
12'b010000100011,
12'b010000100100,
12'b010000100101,
12'b010000101011,
12'b010000101100,
12'b010000101101,
12'b010000xx1001,
12'b01000110x0xx,12'b01000110x10x,12'b01000110x111,
12'b0100010xx10x,12'b01000110x10x,12'b01000111110x,
12'b010010000100,
12'b010010000101,
12'b010010001100,
12'b010010001101,
12'b010010010100,
12'b010010010101,
12'b010010011100,
12'b010010011101,
12'b010010100100,
12'b010010100101,
12'b010010101100,
12'b010010101101,
12'b010010110100,
12'b010010110101,
12'b010010111100,
12'b010010111101,
12'b010011111001,
12'b010100100011,
12'b010100100100,
12'b010100100101,
12'b010100101011,
12'b010100101100,
12'b010100101101,
12'b010100xx1001,
12'b01010110x0xx,12'b01010110x10x,12'b01010110x111,
12'b0101010xx10x,12'b01010110x10x,12'b01010111110x,
12'b010110000100,
12'b010110000101,
12'b010110001100,
12'b010110001101,
12'b010110010100,
12'b010110010101,
12'b010110011100,
12'b010110011101,
12'b010110100100,
12'b010110100101,
12'b010110101100,
12'b010110101101,
12'b010110110100,
12'b010110110101,
12'b010110111100,
12'b010110111101,
12'b010111111001,
12'b1xxx00xxx100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
12'b1xxx01001111,
12'b1xxx01010110,
12'b1xxx01010111,
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx1100,
12'b1xxx01xx0010,
12'b1xxx01xx1010: state_nxt = `sIF1B;
12'b010011101001,
12'b010111101001,
12'b1xxx01110110: state_nxt = `sPCO;
605,76 → 623,54
end
`OF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011,
12'b000011011011,
12'b010000110100,
12'b010000110101,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010100110100,
12'b010100110101,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100: state_nxt = `sADR1;
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b0000000xx110,12'b00000010x110,12'b000000111110,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110,
12'b0000000xx110,12'b00000010x110,12'b000000111110,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110,
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx01100100: state_nxt = `sIF1A;
12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000000xx0001,
12'b000011000011,
12'b000011001101,
12'b000011xxx010,
12'b000011xxx100,
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110110,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110110,
12'b1xxx01xx0011,
12'b011xxxxxxxxx: state_nxt = `sIF3A; //DD/FD + CB
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000000xx0001,
12'b000011000011,
12'b000011001101,
12'b000011xxx010,
12'b000011xxx100,
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110110,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110110,
12'b1xxx01xx0011,
12'b1xxx01xx1011: state_nxt = `sOF2A;
12'b000000010000,
12'b000000011000: state_nxt = `sPCA;
12'b000000110110: state_nxt = `sWR2A;
default: state_nxt = `sIF3A;
default: state_nxt = `sADR1;
endcase
end
`OF2A: state_nxt = `sOF2B;
711,45 → 707,84
`ADR1: state_nxt = `sADR2;
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010111100001,
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sRD1A;
12'b000000100010,
12'b000011xxx111,
12'b000011xx0101,
12'b010000100010,
12'b010011100101,
12'b010100100010,
12'b010111100101,
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010111100001,
12'b010111100011,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = `sRD1A;
12'b000000100010,
12'b000011xxx111,
12'b000011xx0101,
12'b010000100010,
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010011100101,
12'b010100100010,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b010111100101,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx01100101,
12'b1xxx01100110,
12'b1xxx01xx0011: state_nxt = `sWR1A;
12'b000000000010,
12'b000000010010,
770,19 → 805,38
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: state_nxt = `sBLK1;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sWR1A;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = `sWR1A;
default: state_nxt = `sRD2A;
endcase
end
793,56 → 847,67
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: state_nxt = `sBLK1;
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxxxxx,
12'b000001xxx110,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010110110,
12'b000010110xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b001001xxxxxx,
12'b010000101010,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00xxx000,
12'b1xxx0x110100,
12'b1xxx01xxx000,
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxxxxx,
12'b000001xxx110,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010110110,
12'b000010110xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b001001xxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx00xxx000,
12'b1xxx00xxx100,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b1xxx01xx1011: state_nxt = `sIF1A;
12'b000011001001,
12'b000011xxx000,
858,20 → 923,38
`WR1A: state_nxt = `sWR1B;
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1000x011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: state_nxt = `sIF1A;
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx10110011,
12'b1xxx10111011,
12'b1xxx10110000,
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100: state_nxt = `sIF1A;
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
default: state_nxt = `sWR2A;
endcase
end
878,13 → 961,30
`WR2A: state_nxt = `sWR2B;
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx10110011,
12'b1xxx10111011,
12'b1xxx10110000,
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
default: state_nxt = `sIF1A;
endcase
end
899,7 → 999,7
`PCA: state_nxt = `sPCO;
`PCO: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000001110110: state_nxt = `sHLTA;
12'b000001110110,
12'b1xxx01110110: state_nxt = `sHLTA;
default: state_nxt = `sIF1A;
endcase
928,26 → 1028,54
`IF2B: tran_sel = `TRAN_IF;
`OF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000010000,
12'b000000011000,
12'b000011010011,
12'b000011011011,
12'b010x00110100,
12'b010x00110101,
12'b010x011100xx,
12'b010x0111010x,
12'b010x01110111,
12'b010x010xx110,
12'b010x0110x110,
12'b010x01111110,
12'b010x10000110,
12'b010x10001110,
12'b010x10010110,
12'b010x10011110,
12'b010x10100110,
12'b010x10101110,
12'b010x10110110,
12'b010x10111110: tran_sel = `TRAN_IDL;
12'b000000010000,
12'b000000011000,
12'b000011010011,
12'b000011011011,
12'b010000110001,
12'b010000110100,
12'b010000110101,
12'b010000110111,
12'b010000111110,
12'b010000111111,
12'b010000xx0111,
12'b010000xx1111,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010100110001,
12'b010100110100,
12'b010100110101,
12'b010100110111,
12'b010100111110,
12'b010100111111,
12'b010100xx0111,
12'b010100xx1111,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx01100101,
12'b1xxx01100110: tran_sel = `TRAN_IDL;
12'b000000100000: tran_sel = ( zero_bit) ? `TRAN_IF : `TRAN_IDL;
12'b000000101000: tran_sel = ( !zero_bit) ? `TRAN_IF : `TRAN_IDL;
12'b000000110000: tran_sel = ( carry_bit) ? `TRAN_IF : `TRAN_IDL;
986,28 → 1114,40
`IF3B: tran_sel = `TRAN_MEM;
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011,
12'b000011011011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx01110100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xxx111,
12'b000011xx0001,
12'b000011xx0101,
12'b010011100001,
12'b010011100101,
12'b010111100001,
12'b010111100101,
12'b1xxx01000101,
12'b1xxx01001101: tran_sel = `TRAN_STK;
12'b000011010011,
12'b000011011011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xxx111,
12'b000011xx0001,
12'b000011xx0101,
12'b010011100001,
12'b010011100101,
12'b010111100001,
12'b010111100101,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100101,
12'b1xxx01100110: tran_sel = `TRAN_STK;
default: tran_sel = `TRAN_MEM;
endcase
end
1017,17 → 1157,26
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: tran_sel = `TRAN_IDL;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx01001101: tran_sel = `TRAN_STK;
default: tran_sel = `TRAN_MEM;
endcase
1042,54 → 1191,73
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: tran_sel = `TRAN_IDL;
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxx110,
12'b000010000110,
12'b000010001110,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010101110,
12'b000010110110,
12'b000010111110,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b010000101010,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxx110,
12'b000010000110,
12'b000010001110,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010101110,
12'b000010110110,
12'b000010111110,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = `TRAN_IO;
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = `TRAN_IO;
12'b000011100011,
12'b0001xxxxxxxx,
12'b010011100011,
1099,35 → 1267,72
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10110010,
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10111000,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: tran_sel = `TRAN_IF;
12'b000000100010,
12'b010000100010,
12'b010100100010,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10110000,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
12'b000000100010,
12'b010000100010,
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010100100010,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx01xx0011: tran_sel = `TRAN_MEM;
default: tran_sel = `TRAN_STK;
12'b000011001101,
12'b000011100011,
12'b000011xxx100,
12'b000011xxx111,
12'b000011xx0101,
12'b0001xxxxxxxx,
12'b010011100011,
12'b010011100101,
12'b010111100011,
12'b010111100101,
12'b1xxx01100101,
12'b1xxx01100110: tran_sel = `TRAN_STK;
default: tran_sel = `TRAN_IF;
endcase
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10110010,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10110010,
12'b1xxx11000010,
12'b1xxx11001010,
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10111000,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10110000,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
default: tran_sel = `TRAN_IF;
endcase
end
1273,42 → 1478,67
end
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b010011100101,
12'b010011101001,
12'b010111100101,
12'b010111101001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b1xxx00110100,
12'b1xxx01100111,
12'b010011100101,
12'b010011101001,
12'b010111100101,
12'b010111101001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: add_sel = `ADD_ALU;
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: add_sel = `ADD_ALU8;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx0111,
12'b1xxx00xx1111,
12'b1xxx01100111,
12'b1xxx01101111: add_sel = `ADD_HL;
12'b010011100001,
12'b010011100011,
1352,59 → 1582,88
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011100011,
12'b0001xxxxxxxx,
12'b010000110100,
12'b010000110101,
12'b010011100011,
12'b010100110100,
12'b010100110101,
12'b010111100011,
12'b011x00xxxxxx,
12'b011x1xxxxxxx,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
//12'b1xxx01110100,
12'b000011100011,
12'b0001xxxxxxxx,
12'b010000110100,
12'b010000110101,
12'b010011100011,
12'b010100110100,
12'b010100110101,
12'b010111100011,
12'b011000000110,
12'b011000001110,
12'b011000010110,
12'b011000011110,
12'b011000100110,
12'b011000101110,
12'b011000110110,
12'b011000111110,
12'b011010xxx110,
12'b011011xxx110,
12'b011100000110,
12'b011100001110,
12'b011100010110,
12'b011100011110,
12'b011100100110,
12'b011100101110,
12'b011100110110,
12'b011100111110,
12'b011110xxx110,
12'b011111xxx110,
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: add_sel = `ADD_ALU;
12'b1xxx100xx011: add_sel = `ADD_ALU8;
12'b000000110100,
12'b000000110101,
12'b000000xxx100,
12'b000000xxx101,
12'b001000000110,
12'b001000000xxx,
12'b001000001110,
12'b001000001xxx,
12'b001000010110,
12'b001000010xxx,
12'b001000011110,
12'b001000011xxx,
12'b001000100110,
12'b001000100xxx,
12'b001000101110,
12'b001000101xxx,
12'b001000110110,
12'b001000110xxx,
12'b001000111110,
12'b001000111xxx,
12'b001010xxx110,
12'b001010xxxxxx,
12'b001011xxx110,
12'b001011xxxxxx,
12'b1xxx01100111,
12'b000000110100,
12'b000000110101,
12'b000000xxx100,
12'b000000xxx101,
12'b001000000110,
12'b001000000xxx,
12'b001000001110,
12'b001000001xxx,
12'b001000010110,
12'b001000010xxx,
12'b001000011110,
12'b001000011xxx,
12'b001000100110,
12'b001000100xxx,
12'b001000101110,
12'b001000101xxx,
12'b001000110110,
12'b001000110xxx,
12'b001000111110,
12'b001000111xxx,
12'b001010xxx110,
12'b001010xxxxxx,
12'b001011xxx110,
12'b001011xxxxxx,
12'b1xxx01100111,
12'b1xxx01101111: add_sel = `ADD_HL;
default: add_sel = `ADD_PC;
endcase
1411,35 → 1670,59
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1000x011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: add_sel = `ADD_PC;
12'b1xxx10010010,
12'b1xxx10011010: add_sel = `ADD_ALU8;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100: add_sel = `ADD_PC;
default: add_sel = `ADD_ALU;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: add_sel = `ADD_ALU;
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: add_sel = `ADD_ALU8;
default: add_sel = `ADD_PC;
endcase
end
1544,181 → 1827,146
end
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b010011001011, //DD+CB prefix
12'b010111001011, //FD+CB prefix
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110100,
12'b010000110101,
12'b010000110110,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011101001,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110100,
12'b010100110101,
12'b010100110110,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111101001,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01100100,
12'b1xxx01110100,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx0011,
12'b1xxx01xx1011: pc_sel = `PC_LD;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b0010000000xx,12'b00100000010x,12'b001000000111,
12'b0010000010xx,12'b00100000110x,12'b001000001111,
12'b0010000100xx,12'b00100001010x,12'b001000010111,
12'b0010000110xx,12'b00100001110x,12'b001000011111,
12'b0010001000xx,12'b00100010010x,12'b001000100111,
12'b0010001010xx,12'b00100010110x,12'b001000101111,
12'b0010001100xx,12'b00100011010x,12'b001000110111,
12'b0010001110xx,12'b00100011110x,12'b001000111111,
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111,
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111,
12'b001011xxx0xx,12'b001011xxx10x,12'b001011xxx111,
12'b010000100011,
12'b010000101011,
12'b010000xx1001,
12'b010011111001,
12'b010100100011,
12'b010100101011,
12'b010100xx1001,
12'b010111111001,
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
12'b1xxx01xx1100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
12'b1xxx01001111,
12'b1xxx01010110,
12'b1xxx01010111,
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx0010,
12'b1xxx01xx1010: pc_sel = `PC_NILD;
default: pc_sel = `PC_NUL;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b010011100001,
12'b010011100011,
12'b010011100101,
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx0111,
12'b1xxx00xx1111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01110110,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: pc_sel = `PC_NUL;
12'b010000100001,
12'b010000100010,
12'b010000100110,
12'b010000101010,
12'b010000101110,
12'b010000110001,
12'b010000110100,
12'b010000110101,
12'b010000110110,
12'b010000110111,
12'b010000111110,
12'b010000111111,
12'b010000xx0111,
12'b010000xx1111,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011101001,
12'b010100100001,
12'b010100100010,
12'b010100100110,
12'b010100101010,
12'b010100101110,
12'b010100110001,
12'b010100110100,
12'b010100110101,
12'b010100110110,
12'b010100110111,
12'b010100111110,
12'b010100111111,
12'b010100xx0111,
12'b010100xx1111,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111101001,
12'b010011001011, //DD+CB prefix
12'b010111001011, //FD+CB prefix
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx01100100,
12'b1xxx01100101,
12'b1xxx01100110,
12'b1xxx01110100,
12'b1xxx01xx1011,
12'b1xxx01xx0011: pc_sel = `PC_LD;
default: pc_sel = `PC_NILD;
endcase
end
`OF2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000000xx0001,
12'b000011000011,
12'b000011001101,
12'b000011xxx010,
12'b000011xxx100,
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110110,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110110,
12'b1xxx01xx0011,
12'b1xxx01xx1011: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`IF3A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b01xx11001011: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`OF2A,
`IF3A: pc_sel = `PC_LD;
`RD1B,
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: pc_sel = `PC_INT;
default: pc_sel = `PC_NUL;
endcase
end
`RD2B: pc_sel = `PC_INT;
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
1744,35 → 1992,57
end
`PCO: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011101001,
12'b010011101001,
12'b010111101001,
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: pc_sel = `PC_LD;
12'b000011101001,
12'b010011101001,
12'b010111101001,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx,
12'b1xxx01000101,
12'b1xxx01001101,
12'b0001xxxxxxxx: pc_sel = `PC_LD;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: pc_sel = `PC_NILD2;
12'b1xxx01001101: pc_sel = `PC_LD;
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: pc_sel = `PC_NILD2;
default: pc_sel = `PC_NILD;
endcase
end
1837,18 → 2107,30
`RD1B: di_ctl = `DI_DI0;
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000101010,
12'b000011001001,
12'b010x00101010,
12'b010x11100001,
12'b010x11100011,
12'b000011100011,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx: di_ctl = `DI_DI1;
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010111100001,
12'b010111100011,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011: di_ctl = `DI_DI1;
default: di_ctl = `DI_DI0;
endcase
end
1866,33 → 2148,64
casex (state_reg) //synopsys parallel_case
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
12'b010x11100101,
12'b000011xxx100,
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: do_ctl = `DO_IO;
12'b000011001101,
12'b000011xxx100,
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b010011100101,
12'b010111100101,
12'b1xxx01100101,
12'b1xxx01100110: do_ctl = `DO_MSB;
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: do_ctl = `DO_IO;
default: do_ctl = `DO_LSB;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000100010,
12'b010x00100010,
12'b010x11100011,
12'b000011100011,
12'b000000100010,
12'b000011100011,
12'b010000100010,
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010011100011,
12'b010100100010,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b010111100011,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx01xx0011: do_ctl = `DO_MSB;
12'b000011010011,
12'b1xxx0xxxx001,
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b000011010011,
12'b1xxx00xxx001,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10111011: do_ctl = `DO_IO;
default: do_ctl = `DO_LSB;
endcase
1943,6 → 2256,8
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01xx1010: aluop_sel = `ALUOP_ADC;
12'b1xxx10100100,
12'b1xxx10101100,
12'b010000100011,
12'b010000101011,
12'b010000xx1001,
2058,40 → 2373,63
`IF3A: aluop_sel = `ALUOP_ADS;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx00xxx00x,
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000011010011,
12'b000011011011,
12'b0001xxxxxxxx,
12'b010000100010,
12'b010000101010,
12'b010100100010,
12'b010100101010,
12'b1xxx01100100,
12'b1xxx01110100,
12'b1xxx01xx0011,
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
12'b1xxx01100101,
12'b1xxx01100110: aluop_sel = `ALUOP_ADD;
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000011010011,
12'b000011011011,
12'b0001xxxxxxxx,
12'b010000100010,
12'b010000101010,
12'b010100100010,
12'b010100101010,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100,
12'b1xxx01xx1011,
12'b1xxx01xx0011: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_ADS;
endcase
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10111000,
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
12'b1xxx01100101,
12'b1xxx01100110: aluop_sel = `ALUOP_ADS;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2101,94 → 2439,151
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_ADD;
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010111100001,
12'b010111100011,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011: aluop_sel = `ALUOP_ADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
`RD1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_BAND;
default: aluop_sel = `ALUOP_PASS;
endcase
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10111000,
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011: aluop_sel = `ALUOP_BADD;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11001010: aluop_sel = `ALUOP_ADD;
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000xxx100,
12'b010000110100,
12'b000000110100,
12'b000000xxx100,
12'b010000110100,
12'b010100110100: aluop_sel = `ALUOP_BADD;
12'b0x1x10xxxxxx,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b001010xxx110,
12'b001010xxxxxx,
12'b011010xxx110,
12'b011110xxx110,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
12'b000000xxx101,
12'b010000110101,
12'b000000110101,
12'b000000xxx101,
12'b010000110101,
12'b010100110101: aluop_sel = `ALUOP_BDEC;
12'b0x1x11xxxxxx: aluop_sel = `ALUOP_BOR;
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b001011xxx110,
12'b001011xxxxxx,
12'b011011xxx110,
12'b011111xxx110: aluop_sel = `ALUOP_BOR;
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b0001xxxxxxxx,
12'b010011100011,
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
//12'b1xxx01110100,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b0001xxxxxxxx,
12'b010011100011,
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: aluop_sel = `ALUOP_PASS;
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
2207,12 → 2602,30
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: aluop_sel = `ALUOP_PASS;
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: aluop_sel = `ALUOP_PASS;
12'b1xxx10100100,
12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_ADD;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10011011,
12'b1xxx10010011,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
2220,8 → 2633,13
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011,
12'b1xxx10001011,
12'b1xxx10000011,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
2232,6 → 2650,12
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10101000,
2242,6 → 2666,14
12'b1xxx10111011: aluop_sel = `ALUOP_ADD;
12'b000011xxx111,
12'b0001xxxxxxxx: aluop_sel = `ALUOP_APAS;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
2248,6 → 2680,14
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
2259,8 → 2699,18
default: aluop_sel = `ALUOP_ADD;
endcase
end
`PCA,
`PCO: aluop_sel = `ALUOP_ADD;
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10101000,
2267,8 → 2717,21
12'b1xxx10101010,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
12'b1xxx10111010,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
12'b1xxx00011010,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011: aluop_sel = `ALUOP_ADS;
12'b000010001xxx,
12'b000011001110,
12'b010x10001110: aluop_sel = `ALUOP_BADC;
2276,6 → 2739,8
12'b000011000110,
12'b010x10000110,
12'b1xxx100xx011,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2359,7 → 2824,9
12'b010100100101,
12'b010100101011,
12'b010100101101,
12'b1xxx10101100,
12'b010111100101: alua_sel = `ALUA_M1;
12'b1xxx10100100,
12'b010000100100,
12'b010000101100,
12'b010000100011,
2390,8 → 2857,21
endcase
end
`IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
`ADR1: alua_sel = (page_reg[2]) ? ((page_reg[0]) ? `ALUA_IY : `ALUA_IX) : `ALUA_M1;
`ADR2: alua_sel = `ALUA_M1;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011: alua_sel = `ALUA_M1;
12'b1xxx01100101,
12'b1xxx01100110: alua_sel = `ALUA_M1;
default: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
endcase
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01100101: alua_sel = `ALUA_IX;
12'b1xxx01100110: alua_sel = `ALUA_IY;
default: alua_sel = `ALUA_M1;
endcase
end
`RD1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100001,
2403,12 → 2883,21
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx,
12'b1xxx100x1011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10111000,
12'b1xxx10111010: alua_sel = `ALUA_M1;
12'b0001xxxxxxxx,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
endcase
end
2437,41 → 2926,69
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000100010,
12'b000011100011,
12'b010000100010,
12'b010011100011,
12'b010100100010,
12'b010111100011,
12'b1xxx01xx0011,
12'b1xxx100x0011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10110000,
12'b1xxx10110011: alua_sel = `ALUA_ONE;
default: alua_sel = `ALUA_M1;
12'b000011001101,
12'b000011xxx100,
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b010011100101,
12'b010111100101,
12'b1xxx01100101,
12'b1xxx01100110,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100: alua_sel = `ALUA_ONE;
default: alua_sel = `ALUA_M1;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
12'b1xxx100x1011,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10111000,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
12'b000011xxx111: alua_sel = `ALUA_RST;
default: alua_sel = `ALUA_ONE;
endcase
2478,19 → 2995,38
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
endcase
end
2504,22 → 3040,46
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx100x1011,
12'b1xxx00110010,
12'b1xxx00xx0010,
12'b1xxx01010101: alua_sel = `ALUA_IX;
12'b1xxx00110011,
12'b1xxx00xx0011,
12'b1xxx01010100: alua_sel = `ALUA_IY;
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx100x0011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10110000,
12'b1xxx10110010: alua_sel = `ALUA_ONE;
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110100,
12'b1xxx11000010,
12'b1xxx11000011: alua_sel = `ALUA_ONE;
12'b1xxx01110100: alua_sel = `ALUA_TMP;
default: alua_sel = `ALUA_AA;
endcase
2599,6 → 3159,8
12'b1xxx01001111: alub_sel = `ALUB_AA;
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000100,
12'b1xxx10001100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
2662,6 → 3224,10
12'b0010xxxxx000: alub_sel = `ALUB_BB;
12'b010x0110x001,
12'b1xxx00001100,
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010,
12'b0010xxxxx001: alub_sel = `ALUB_CC;
12'b010x0110x010,
12'b1xxx00010100,
2685,6 → 3251,10
12'b010011100101,
12'b010111100101: alub_sel = `ALUB_SP;
12'b010x00001001: alub_sel = `ALUB_BC;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010,
12'b010x00011001: alub_sel = `ALUB_DE;
12'b010000101001: alub_sel = `ALUB_IX;
12'b010100101001: alub_sel = `ALUB_IY;
2742,7 → 3312,9
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01110100: alub_sel = `ALUB_CC;
12'b000011010011,
12'b000011011011: alub_sel = `ALUB_IO;
12'b000011011011: alub_sel = `ALUB_IO;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_SP;
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
default: alub_sel = `ALUB_DIN;
endcase
2753,6 → 3325,14
12'b000000010010,
12'b000000110010,
12'b000011010011: alub_sel = `ALUB_AA;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
2762,6 → 3342,12
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
2768,17 → 3354,30
12'b1xxx10101001,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000,
12'b1xxx10111001: alub_sel = `ALUB_BC;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_DIN;
12'b010000100010: alub_sel = `ALUB_IX;
12'b010011100101: alub_sel = `ALUB_IXH;
12'b010000111111,
12'b010100111110,
12'b1xxx00111111: alub_sel = `ALUB_IXL;
12'b010100100010: alub_sel = `ALUB_IY;
12'b010111100101: alub_sel = `ALUB_IYH;
12'b010000111110,
12'b010100111111,
12'b1xxx00111110: alub_sel = `ALUB_IYL;
12'b000011xxx111: alub_sel = `ALUB_PCH;
12'b000001xxx000,
12'b010x01110000,
12'b1xxx00000001,
12'b1xxx01000001: alub_sel = `ALUB_BB;
12'b010000001111,
12'b010100001111,
12'b1xxx00001111,
12'b000001xxx001,
12'b010x01110001,
12'b1xxx01110100,
2788,6 → 3387,9
12'b010x01110010,
12'b1xxx00010001,
12'b1xxx01010001: alub_sel = `ALUB_DD;
12'b010000011111,
12'b010100011111,
12'b1xxx00011111,
12'b000001xxx011,
12'b010x01110011,
12'b1xxx00011001,
2796,6 → 3398,9
12'b010x01110100,
12'b1xxx00100001,
12'b1xxx01100001: alub_sel = `ALUB_HH;
12'b010000101111,
12'b010100101111,
12'b1xxx00101111,
12'b000001xxx101,
12'b010x01110101,
12'b1xxx00101001,
2810,21 → 3415,42
12'b000011000101: alub_sel = `ALUB_BB;
12'b000011010101: alub_sel = `ALUB_DD;
12'b000011100101: alub_sel = `ALUB_HH;
12'b000011110101: alub_sel = `ALUB_AA;
12'b000011110101: alub_sel = `ALUB_AA;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_TMP;
default: alub_sel = `ALUB_HL;
endcase
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BC;
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000: alub_sel = `ALUB_DE;
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10101001,
2833,6 → 3459,12
12'b1xxx10110010,
12'b1xxx10111001,
12'b1xxx10111010: alub_sel = `ALUB_HL;
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b000000101010,
12'b0001xxxxxxxx,
12'b010000101010,
2841,9 → 3473,11
default: alub_sel = `ALUB_SP;
endcase
end
`RD1B: alub_sel = `ALUB_DIN;
`RD1B: alub_sel = `ALUB_DIN;
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2850,10 → 3484,24
12'b1xxx10111011: alub_sel = `ALUB_BC;
12'b1xxx01110100,
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000: alub_sel = `ALUB_DE;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010,
12'b001010xxxxxx,
12'b1xxx10100001,
12'b1xxx10100010,
2882,6 → 3530,15
12'b000011100011: alub_sel = `ALUB_HL;
12'b010011100011: alub_sel = `ALUB_IX;
12'b010111100011: alub_sel = `ALUB_IY;
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b000000001010,
12'b000000011010,
12'b000000101010,
2934,10 → 3591,31
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: alub_sel = `ALUB_BB;
12'b1xxx10000100,
12'b1xxx10001100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: alub_sel = `ALUB_BC;
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: alub_sel = `ALUB_CC;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010: alub_sel = `ALUB_DE;
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
2947,6 → 3625,12
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111011: alub_sel = `ALUB_HL;
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b000000100010,
12'b010000100010,
12'b010100100010,
2956,19 → 3640,44
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10010010,
12'b1xxx10011010,
12'b010000001111,
12'b010100001111,
12'b1xxx00001111,
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10110000,
12'b1xxx10111000: alub_sel = `ALUB_BC;
12'b010000011111,
12'b010100011111,
12'b1xxx00011111: alub_sel = `ALUB_DD;
12'b010000101111,
12'b010100101111,
12'b1xxx00101111,
12'b000000100010,
12'b000011100011: alub_sel = `ALUB_HH;
12'b010011100101: alub_sel = `ALUB_IX;
12'b010000111111,
12'b010100111110,
12'b1xxx00111111,
12'b010000100010,
12'b010011100011: alub_sel = `ALUB_IXH;
12'b010111100101: alub_sel = `ALUB_IY;
12'b010000111110,
12'b010100111111,
12'b1xxx00111110,
12'b010100100010,
12'b010111100011: alub_sel = `ALUB_IYH;
12'b1xxx01000011: alub_sel = `ALUB_BC;
2979,15 → 3688,25
12'b000011010101: alub_sel = `ALUB_DE;
12'b000011100101: alub_sel = `ALUB_HL;
12'b000011110101: alub_sel = `ALUB_AF;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_TMP;
default: alub_sel = `ALUB_PC;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: alub_sel = `ALUB_CC;
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: alub_sel = `ALUB_BC;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010: alub_sel = `ALUB_DE;
12'b000011001101,
12'b000011xxx100: alub_sel = `ALUB_DIN;
default: alub_sel = `ALUB_HL;
2995,6 → 3714,14
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3004,6 → 3731,14
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
3021,15 → 3756,31
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10110000,
12'b1xxx10111000: alub_sel = `ALUB_DE;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10101010,
12'b1xxx10111010,
12'b1xxx10100010,
12'b1xxx10110010: alub_sel = `ALUB_HL;
12'b1xxx10110010,
12'b1xxx11000010,
12'b1xxx11001010: alub_sel = `ALUB_HL;
default: alub_sel = `ALUB_DIN;
endcase
end
3076,10 → 3827,26
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: wr_addr = `WREG_HL;
12'b1xxx01100101,
12'b1xxx01100110,
12'b000011xxx111,
12'b000011xx0101,
12'b010011100101,
12'b010111100101: wr_addr = `WREG_SP;
12'b010000110001,
12'b010000110111,
12'b010000111110,
12'b010000111111,
12'b010000xx0111,
12'b010000xx1111,
12'b010100110001,
12'b010100110111,
12'b010100111110,
12'b010100111111,
12'b010100xx0111,
12'b010100xx1111,
12'b000000100010,
12'b000000101010,
12'b010000100010,
3097,6 → 3864,12
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3106,6 → 3879,14
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
3131,6 → 3912,14
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3140,6 → 3929,14
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
3154,14 → 3951,26
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011: wr_addr = `WREG_CC;
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: wr_addr = `WREG_DE;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: wr_addr = `WREG_HL;
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: wr_addr = `WREG_HL;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
3172,9 → 3981,30
12'b1xxx01001101: wr_addr = `WREG_SP;
default: wr_addr = `WREG_NUL;
endcase
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01100101,
12'b1xxx01100110: wr_addr = `WREG_TMP;
default: wr_addr = `WREG_NUL;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: wr_addr = `WREG_BB;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010: wr_addr = `WREG_CC;
12'b1xxx10010100,
12'b1xxx10011100: wr_addr = `WREG_DE;
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
3184,6 → 4014,8
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111011: wr_addr = `WREG_HL;
12'b1xxx01100101,
12'b1xxx01100110,
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
3196,6 → 4028,20
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010: wr_addr = `WREG_CC;
12'b1xxx10010100,
12'b1xxx10011100: wr_addr = `WREG_DE;
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
3248,8 → 4094,6
12'b000011110110,
12'b001000xxx111,
12'b00101xxxx111,
//12'b011x00xxx111,
//12'b011x1xxxx111,
12'b010010000100,
12'b010010000101,
12'b010010000110,
3306,8 → 4150,6
12'b000001000xxx,
12'b001000xxx000,
12'b00101xxxx000,
//12'b011x00xxx000,
// 12'b011x1xxxx000,
12'b010x0100010x,
12'b010x01000110,
12'b1xxx0x000000,
3315,18 → 4157,23
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b010000000111,
12'b010100000111,
12'b1xxx00000111,
12'b1xxx00000010,
12'b1xxx00000011,
12'b000000000001,
12'b00000000x011,
12'b000011000001,
12'b1xxx01001100,
12'b1xxx01001011: wr_addr = `WREG_BC;
12'b1xxx10100100,
12'b1xxx10101100,
12'b00000000110x,
12'b000000001110,
12'b000001001xxx,
12'b001000xxx001,
12'b00101xxxx001,
//12'b011x00xxx001,
//12'b011x1xxxx001,
12'b010x0100110x,
12'b010x01001110,
12'b1xxx100xx011,
3336,11 → 4183,16
12'b000001010xxx,
12'b001000xxx010,
12'b00101xxxx010,
//12'b011x00xxx010,
//12'b011x1xxxx010,
12'b010x0101010x,
12'b010x01010110,
12'b1xxx0x010000: wr_addr = `WREG_DD;
12'b010000010111,
12'b010100010111,
12'b1xxx00010111,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx00010010,
12'b1xxx00010011,
12'b000011010001,
12'b00000001x011,
12'b000000010001,
3356,8 → 4208,6
12'b000001011xxx,
12'b001000xxx011,
12'b00101xxxx011,
//12'b011x00xxx011,
//12'b011x1xxxx011,
12'b010x0101110x,
12'b010x01011110,
12'b1xxx0x011000: wr_addr = `WREG_EE;
3366,10 → 4216,21
12'b000001100xxx,
12'b001000xxx100,
12'b00101xxxx100,
//12'b011x00xxx100,
//12'b011x1xxxx100,
12'b010x01100110,
12'b1xxx0x100000: wr_addr = `WREG_HH;
12'b010000100111,
12'b010100100111,
12'b1xxx00100010,
12'b1xxx00100011,
12'b1xxx00100111,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b000000100001,
12'b000000101010,
12'b00000010x011,
3383,8 → 4244,15
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: wr_addr = `WREG_HL;
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: wr_addr = `WREG_HL;
12'b1xxx01000111: wr_addr = `WREG_II;
12'b010000110111,
12'b010100110001,
12'b1xxx00110111,
12'b1xxx00110010,
12'b1xxx01010100,
12'b010000100001,
12'b010000100011,
12'b010000101010,
3404,6 → 4272,11
12'b0100011010xx,
12'b01000110110x,
12'b010001101111: wr_addr = `WREG_IXL;
12'b010000110001,
12'b010100110111,
12'b1xxx00110110,
12'b1xxx00110011,
12'b1xxx01010101,
12'b010100100001,
12'b010100100011,
12'b010100101010,
3428,8 → 4301,6
12'b000001101xxx,
12'b001000xxx101,
12'b00101xxxx101,
//12'b011x00xxx101,
//12'b011x1xxxx101,
12'b010x01101110,
12'b1xxx0x101000: wr_addr = `WREG_LL;
12'b1xxx01001111: wr_addr = `WREG_RR;
3592,6 → 4463,20
`RD1A,
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3604,6 → 4489,13
default: zflg_en = 1'b0;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: zflg_en = 1'b1;
default: zflg_en = 1'b0;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000110100,
4131,6 → 5023,22
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: nflg_ctl = `NFLG_0;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b000000101111,
12'b000000110101,
12'b000000xxx101,
/top_levl.v
3,7 → 3,7
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** Y80 processor test bench Rev 0.0 06/13/2012 **/
/** Y80e processor test bench Rev 0.0 06/18/2012 **/
/** **/
/*******************************************************************************************/
`timescale 1ns / 10ps /* set time scale */
54,7 → 54,7
reg PAT_DONE; /* pattern done flag */
reg TRIG_INT; /* assert interrupt */
reg TRIG_NMI; /* assert nmi */
reg [2:0] PAT_CNT; /* counter to track patterns */
reg [3:0] PAT_CNT; /* counter to track patterns */
reg [15:0] CMP_ERR_L; /* error counter */
 
reg wait_dly; /* wait request state machine */
340,7 → 340,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
PAT_CNT = 5'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
351,7 → 351,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
PAT_CNT = 5'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
360,7 → 360,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
PAT_CNT = 5'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
369,7 → 369,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
PAT_CNT = 5'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
378,7 → 378,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
PAT_CNT = 5'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
387,7 → 387,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
PAT_CNT = 5'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
396,7 → 396,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
PAT_CNT = 5'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
403,12 → 403,21
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 5'h8;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("ez8_ops.vm", rdmem);
$readmemh("ez8_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_WAIT = 0; /* wait generator on */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
PAT_CNT = 5'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
419,7 → 428,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
PAT_CNT = 5'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
428,7 → 437,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
PAT_CNT = 5'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
437,7 → 446,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
PAT_CNT = 5'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
446,7 → 455,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
PAT_CNT = 5'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
455,7 → 464,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
PAT_CNT = 5'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
464,7 → 473,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
PAT_CNT = 5'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
471,6 → 480,15
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 5'h8;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("ez8_ops.vm", rdmem);
$readmemh("ez8_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_BREQ = 0; /* bus req generator on */
DISABLE_WAIT = 1; /* wait generator off */
477,7 → 495,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
PAT_CNT = 5'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
488,7 → 506,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
PAT_CNT = 5'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
497,7 → 515,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
PAT_CNT = 5'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
506,7 → 524,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
PAT_CNT = 5'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
515,7 → 533,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
PAT_CNT = 5'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
524,7 → 542,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
PAT_CNT = 5'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
533,7 → 551,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
PAT_CNT = 5'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
540,6 → 558,15
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 5'h8;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("ez8_ops.vm", rdmem);
$readmemh("ez8_opsd.vm", wrmem);
wait (PAT_DONE);
 
$stop;
end
 

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