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/trunk/test_sys/rtl/verilog/xilinx_internal_jtag.v
0,0 → 1,438
///////////////////////////////////////////////////////////////////////
//// ////
//// xilinx_internal_jtag.v ////
//// ////
//// ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// //
// This file is a wrapper for the various Xilinx internal BSCAN //
// TAP devices. It is designed to take the place of a separate TAP //
// controller in Xilinx systems, to allow a user to access a CPU //
// debug module (such as that of the OR1200) through the FPGA's //
// dedicated JTAG / configuration port. //
// //
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xilinx_internal_jtag.v,v $
// Revision 1.4 2009-12-28 01:15:28 Nathan
// Removed incorrect duplicate assignment of capture_dr_o in SPARTAN2 TAP, per bug report from Raul Fajardo.
//
// Revision 1.3 2009/06/16 02:54:23 Nathan
// Changed some signal names for better consistency between different hardware modules.
//
// Revision 1.2 2009/05/17 20:54:16 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/18 20:07:32 Nathan
// Changed the directory structure to match existing projects.
//
// Revision 1.4 2008/07/11 08:26:10 Nathan
// Ran through dos2unix
//
// Revision 1.3 2008/07/11 08:25:52 Nathan
// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4.
//
// Revision 1.2 2008/06/09 19:34:14 Nathan
// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools.
//
// Revision 1.1 2008/05/22 19:54:07 Nathan
// Initial version
//
 
 
`include "xilinx_internal_jtag_options.v"
 
// Note that the SPARTAN BSCAN controllers have more than one channel.
// This implementation always uses channel 1, this is not configurable.
// If you want to use another channel, then it is probably because you
// want to attach multiple devices to the BSCAN device, which means
// you'll be making changes to this file anyway.
// Virtex BSCAN devices are instantiated separately for each channel.
// To select something other than the default (1), change the parameter
// "virtex_jtag_chain".
 
 
module xilinx_internal_jtag (
tck_o,
debug_tdo_i,
tdi_o,
test_logic_reset_o,
run_test_idle_o,
shift_dr_o,
capture_dr_o,
pause_dr_o,
update_dr_o,
debug_select_o
);
 
// May be 1, 2, 3, or 4
// Only used for Virtex 4/5 devices
parameter virtex_jtag_chain = 1;
 
input debug_tdo_i;
output tck_o;
output tdi_o;
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output capture_dr_o;
output pause_dr_o;
output update_dr_o;
output debug_select_o;
 
wire debug_tdo_i;
wire tck_o;
wire drck;
wire tdi_o;
wire test_logic_reset_o;
wire run_test_idle_o;
wire shift_dr_o;
wire pause_dr_o;
wire update_dr_o;
wire debug_select_o;
 
 
 
`ifdef SPARTAN2
 
// Note that this version is missing three outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected
// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no
// capture_dr output.
 
reg capture_dr_o;
wire update_bscan;
reg update_out;
 
BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0 ) // Data input for USER2 function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
// On that negative edge, set capture_dr, and it will get registered on the rising
// edge.
always @ (negedge tck_o)
begin
if(debug_select_o && !shift_dr_o)
capture_dr_o <= 1'b1;
else
capture_dr_o <= 1'b0;
end
 
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
 
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
 
assign update_dr_o = update_out;
 
`else
`ifdef SPARTAN3
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
 
wire capture_dr_o;
wire update_bscan;
reg update_out;
 
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2(1'b0) // Data input for USER2 function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
 
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
 
assign update_dr_o = update_out;
 
`else
`ifdef SPARTAN3A
// Note that this version is missing two outputs.
// At least it has a real TCK.
 
wire capture_dr_o;
 
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK1(), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TCK(tck_o), // TCK output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.TMS(), // TMS output from TAP controller
.UPDATE(update_dr_o), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0) // Data input for USER2 function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
`else
`ifdef VIRTEX
 
// Note that this version is missing three outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
 
reg capture_dr_o;
wire update_bscan;
reg update_out;
 
BSCAN_VIRTEX BSCAN_VIRTEX_inst (
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0) // Data input for USER2 function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low)
// On that negative edge, set capture_dr, and it will get registered on the rising
// edge, then de-asserted on the same edge that SHIFT goes high.
always @ (negedge tck_o)
begin
if(debug_select_o && !shift_dr_o)
capture_dr_o <= 1'b1;
else
capture_dr_o <= 1'b0;
end
 
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
 
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
 
assign update_dr_o = update_out;
 
`else
`ifdef VIRTEX2
 
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
 
wire capture_dr_o;
wire update_bscan;
reg update_out;
 
BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0 ) // Data input for USER2 function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
 
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
 
assign update_dr_o = update_out;
 
`else
`ifdef VIRTEX4
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK is only active when USERn is selected.
 
wire capture_dr_o;
wire update_bscan;
reg update_out;
 
BSCAN_VIRTEX4 #(
.JTAG_CHAIN(virtex_jtag_chain)
) BSCAN_VIRTEX4_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK(drck), // Data register output for USER function
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL(debug_select_o), // USER active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO( debug_tdo_i ) // Data input for USER function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
 
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
 
assign update_dr_o = update_out;
 
`else
`ifdef VIRTEX5
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK is only active when USERn is selected.
 
wire capture_dr_o;
wire update_bscan;
reg update_out;
 
BSCAN_VIRTEX5 #(
.JTAG_CHAIN(virtex_jtag_chain)
) BSCAN_VIRTEX5_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK(drck), // Data register output for USER function
.RESET(test_logic_reset), // Reset output from TAP controller
.SEL(debug_select_o), // USER active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO(debug_tdo_i) // Data input for USER function
);
 
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
 
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
 
assign update_dr_o = update_out;
 
 
`endif
`endif
`endif
`endif
`endif
`endif
`endif
 
endmodule
/trunk/test_sys/rtl/verilog/xilinx_internal_jtag_options.v
0,0 → 1,12
 
 
// Xilinx has a different HDL entity for the internal JTAG in each of these.
// How thoughtful.
 
//`define SPARTAN2
//`define SPARTAN3 // This is also used for SPARTAN 3E devices
`define SPARTAN3A
//`define VIRTEX
//`define VIRTEX2 // Also used for the VIRTEX 2P
//`define VIRTEX4
//`define VIRTEX5
/trunk/test_sys/rtl/vhdl/test_sys_top.vhd
0,0 → 1,291
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
 
entity test_sys_top is
Port ( CLK_50M : in STD_LOGIC;
BTN_NORTH : in STD_LOGIC;
BTN_EAST : in STD_LOGIC;
BTN_SOUTH : in STD_LOGIC;
BTN_WEST : in STD_LOGIC;
SW : in STD_LOGIC_VECTOR( 4-1 downto 0 );
LED : out STD_LOGIC_VECTOR( 8-1 downto 0 );
RS232_DCE_RXD : in STD_LOGIC;
RS232_DCE_TXD : out STD_LOGIC
);
end test_sys_top;
 
architecture Behavioral of test_sys_top is
 
constant VPI_TAP : boolean := false;
 
 
component dbg_comm_vpi is
Port(
SYS_CLK : out STD_LOGIC;
SYS_RST : out STD_LOGIC;
P_TMS : out STD_LOGIC;
P_TCK : out STD_LOGIC;
P_TRST : out STD_LOGIC;
P_TDI : out STD_LOGIC;
P_TDO : in STD_LOGIC
);
end component;
signal P_TMS : STD_LOGIC;
signal P_TCK : STD_LOGIC;
signal P_TRST : STD_LOGIC;
signal P_TDI : STD_LOGIC;
signal P_TDO : STD_LOGIC;
 
 
 
component yac_test_soc is
port(
clk_i : in std_logic ;
rst_i : in std_logic ;
tck_i : in std_logic ;
tdi_i : in std_logic ;
tdo_o : out std_logic ;
debug_rst_i : in std_logic ;
shift_dr_i : in std_logic ;
pause_dr_i : in std_logic ;
update_dr_i : in std_logic ;
capture_dr_i : in std_logic ;
debug_select_i : in std_logic;
stx_pad_o : out std_logic ;
srx_pad_i : in std_logic ;
rts_pad_o : out std_logic ;
cts_pad_i : in std_logic ;
dtr_pad_o : out std_logic ;
dsr_pad_i : in std_logic ;
ri_pad_i : in std_logic ;
dcd_pad_i : in std_logic
);
end component yac_test_soc;
 
component tap_top is
port (
 
-- JTAG pads
signal tms_pad_i : in std_logic;
signal tck_pad_i : in std_logic;
signal trstn_pad_i : in std_logic;
signal tdi_pad_i : in std_logic;
signal tdo_pad_o : out std_logic;
signal tdo_padoe_o : out std_logic;
 
-- TAP states
signal test_logic_reset_o : out std_logic;
signal run_test_idle_o : out std_logic;
signal shift_dr_o : out std_logic;
signal pause_dr_o : out std_logic;
signal update_dr_o : out std_logic;
signal capture_dr_o : out std_logic;
 
-- Select signals for boundary scan or mbist
signal extest_select_o : out std_logic;
signal sample_preload_select_o : out std_logic;
signal mbist_select_o : out std_logic;
signal debug_select_o : out std_logic;
 
-- TDO signal that is connected to TDI of sub-modules.
signal tdi_o : out std_logic;
 
-- TDI signals from sub-modules
signal debug_tdo_i : in std_logic; -- from debug module
signal bs_chain_tdo_i : in std_logic; -- from Boundary Scan Chain
signal mbist_tdo_i : in std_logic -- from Mbist Chain
);
end component;
 
component xilinx_internal_jtag is
port(
signal tck_o : out std_logic;
signal debug_tdo_i : in std_logic;
signal tdi_o : out std_logic;
signal test_logic_reset_o : out std_logic;
signal run_test_idle_o : out std_logic;
signal shift_dr_o : out std_logic;
signal capture_dr_o : out std_logic;
signal pause_dr_o : out std_logic;
signal update_dr_o : out std_logic;
signal debug_select_o : out std_logic
);
end component;
 
 
 
signal clk_i : std_logic ;
signal rst_i : std_logic ;
signal n_rst_i : std_logic ;
signal tck_i : std_logic ;
signal tdi_i : std_logic ;
signal tdo_o : std_logic ;
signal shift_dr_i : std_logic ;
signal pause_dr_i : std_logic ;
signal update_dr_i : std_logic ;
signal capture_dr_i : std_logic ;
signal debug_select_i : std_logic ;
signal debug_rst_i : std_logic ;
signal stx_pad_o : std_logic ;
signal srx_pad_i : std_logic ;
signal rts_pad_o : std_logic ;
signal cts_pad_i : std_logic ;
signal dtr_pad_o : std_logic ;
signal dsr_pad_i : std_logic ;
signal ri_pad_i : std_logic ;
signal dcd_pad_i : std_logic ;
signal gnd : std_logic;
 
 
signal VPI_CLK : std_logic;
 
begin
 
gnd <= '0';
srx_pad_i <= RS232_DCE_RXD;
RS232_DCE_TXD <= stx_pad_o;
cts_pad_i <= '0';
dsr_pad_i <= '0';
dcd_pad_i <= '0';
ri_pad_i <= '0';
 
 
-- led_p : process( clk_i )
-- begin
-- if clk_i'event and clk_i='1' then
-- LED <= SW & BTN_NORTH & BTN_EAST & BTN_SOUTH & BTN_WEST;
-- end if;
-- end process;
 
--LED <= SW & BTN_NORTH & BTN_EAST & BTN_SOUTH & BTN_WEST;
LED <= "10101100";
 
 
 
 
 
--
-- Simulation Part:
-- The VPI and Standard JTAG TAP is used
--
VPI_SEL : if VPI_TAP = true generate
 
 
-- clk_i <= CLK_50M;
rst_i <= BTN_SOUTH;
n_rst_i <= not rst_i;
 
--
-- Debug VPI
--
vpi : dbg_comm_vpi
port map(
SYS_CLK => clk_i,
P_TMS => P_TMS ,
P_TCK => P_TCK ,
P_TRST => P_TRST ,
P_TDI => P_TDI ,
P_TDO => P_TDO );
 
--
-- Standard JTAG TAP
--
tap_inst : tap_top
port map(
 
-- JTAG pads: this 6 signals simulates
-- the physical connection to the tap
tms_pad_i => P_TMS,
tck_pad_i => P_TCK,
trstn_pad_i => n_rst_i,
tdi_pad_i => P_TDI,
tdo_pad_o => P_TDO,
tdo_padoe_o => open,
 
-- TAP states
test_logic_reset_o => debug_rst_i,
run_test_idle_o => open,
shift_dr_o => shift_dr_i,
pause_dr_o => pause_dr_i,
update_dr_o => update_dr_i,
capture_dr_o => capture_dr_i,
 
-- Select signals for boundary scan or mbist
extest_select_o => open,
sample_preload_select_o => open,
mbist_select_o => open,
debug_select_o => debug_select_i,
 
-- TDO signal that is connected to TDI of sub-modules.
tdi_o => tdi_i,
 
-- TDI signals from sub-modules
debug_tdo_i => tdo_o,
bs_chain_tdo_i => gnd,
mbist_tdo_i => gnd
);
 
tck_i <= P_TCK;
 
 
 
end generate VPI_SEL;
 
--
-- Synthesis Part:
-- The FPGA internal Xilinx TAP is used
--
NO_VPI_SEL : if VPI_TAP = false generate
 
clk_i <= CLK_50M;
rst_i <= BTN_SOUTH;
n_rst_i <= not rst_i;
 
tap_inst_xilinx : xilinx_internal_jtag
port map(
tck_o => tck_i,
debug_tdo_i => tdo_o,
tdi_o => tdi_i,
test_logic_reset_o => debug_rst_i,
run_test_idle_o => open,
shift_dr_o => shift_dr_i,
capture_dr_o => capture_dr_i,
pause_dr_o => pause_dr_i,
update_dr_o => update_dr_i,
debug_select_o => debug_select_i
);
 
end generate NO_VPI_SEL;
 
 
--
-- The SOC instance
--
top : yac_test_soc
port map(
clk_i => clk_i ,
rst_i => rst_i ,
tck_i => tck_i ,
tdi_i => tdi_i ,
tdo_o => tdo_o ,
debug_rst_i => debug_rst_i ,
shift_dr_i => shift_dr_i ,
pause_dr_i => pause_dr_i ,
update_dr_i => update_dr_i ,
capture_dr_i => capture_dr_i ,
debug_select_i => debug_select_i ,
stx_pad_o => stx_pad_o ,
srx_pad_i => srx_pad_i ,
rts_pad_o => rts_pad_o ,
cts_pad_i => cts_pad_i ,
dtr_pad_o => dtr_pad_o ,
dsr_pad_i => dsr_pad_i ,
ri_pad_i => ri_pad_i ,
dcd_pad_i => dcd_pad_i
);
 
 
end Behavioral;
 
/trunk/test_sys/s3astarter.ucf
0,0 → 1,27
CONFIG VCCAUX = "3.3" ;
CONFIG ENABLE_SUSPEND = "FILTERED" ;
CONFIG POST_CRC = "DISABLE" ;
NET "CLK_50M" LOC = "E12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_50M" ;
OFFSET = OUT 20.000 AFTER "CLK_50M" ;
NET "RS232_DCE_RXD" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
NET "RS232_DCE_TXD" LOC = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
 
NET "BTN_EAST" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
NET "BTN_NORTH" LOC = "T14" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
NET "BTN_SOUTH" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
NET "BTN_WEST" LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
 
NET "SW<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "SW<1>" LOC = "U10" | IOSTANDARD = LVCMOS33 ;
NET "SW<2>" LOC = "U8" | IOSTANDARD = LVCMOS33 ;
NET "SW<3>" LOC = "T9" | IOSTANDARD = LVCMOS33 ;
 
NET "LED<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
/trunk/test_sys/inc.yaml
0,0 → 1,5
SOCM_INCLUDE
v_socm: 0.1.1
dirs:
- soc_maker_lib
- ../
/trunk/test_sys/README.txt
0,0 → 1,34
 
Dependencies:
- SVN / Git
- SOC-Maker
- SCons
- or32 toolchain (compiler, linker, debugger)
- advanced debug bridge software
- Xilinx BSDL files (usually in our xilinx installation)
- Spartan 3an starter kit
(no hard dependenciy, but
the procedure below needs to be adapted)
 
 
 
Do the following to get the test system working:
 
 
 
# replace <Version> in order to match your SOC-Maker version
git clone --branch <Version> https://github.com/feddischson/soc_maker_lib.git
 
 
# create the system
soc_maker test_system.yaml
 
 
# create a Xilinx project file and synthesize all files
# from ./rtl and ./build
 
# program your FPGA
 
# Build the software
# todo ...
 
/trunk/test_sys/test_sys.yaml
0,0 → 1,215
SOCM_SOC
v_socm: 0.1.1
name: YAC Test SOC
description: 'A test system to test the YAC core'
date: 'June 2015'
license: 'LGPL v3'
licensefile: ''
author: 'Christian Haettich'
authormail: 'feddischson@opencores.org'
vccmd: ''
toplevel: yac_test_soc
interfaces:
:clk_ifc: SOCM_IFC
name: clk
dir: 1
ports:
:clk_i: SOCM_PORT
spc_ref: clk
len: 1
id: clk,1
:rst_ifc: SOCM_IFC
name: rst
dir: 1
ports:
:rst_i: SOCM_PORT
spc_ref: rst
len: 1
id: rst,1
:jtag_ifc: SOCM_IFC
name: jtag_tap
dir: 1
ports:
:tck_i: SOCM_PORT
spc_ref: tck
len: 1
:tdi_i: SOCM_PORT
spc_ref: tdi
len: 1
:tdo_o: SOCM_PORT
spc_ref: tdo
len: 1
:debug_rst_i: SOCM_PORT
spc_ref: rst
len: 1
:shift_dr_i: SOCM_PORT
spc_ref: shift
len: 1
:pause_dr_i: SOCM_PORT
spc_ref: pause
len: 1
:update_dr_i: SOCM_PORT
spc_ref: update
len: 1
:capture_dr_i: SOCM_PORT
spc_ref: capture
len: 1
:debug_select_i: SOCM_PORT
spc_ref: select
len: 1
id: jtag_tap,1
:uart_ifc: SOCM_IFC
name: uart
dir: 1
ports:
:stx_pad_o: SOCM_PORT
spc_ref: stx_pad
len: 1
:srx_pad_i: SOCM_PORT
spc_ref: srx_pad
len: 1
:rts_pad_o: SOCM_PORT
spc_ref: rts_pad
len: 1
:cts_pad_i: SOCM_PORT
spc_ref: cts_pad
len: 1
:dtr_pad_o: SOCM_PORT
spc_ref: dtr_pad
len: 1
:dsr_pad_i: SOCM_PORT
spc_ref: dsr_pad
len: 1
:ri_pad_i: SOCM_PORT
spc_ref: ri_pad
len: 1
:dcd_pad_i: SOCM_PORT
spc_ref: dcd_pad
len: 1
id: uart,1
functions: {}
inst_parameters: {}
static_parameters: {}
hdlfiles: {}
id: yac_test_soc,v1
cores:
:cpu: SOCM_INST
params: {}
type: or1200,rel2
:wb_bus: SOCM_INST
type: wb_connect,1
params:
:t0_addr_w: 8
:t0_addr: 0
:t1_addr_w: 8
:t1_addr: 4
:t28c_addr_w: 4
:t28_addr: 9
:t28i_addr_w: 8
:t2_addr: 151
:t3_addr: 146
:t4_addr: 157
:t5_addr: 144
:t6_addr: 148
:t7_addr: 158
:t8_addr: 159
:dbg: SOCM_INST
type: adv_debug_sys,ads_3
params: {}
:ram1: SOCM_INST
type: ram_wb,b3
params:
:mem_size_bytes: 10240
:mem_adr_width: 14
:ram2: SOCM_INST
params:
:mem_size_bytes: 10240
:mem_adr_width: 15
type: ram_wb,b3
:uart: SOCM_INST
type: uart16550,rel4
params:
:uart_data_width: 32
:uart_addr_width: 32
:yac: SOCM_INST
type: yac,v0
params:
:WB_ADR_WIDTH: 32
:N_ENTRIES: 4
:A_WIDTH: 8
:XY_WIDTH: 8
:GUARD_BITS: 2
:RM_GAIN: 3
cons:
:con_main_clk:
:mapping:
- :yac_test_soc: :clk_ifc
- :cpu: :clk
:wb_bus: :clk
:dbg: :cpu0_dbg_clk
:con_main_rst:
:mapping:
- :yac_test_soc: :rst_ifc
- :cpu: :rst
:wb_bus: :rst
:con_jtag_top:
:mapping:
- :yac_test_soc: :jtag_ifc
- :dbg: :jtag
:con_uart_top:
:mapping:
- :yac_test_soc: :uart_ifc
- :uart: :uart_ifc
:con_wb_debug:
:mapping:
- :wb_bus: :i3
- :dbg: :wb_ifc
:con_data:
:mapping:
- :wb_bus: :i4
- :cpu: :wb_data
:con_instruction:
:mapping:
- :wb_bus: :i5
- :cpu: :wb_instruction
:con_ram1:
:mapping:
- :wb_bus: :t0
- :ram1: :wb_ifc
:con_ram2:
:mapping:
- :wb_bus: :t1
- :ram2: :wb_ifc
:con_uart:
:mapping:
- :wb_bus: :t5
- :uart: :wb_ifc
:con_debug:
:mapping:
- :dbg: :cpu0_dbg
- :cpu: :ext_debug
:con_yac:
:mapping:
- :wb_bus: :t8
- :yac: :wb_ifc
static:
:or1200,rel2:
:VCD_DUMP: false
:VERBOSE: false
:ASIC: false
:ASIC_MEM_CHOICE: 0
:ASIC_NO_DC: true
:ASIC_NO_IC: true
:ASIC_NO_DMMU: true
:ASIC_NO_IMMU: true
:ASIC_MUL_CHOICE: 0
:ASIC_IC_CHOICE: 0
:ASIC_DC_CHOICE: 0
:FPGA_MEM_CHOICE: 2
:FPGA_NO_DC: true
:FPGA_NO_IC: true
:FPGA_NO_DMMU: true
:FPGA_NO_IMMU: true
:FPGA_MUL_CHOICE: 1
:FPGA_IC_CHOICE: 0
:FPGA_DC_CHOICE: 0
/trunk/yac.yaml
0,0 → 1,140
SOCM_CORE
v_socm: 0.1.1
name: yac
id: yac,v0
description: 'Yet Another CORDIC Core'
date: '2015'
license: 'LGPL v3'
licensefile: ''
author: 'Christian Haettich'
authormail: 'feddischson@opencores.org'
vccmd: 'git clone https://github.com/feddischson/yac.git'
toplevel: cordic_iterative_wb
interfaces:
:wb_ifc: SOCM_IFC
name: Wishbone IFC
dir: 1
id: wishbone_sl,b3
ports:
:adr_i: SOCM_PORT
len: 32
spc_ref: adr
:bte_i: SOCM_PORT
len: 2
spc_ref: bte
:cti_i: SOCM_PORT
len: 3
spc_ref: cti
:cyc_i: SOCM_PORT
len: 1
spc_ref: cyc
:dat_i: SOCM_PORT
len: 32
spc_ref: dat_o
:sel_i: SOCM_PORT
len: 4
spc_ref: sel
:stb_i: SOCM_PORT
len: 1
spc_ref: stb
:we_i: SOCM_PORT
len: 1
spc_ref: we
:ack_o: SOCM_PORT
len: 1
spc_ref: ack
:dat_o: SOCM_PORT
len: 32
spc_ref: dat_i
:clk_i: SOCM_PORT
len: 1
spc_ref: clk
:rst_i: SOCM_PORT
len: 1
spc_ref: rst
# :irq_ifc: SOCM_IFC
# name: IRQ IFC
# dir: 1
# id: single,1
# ports:
# :irq_o: SOCM_PORT
# len: 1
# spc_ref: single
 
 
functions: {}
inst_parameters:
:WB_ADR_WIDTH: SOCM_PARAM
type: natural
default: 0
min: 0
max: 0
visible: true
editable: false
description: ''
:N_ENTRIES: SOCM_PARAM
type: natural
default: 0
min: 0
max: 0
visible: true
editable: false
description: ''
:A_WIDTH: SOCM_PARAM
type: natural
default: 0
min: 0
max: 0
visible: true
editable: false
description: ''
:XY_WIDTH: SOCM_PARAM
type: natural
default: 0
min: 0
max: 0
visible: true
editable: false
description: ''
:GUARD_BITS: SOCM_PARAM
type: natural
default: 0
min: 0
max: 0
visible: true
editable: false
description: ''
:RM_GAIN: SOCM_PARAM
type: natural
default: 0
min: 0
max: 0
visible: true
editable: false
description: ''
static_parameters: {}
hdlfiles:
cordic_iterative_int: SOCM_HDL_FILE
path: rtl/vhdl/cordic_iterative_int.vhd
use_syn: true
use_sys_sim: true
use_mod_sim: true
type: vhdl
cordic_iterative_pkg: SOCM_HDL_FILE
path: rtl/vhdl/cordic_iterative_pkg.vhd
use_syn: true
use_sys_sim: true
use_mod_sim: true
type: vhdl
cordic_iterative_tb: SOCM_HDL_FILE
path: rtl/vhdl/cordic_iterative_tb.vhd
use_syn: false
use_sys_sim: true
use_mod_sim: true
type: vhdl
cordic_iterative_wb: SOCM_HDL_FILE
path: rtl/vhdl/cordic_iterative_wb.vhd
use_syn: true
use_sys_sim: false
use_mod_sim: false
type: vhdl

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