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Rev 2 → Rev 4

/define.h
0,0 → 1,218
//Jul.11.2004
 
`define LONG_ACCESS 2'b00
`define WORD_ACCESS 2'b01
`define BYTE_ACCESS 2'b10
 
 
 
//Shift
 
//`define SHIFT_NOTHING 2'b00
`define SHIFT_LEFT 2'b01
`define SHIFT_RIGHT_UNSIGNED 2'b10
`define SHIFT_RIGHT_SIGNED 2'b11
 
//ALU
`define ALU_NOTHING 4'b0000
`define ALU_ADD 4'b0001
`define ALU_SUBTRACT 4'b0010
`define ALU_LESS_THAN_UNSIGNED 4'b0101 //Jul.5.2004
`define ALU_LESS_THAN_SIGNED 4'b0100 //Jul.5.2004
`define ALU_OR 4'b0011
`define ALU_AND 4'b0110
`define ALU_XOR 4'b0111
`define ALU_NOR 4'b1000
//`define ALU_NOR 4'b0000 //Jul.6.2004
 
//PC
`define PC_INC 3'b000
`define PC_HOLD 3'b001
`define PC_IMM 3'b010
`define PC_IMM_PLUS 3'b011
`define PC_REG 3'b100
//`define FLAG_SEL 3'b101
`define PC_FLAG_SEL16 3'b101
`define PC_DEC 3'b110
 
//ALU Right SEL
`define Imm_signed 2'b00
`define Imm_unsigned 2'b01
`define A_RIGHT_ERT 2'b10
`define IMM_26_SEL 2'b11
 
//ALU_LEFT_SEL
`define PC_SEL 1'b1
 
//Shift amount Sel
`define A_sel 1'b0
`define Ers_d2_sel
 
//Memory_Signed_extenstion
`define M_unsigned 1'b0
`define M_signed 1'b1
 
//RRegSel
`define MOUT_SEL 2'b00
`define NREG_SEL 2'b01
 
//AREG ALU/MUL_SEL
//2'b00 => ALU_SEL
`define MUL_hi_SEL 2'b10
`define MUL_lo_SEL 2'b11
 
//RF_INPUT SEL
`define RF_ALU_sel 2'b00
`define RF_Shifter_sel 2'b01
`define RF_PC_SEL 2'b010
`define SHIFT16_SEL 2'b11
 
//MUX
//`define STRAIGHT 2'b00
//`define AREG_SEL 2'b01
//`define RREG_SEL 2'b11
 
 
//RF INPUT ADDRESS
`define RF_Ert_sel 2'b00
`define RF_Erd_sel 2'b01
`define RF_R15_SEL 2'b10
`define RF_INTR_SEL 2'b11
 
`define Last_Reg 31
`define Intr_Reg 26 // Jul.7.2004 TRY FOR OS,, Use R26 as Interrput Return address.
//OPCODE
 
`define add 6'b100000
`define addu 6'b100001
`define addi 6'b001000
`define addiu 6'b001001
`define sub 6'b100010
`define subu 6'b100011
`define and 6'b100100
`define andi 6'b001100
`define nor 6'b100111
`define or 6'b100101
`define ori 6'b001101
`define lsl 6'b000000
`define asr 6'b000011
`define lsr 6'b000010
`define sllv 6'b000100
`define srav 6'b000111
`define srlv 6'b000110
`define xor 6'b100110
`define xori 6'b001110
`define lui 6'b001111
`define comp_signed 6'b101010
`define comp_unsigned 6'b101011 //Jun.29.2004
`define comp_im_signed 6'b001010
`define comp_im_unsigned 6'b001011 //Jun.29.2004
`define beq 6'b000100
`define bgtz 6'b000111
`define blez 6'b000110
`define bne 6'b000101
//opecode "000001" => [20:16] Special Opecode
`define bltzal 5'b10000 //unsupported
`define bltz 5'b00000
 
`define bgez 5'b00001
`define bltzall 5'b10010 //unsupprted
`define bltzl 5'b00010 //unsupported
`define bgezall 5'b10011 //unsupported
`define bgezl 5'b00011 //unsupported
 
`define jump 6'b000010
`define jump_and_link_im 6'b000011
`define jump_and_link_register 6'b001001
`define jmp_register 6'b001000
 
//Load Instructions
`define loadbyte_signed 6'b100000
`define loadbyte_unsigned 6'b100100
`define loadword_signed 6'b100001
`define loadword_unsigned 6'b100101
`define loadlong 6'b100011
 
//Store Instructions
`define storebyte 6'b101000
`define storeword 6'b101001
`define storelong 6'b101011
 
//Exception and Interrupt Instructions
`define softwave_interrupt 6'b011010
`define divs 6'b011010
`define divu 6'b011011
`define muls 6'b011000
`define mulu 6'b011001
 
`define mfhi 6'b010000
`define mflo 6'b010010
 
`define MUL_DIV_WORD_ACCESS 1'b1
`define MUL_DIV_BYTE_ACCESS 1'b0
`define MUL_DIV_MUL_SEL 1'b0
 
 
`define mult_nothing 4'b0000
`define mult_read_lo 4'b0000
`define mult_read_hi 4'b0001
`define mult_write_lo 4'b0011
`define mult_write_hi 4'b0100
`define mult_mult 4'b1000
`define mult_signed_mult 4'b1010
`define mult_divide 4'b1100
`define mult_signed_divide 4'b1110
 
`define SHIFT_AMOUNT_IMM_SEL 1'b0
`define SHIFT_AMOUNT_REG_SEL 1'b1
 
 
//`define RAM4K
`define RAM16K
//`define RAM32K
 
 
 
//UART PORT RATE SELECT
`define COUNTER_VALUE1 216 //115.2kbps for clock=50MHz
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
 
 
`define RTL_SIMULATION //comment out for synthesis
`define ALTERA //comment out if XILINX is used
 
//IO Map
// All access must be 32bit word
//3f80 usuall SP address (set by program)
//16KRAM
// 3fc0-3fef : AES reserved
// 3ff0 : debug port
// 3ff4 : debug port long
// 3ff8 : interrupt set address
// 3ffc : uart port
// 3ffc : [7:0] write_port/read_port
// [8] write_busy
// [31:9] :reserved
 
 
 
`define Print_Port_Address 16'h3ff0 //ATMEL Big Endian
`define Print_CAHR_Port_Address 16'h3ff1
`define Print_INT_Port_Address 16'h3ff2 //First ADDRESS
`define Print_LONG_Port_Address 16'h3ff4 //First ADDRESS
 
`define UART_PORT_ADDRESS 16'h3ffc //
`define INTERUPPT_ADDRESS 16'h3ff8 //
/yacc.qws
0,0 → 1,11
[ProjectWorkspace]
ptn_Child1=Frames
ptn_Child2=Workmode
ptn_Child3=ActionPoints
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
[ProjectWorkspace.Workmode]
CurrentWorkmode=0
/fifo512_cyclone.v
0,0 → 1,161
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
 
// ============================================================
// File Name: fifo512_cyclone.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo512_cyclone (
data,
wrreq,
rdreq,
clock,
q,
full,
empty);
 
input [7:0] data;
input wrreq;
input rdreq;
input clock;
output [7:0] q;
output full;
output empty;
 
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire empty = sub_wire0;
wire [7:0] q = sub_wire1[7:0];
wire full = sub_wire2;
 
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.empty (sub_wire0),
.q (sub_wire1),
.full (sub_wire2)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ()
// synopsys translate_on
);
defparam
scfifo_component.lpm_width = 8,
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_widthu = 9,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "OFF";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_wave*.jpg FALSE
/ram4092x8_0.v
0,0 → 1,237
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram4092x8_0.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram4092x8_0 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [11:0] address_a;
input [7:0] data_b;
input [11:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 12,
altsyncram_component.numwords_a = 4096,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 12,
altsyncram_component.numwords_b = 4096,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
`ifdef NO_PLI
altsyncram_component.init_file = "code0.rif"
`else
altsyncram_component.init_file = "code0.hex"
`endif
;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "code0.hex"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "code0.hex"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_wave*.jpg FALSE
/ram4092x8_1.v
0,0 → 1,237
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram4092x8_1.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram4092x8_1 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [11:0] address_a;
input [7:0] data_b;
input [11:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 12,
altsyncram_component.numwords_a = 4096,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 12,
altsyncram_component.numwords_b = 4096,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
`ifdef NO_PLI
altsyncram_component.init_file = "code1.rif"
`else
altsyncram_component.init_file = "code1.hex"
`endif
;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "code1.hex"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "code1.hex"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_wave*.jpg FALSE
/yacc.qpf
0,0 → 1,29
# Copyright (C) 1991-2005 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
 
 
 
QUARTUS_VERSION = "4.2"
DATE = "15:15:55 April 09, 2005"
 
 
# Revisions
 
PROJECT_REVISION = "yacc"
/ram4092x8_1_bb.v
0,0 → 1,169
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram4092x8_1.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
module ram4092x8_1 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [11:0] address_a;
input [7:0] data_b;
input [11:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "code1.hex"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "code1.hex"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_wave*.jpg FALSE
/ram4096x8_2.v
0,0 → 1,237
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram4096x8_2.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram4096x8_2 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [11:0] address_a;
input [7:0] data_b;
input [11:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 12,
altsyncram_component.numwords_a = 4096,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 12,
altsyncram_component.numwords_b = 4096,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
`ifdef NO_PLI
altsyncram_component.init_file = "code2.rif"
`else
altsyncram_component.init_file = "code2.hex"
`endif
;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "code2.hex"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "code2.hex"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_wave*.jpg FALSE
/ram4096x8_3.v
0,0 → 1,237
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram4096x8_3.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram4096x8_3 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [11:0] address_a;
input [7:0] data_b;
input [11:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 12,
altsyncram_component.numwords_a = 4096,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 12,
altsyncram_component.numwords_b = 4096,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
`ifdef NO_PLI
altsyncram_component.init_file = "code3.rif"
`else
altsyncram_component.init_file = "code3.hex"
`endif
;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "code3.hex"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "code3.hex"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_wave*.jpg FALSE
/ram4096x8_3_bb.v
0,0 → 1,169
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram4096x8_3.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
// ************************************************************
 
//Copyright (C) 1991-2005 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
module ram4096x8_3 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [11:0] address_a;
input [7:0] data_b;
input [11:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "code3.hex"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "code3.hex"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_wave*.jpg FALSE
/code0.hex
0,0 → 1,38
:100000003c373c343c343c37ac0014240c000834fe
:1000100034a33440034003403403a0348010241040
:10002000a0033490001000248c003014009000a035
:100030002490001400030030248c00301424a0030a
:1000400000248c0330900010002400a024900014a1
:10005000002403a0302403a0003ca0243c243c3412
:10006000000000000000000024a02404003c032441
:1000700027afafaf0c000c003c0c243c3400100048
:100080003c340000003c2400008c0c003c0c24009c
:10009000000000000000000000000000023c3400ee
:1000a000103c340200003c2400008c0c003c0c246a
:1000b0000000000000000000000000023c340014ba
:1000c0003c3c0c243c3400103c340200003c242610
:1000d00000008c0c000c2400000000000000000058
:1000e000023c3400143c3c0c243c3400103c3402f0
:1000f00000003c2400008c0c003c0c24000000009c
:10010000000000023c340010003c340000003c249d
:1001100000008c0c003c0c240000000000000000db
:1001200000022e102e3c0c242e142e3c3402000013
:100130003c242600008c0c000c2400000000000071
:1001400000022e103c3c0c242e142e3c34020000e5
:100150003c2400008c0c003c0c2400000000000239
:100160002e142e3c340200003c2400008c0c003c79
:100170000c240000000000022e143c3c340200005d
:10018000242600008c0c000c24000000023c2400fb
:10019000008c0c000c240c248f8f8f032727afaf0b
:1001a000afafafaf3c0c243c0c24003c0c26262ef9
:1001b000142424003c3c0c020016020c260c2610d1
:1001c000260000000000006e746574736e7379661b
:1001d000796679747474746e7400657400736e6eed
:1001e0007365666566740074740074766565746e14
:1001f000006574736e73660066007465746f003a10
:10020000206c202064206d6900206c2074732020f5
:10021000756454206720626420766864617572207a
:10022000730a4d2033752074732024690000000088
:1002300000000000000000000000000000000000be
:1002400000000000000000000000000000000000ae
:00000001ff
/code1.hex
0,0 → 1,38
:100000001c9c048405a51dbd808560840000001a29
:100010001b5b1a1b609ae08405e0a40586c084007f
:10002000a6e00282004000036200424000820062bb
:100030008482004000e0008403620042400244e009
:10004000000242e042820040400560a284830060da
:100050006002e0408402e04480024005024807e775
:10006000a8c70009034302c24282a5a16002e04280
:10007000bdbfb1b000800040040084024251401175
:100080000242620005036310434400000400841030
:100090005002500250025002620370032302425188
:1000a0004002422200050363104344000004008420
:1000b000105002500250025002500222024251409f
:1000c00002040084024251400242220005036302fe
:1000d0000243440000000410700343025002430234
:1000e0002202425140020400840242514002422254
:1000f00000050363104344000004008410700343b0
:100100000250022202425140110242620005036382
:100110001043440000040084105002430250025077
:1001200002222240220400842240220242220005b0
:1001300003630202434400000004105002500250c6
:1001400002222240020400842240220242220005b0
:100150000363104344000004008410500250022244
:10016000224022024222000503631043440000049f
:100170000084105002500222224003024222000555
:100180006302024344000000041050022203631182
:100190004344000000040004bfb1b0e0bdbdbfb4e3
:1001a000b3b2b1b004008404008400110024100232
:1001b00040141100131200201114220064004400a6
:1001c00010000000000000697969796574690069b0
:1001d000006f00687977796965006965006574006a
:1001e000696569656f650068650077656c6e65694e
:1001f00000690065006969006f006800776e002083
:10020000626900687200696f006d6900686100745e
:10021000732068707269612053656f736e7420700b
:100220006d0075620d61702074006673000000003f
:1002300000000000000000000000000000000000be
:1002400000000000000000000000000000000000ae
:00000001ff
/code2.hex
0,0 → 1,38
:10000000008800090009003f0018ff00010000ff00
:100010000000007000600060ff0000ff000000ffb3
:10002000000000000000003f000001ff0000000091
:10003000000000ff000000003f000001ff3f000043
:10004000003f000000000000183f1000000000ff0b
:10005000103f0000003f0000300009000009cccc38
:1000600020004818101010100000ffff3000000999
:10007000ff000000008800200000073bc910001aa4
:10008000004b00288100081010000000000008113b
:1000900010101011101010191818181a8805e010f7
:1000a00000553b00288600081010000000000008e2
:1000b00010101110101011101110128800421000b1
:1000c00001000008012c10006bca00288500080000
:1000d0001010000000000019181110101018101155
:1000e0008800421000430000080042100043de0078
:1000f00028840008101000000000000819181110d2
:100100001010118800861000190a5a002881000872
:10011000101000000000000810101910101010102e
:10012000118803004e0000084e0003d117002883f9
:100130000008001010000000000010101010111036
:100140001188030010000008030000104d002881f2
:100150000008101000000000000811101010108896
:1001600000000051850028810008101000000000e8
:100170000008101010101088000000cccc0028805f
:100180000800101000000000001010108800081077
:1001900010000000000000000000000000ff000050
:1001a00000000000000008000008800000080000b7
:1001b000ff0000800000002010008800080008fff9
:1001c000000000000000006e00670076797800668d
:1001d000007200690065006e650067650076650065
:1001e000786e666e756500696500650065006e6e07
:1001f0000067007600787600750072006f65000079
:10020000696f007565006c6e00696f006f6e006845
:10021000610069726173736f7420612d2c686f6c5b
:1002200061006c790a726f740a0069680707070732
:10023000070707070707070707070707070707074e
:100240000707070707070707070700000000000068
:00000001ff
/code3.hex
0,0 → 1,38
:1000000000a0002800340080002afd049d000eff9f
:100010002e00010008000800ff0800ff000301fc9b
:1000200000080000000f00fc000000fc00000000c1
:10003000010000f4000800fffc000000fcfc0008c8
:1000400000fc0008ff00000925f02500010000fb6e
:1000500025f00800fff00800250032090028cccd6b
:10006000211910c2802140233000fff42500082808
:10007000e0181410582545250045fc9aff2b1e4218
:1000800004831910c200b0802100450000450040e3
:100090002380230021c023402380214023f5ff2b10
:1000a00023e68919104200b0802100450000450c6c
:1000b0004021802380230023402100230f3f2b0574
:1000c0003100451831ff2b215f6b19108200b014ed
:1000d0008021004500542040238023c0218021c07e
:1000e000230f3f2b091b0045180f3f2b171b8319ac
:1000f000108200b080210045000045244023802369
:10010000c0218023019f2b20427cc51910c200b062
:10011000802100450000450c402180218021802164
:100120004023e80520004530201fe8b75919104248
:1001300000b014802100450054208021c0230021fc
:100140000023e80862004530e8176462d319108282
:1001500000b0802100450000453c40238021c023a1
:10016000641714eb1f19104200b0802100450000f5
:10017000450c4021c0218023141400cccd1910c29d
:10018000b014802100450054208021402300b0801d
:1001900021004500540d540a1814100820d82420ba
:1001a0001c181410004548004588250023940103bd
:1001b000fb1203250000702540052145a445a8f643
:1001c0000100000000000065006800650074007414
:1001d00000740072006e00656e00686e0065650058
:1001e00074007400726e00726e006c007600006520
:1001f00000680065000065007200650000000000f6
:100200006c6e006e64006c20006c6e007564006f94
:100210006e00736f6d20656e65527273616f6661fb
:100220002e0074200074726500006e00f8f4f0e88f
:10023000e0d8d4ccc4bcb8b0a89c90888074685c6a
:10024000f8b8544c443c342c241c0000000000003e
:00000001ff
/simulation/custom/p_temp001.txt
/simulation/custom/Gate_altera.vtakprj Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/simulation/custom/Gate_altera.vtakprj
simulation/custom/Gate_altera.vtakprj Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: yacc_fpga.qws =================================================================== --- yacc_fpga.qws (nonexistent) +++ yacc_fpga.qws (revision 4) @@ -0,0 +1,12 @@ +[ProjectWorkspace] +ptn_Child1=Frames +ptn_Child2=Workmode +ptn_Child3=ActionPoints +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +[ProjectWorkspace.Workmode] +CurrentWorkmode=0 Index: yacc.map.summary =================================================================== --- yacc.map.summary (nonexistent) +++ yacc.map.summary (revision 4) @@ -0,0 +1,13 @@ +Flow Status : Successful - Thu Apr 14 20:33:08 2005 +Quartus II Version : 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +Revision Name : yacc +Top-level Entity Name : yacc +Family : Cyclone +Device : EP1C12Q240C6 +Timing Models : Final +Met timing requirements : N/A +Total logic elements : 3,666 +Total pins : 53 +Total virtual pins : 0 +Total memory bits : 137,216 +Total PLLs : 0 Index: yacc.flow.rpt =================================================================== --- yacc.flow.rpt (nonexistent) +++ yacc.flow.rpt (revision 4) @@ -0,0 +1,96 @@ +Flow report for yacc +Thu Apr 14 21:02:39 2005 +Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Elapsed Time + 5. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2005 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. + + + ++------------------------------------------------------------------------+ +; Flow Summary ; ++-------------------------+----------------------------------------------+ +; Flow Status ; Successful - Thu Apr 14 21:02:27 2005 ; +; Quartus II Version ; 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition ; +; Revision Name ; yacc ; +; Top-level Entity Name ; yacc ; +; Family ; Cyclone ; +; Device ; EP1C12Q240C6 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 3,624 / 12,060 ( 30 % ) ; +; Total pins ; 53 / 173 ( 30 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 137,216 / 239,616 ( 57 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++-------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/14/2005 20:28:30 ; +; Main task ; Compilation ; +; Revision Name ; yacc ; ++-------------------+---------------------+ + + ++-------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+ +; Module Name ; Elapsed Time ; ++----------------------+--------------+ +; Analysis & Synthesis ; 00:04:40 ; +; Fitter ; 00:25:30 ; +; Assembler ; 00:00:27 ; +; Timing Analyzer ; 00:00:17 ; +; EDA Netlist Writer ; 00:02:29 ; +; Total ; 00:33:23 ; ++----------------------+--------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --lower_priority --import_settings_files=on --export_settings_files=off yacc -c yacc +quartus_fit --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc +quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc +quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc --timing_analysis_only +quartus_eda --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc + + + Index: yacc.fit.summary =================================================================== --- yacc.fit.summary (nonexistent) +++ yacc.fit.summary (revision 4) @@ -0,0 +1,13 @@ +Flow Status : Successful - Thu Apr 14 20:58:42 2005 +Quartus II Version : 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +Revision Name : yacc +Top-level Entity Name : yacc +Family : Cyclone +Device : EP1C12Q240C6 +Timing Models : Final +Met timing requirements : N/A +Total logic elements : 3,624 / 12,060 ( 30 % ) +Total pins : 53 / 173 ( 30 % ) +Total virtual pins : 0 +Total memory bits : 137,216 / 239,616 ( 57 % ) +Total PLLs : 0 / 2 ( 0 % ) Index: yacc.tan.summary =================================================================== --- yacc.tan.summary (nonexistent) +++ yacc.tan.summary (revision 4) @@ -0,0 +1,66 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 6.078 ns +From : RXD +To : uart_read:uread|rxq1 +From Clock : +To Clock : clock +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 9.112 ns +From : uart_write:uwite|txd +To : TXD +From Clock : clock +To Clock : +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : -6.037 ns +From : RXD +To : uart_read:uread|rxq1 +From Clock : +To Clock : clock +Failed Paths : 0 + +Type : Clock Setup: 'clock' +Slack : 0.454 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : 104.76 MHz ( period = 9.546 ns ) +From : Pipelined_RegFile:pipe|test2D~57 +To : decoder:d1|control_state[4]~476 +From Clock : clock +To Clock : clock +Failed Paths : 0 + +Type : Clock Hold: 'clock' +Slack : 0.633 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : N/A +From : Pipelined_RegFile:pipe|mul_div:MulDiv|answer_reg[31] +To : Pipelined_RegFile:pipe|mul_div:MulDiv|answer_reg[31] +From Clock : clock +To Clock : clock +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + Index: cmp_state.ini =================================================================== --- cmp_state.ini (nonexistent) +++ cmp_state.ini (revision 4) @@ -0,0 +1 @@ +49 \ No newline at end of file Index: fifo512_cyclone_bb.v =================================================================== --- fifo512_cyclone_bb.v (nonexistent) +++ fifo512_cyclone_bb.v (revision 4) @@ -0,0 +1,119 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo512_cyclone.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module fifo512_cyclone ( + data, + wrreq, + rdreq, + clock, + q, + full, + empty); + + input [7:0] data; + input wrreq; + input rdreq; + input clock; + output [7:0] q; + output full; + output empty; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_wave*.jpg FALSE Index: yacc_fpga.qpf =================================================================== --- yacc_fpga.qpf (nonexistent) +++ yacc_fpga.qpf (revision 4) @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.2" +DATE = "15:15:55 April 09, 2005" + + +# Revisions + +PROJECT_REVISION = "yacc" Index: yacc.asm.rpt =================================================================== --- yacc.asm.rpt (nonexistent) +++ yacc.asm.rpt (revision 4) @@ -0,0 +1,138 @@ +Assembler report for yacc +Thu Apr 14 20:59:32 2005 +Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: F:/yacc/syn/altera/yacc.sof + 6. Assembler Device Options: F:/yacc/syn/altera/yacc.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2005 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Apr 14 20:59:31 2005 ; +; Revision Name ; yacc ; +; Top-level Entity Name ; yacc ; +; Family ; Cyclone ; +; Device ; EP1C12Q240C6 ; ++-----------------------+---------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++---------------------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Normal ; Normal ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate In System Configuration File (.isc) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; +; Generate Serial Vector Format File (.svf) For Configuration Device ; Off ; Off ; +; Generate In System Configuration File (.isc) For Configuration Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam)For Configuration Device ; Off ; Off ; +; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) For Configuration Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) For Configuration Device ; On ; On ; +; Generate Hexadecimal (Intel-format) Output File (.hexout) For Configuration Device ; Off ; Off ; +; Generate compressed bitstreams ; on ; on ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHz ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; JTAG user code for target device ; Ffffffff ; Ffffffff ; +; Auto user code ; off ; off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; JTAG user code for configuration device ; Ffffffff ; Ffffffff ; +; Configuration device auto user code ; off ; off ; +; Auto-increment JTAG user code for multiple configuration devices ; On ; On ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; off ; off ; +; Auto-restart configuration after error ; On ; On ; ++---------------------------------------------------------------------------------------+----------+---------------+ + + ++-----------------------------+ +; Assembler Generated Files ; ++-----------------------------+ +; File Name ; ++-----------------------------+ +; F:/yacc/syn/altera/yacc.sof ; +; F:/yacc/syn/altera/yacc.pof ; ++-----------------------------+ + + ++-------------------------------------------------------+ +; Assembler Device Options: F:/yacc/syn/altera/yacc.sof ; ++----------------+--------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------+ +; Device ; EP1C12Q240C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x004338A4 ; ++----------------+--------------------------------------+ + + ++-------------------------------------------------------+ +; Assembler Device Options: F:/yacc/syn/altera/yacc.pof ; ++----------------+--------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x067B7A51 ; ++----------------+--------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition + Info: Processing started: Thu Apr 14 20:59:05 2005 +Info: Command: quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Processing ended: Thu Apr 14 20:59:31 2005 + Info: Elapsed time: 00:00:27 + + Index: yacc.done =================================================================== --- yacc.done (nonexistent) +++ yacc.done (revision 4) @@ -0,0 +1 @@ +Thu Apr 14 21:03:47 2005 Index: ram4092x8_0_bb.v =================================================================== --- ram4092x8_0_bb.v (nonexistent) +++ ram4092x8_0_bb.v (revision 4) @@ -0,0 +1,169 @@ +// megafunction wizard: %RAM: 2-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram4092x8_0.v +// Megafunction Name(s): +// altsyncram +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module ram4092x8_0 ( + data_a, + wren_a, + address_a, + data_b, + address_b, + wren_b, + clock, + q_a, + q_b); + + input [7:0] data_a; + input wren_a; + input [11:0] address_a; + input [7:0] data_b; + input [11:0] address_b; + input wren_b; + input clock; + output [7:0] q_a; + output [7:0] q_b; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "code0.hex" +// Retrieval info: PRIVATE: UseLCs NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: INIT_FILE STRING "code0.hex" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] +// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0] +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] +// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0] +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_wave*.jpg FALSE Index: yacc.pin =================================================================== --- yacc.pin (nonexistent) +++ yacc.pin (revision 4) @@ -0,0 +1,303 @@ + -- Copyright (C) 1991-2005 Altera Corporation + -- Any megafunction design, and related netlist (encrypted or decrypted), + -- support information, device programming or simulation file, and any other + -- associated documentation or information provided by Altera or a partner + -- under Altera's Megafunction Partnership Program may be used only + -- to program PLD devices (but not masked PLD devices) from Altera. Any + -- other use of such megafunction design, netlist, support information, + -- device programming or simulation file, or any other related documentation + -- or information is prohibited for any other purpose, including, but not + -- limited to modification, reverse engineering, de-compiling, or use with + -- any other silicon devices, unless such use is explicitly licensed under + -- a separate agreement with Altera or a megafunction partner. Title to the + -- intellectual property, including patents, copyrights, trademarks, trade + -- secrets, or maskworks, embodied in any such megafunction design, netlist, + -- support information, device programming or simulation file, or any other + -- related documentation or information provided by Altera or a megafunction + -- partner, remains with Altera, the megafunction partner, or their respective + -- licensors. No other licenses, including any licenses needed under any third + -- party's intellectual property, are provided herein. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. This pin can either be left unconnected or + -- connected to GND. Connecting this pin to GND will improve the + -- device's immunity to noise. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + --------------------------------------------------------------------------------- + +Quartus II Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition +CHIP "yacc" ASSIGNED TO AN: EP1C12Q240C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND* : 1 : : : : 1 : +GND* : 2 : : : : 1 : +GND* : 3 : : : : 1 : +GND* : 4 : : : : 1 : +GND* : 5 : : : : 1 : +GND* : 6 : : : : 1 : +GND* : 7 : : : : 1 : +GND* : 8 : : : : 1 : +VCCIO1 : 9 : power : : 3.3V : 1 : +GND : 10 : gnd : : : : +GND* : 11 : : : : 1 : +GND* : 12 : : : : 1 : +GND* : 13 : : : : 1 : +GND* : 14 : : : : 1 : +GND* : 15 : : : : 1 : +GND* : 16 : : : : 1 : +GND* : 17 : : : : 1 : +GND* : 18 : : : : 1 : +MemoryWData[19] : 19 : output : LVTTL : : 1 : N +MemoryWData[24] : 20 : output : LVTTL : : 1 : N +MemoryWData[9] : 21 : output : LVTTL : : 1 : N +VCCIO1 : 22 : power : : 3.3V : 1 : +MemoryWData[20] : 23 : output : LVTTL : : 1 : N +~nCSO~ / GND* : 24 : output : LVTTL : : 1 : N +DATA0 : 25 : input : : : 1 : +nCONFIG : 26 : : : : 1 : +VCCA_PLL1 : 27 : power : : 1.5V : : +clock : 28 : input : LVTTL : : 1 : Y +GND+ : 29 : : : : 1 : +GNDA_PLL1 : 30 : gnd : : : : +GNDG_PLL1 : 31 : gnd : : : : +nCEO : 32 : : : : 1 : +nCE : 33 : : : : 1 : +MSEL0 : 34 : : : : 1 : +MSEL1 : 35 : : : : 1 : +DCLK : 36 : bidir : : : 1 : +~ASDO~ / GND* : 37 : output : LVTTL : : 1 : N +GND* : 38 : : : : 1 : +GND* : 39 : : : : 1 : +GND : 40 : gnd : : : : +GND* : 41 : : : : 1 : +GND* : 42 : : : : 1 : +GND* : 43 : : : : 1 : +GND* : 44 : : : : 1 : +GND* : 45 : : : : 1 : +GND* : 46 : : : : 1 : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND* : 49 : : : : 1 : +GND* : 50 : : : : 1 : +VCCIO1 : 51 : power : : 3.3V : 1 : +GND : 52 : gnd : : : : +GND* : 53 : : : : 1 : +GND* : 54 : : : : 1 : +GND* : 55 : : : : 1 : +GND* : 56 : : : : 1 : +GND* : 57 : : : : 1 : +GND* : 58 : : : : 1 : +GND* : 59 : : : : 1 : +GND* : 60 : : : : 1 : +GND* : 61 : : : : 4 : +GND* : 62 : : : : 4 : +GND* : 63 : : : : 4 : +GND* : 64 : : : : 4 : +GND* : 65 : : : : 4 : +GND* : 66 : : : : 4 : +GND* : 67 : : : : 4 : +GND* : 68 : : : : 4 : +GND : 69 : gnd : : : : +VCCIO4 : 70 : power : : 3.3V : 4 : +GND : 71 : gnd : : : : +VCCINT : 72 : power : : 1.5V : : +GND* : 73 : : : : 4 : +GND* : 74 : : : : 4 : +MemoryWData[26] : 75 : output : LVTTL : : 4 : N +GND* : 76 : : : : 4 : +MemoryWData[12] : 77 : output : LVTTL : : 4 : N +MemoryWData[10] : 78 : output : LVTTL : : 4 : N +MemoryWData[11] : 79 : output : LVTTL : : 4 : N +GND : 80 : gnd : : : : +VCCINT : 81 : power : : 1.5V : : +MemoryWData[13] : 82 : output : LVTTL : : 4 : N +MemoryWData[14] : 83 : output : LVTTL : : 4 : N +MemoryWData[16] : 84 : output : LVTTL : : 4 : N +MemoryWData[8] : 85 : output : LVTTL : : 4 : N +data_port_address[2] : 86 : output : LVTTL : : 4 : N +MemoryWData[22] : 87 : output : LVTTL : : 4 : N +data_port_address[12] : 88 : output : LVTTL : : 4 : N +GND : 89 : gnd : : : : +VCCINT : 90 : power : : 1.5V : : +GND : 91 : gnd : : : : +VCCIO4 : 92 : power : : 3.3V : 4 : +data_port_address[15] : 93 : output : LVTTL : : 4 : N +data_port_address[10] : 94 : output : LVTTL : : 4 : N +data_port_address[11] : 95 : output : LVTTL : : 4 : N +GND : 96 : gnd : : : : +VCCINT : 97 : power : : 1.5V : : +data_port_address[7] : 98 : output : LVTTL : : 4 : N +data_port_address[5] : 99 : output : LVTTL : : 4 : N +data_port_address[8] : 100 : output : LVTTL : : 4 : N +data_port_address[6] : 101 : output : LVTTL : : 4 : N +GND : 102 : gnd : : : : +VCCINT : 103 : power : : 1.5V : : +MemoryWData[31] : 104 : output : LVTTL : : 4 : N +data_port_address[14] : 105 : output : LVTTL : : 4 : N +data_port_address[9] : 106 : output : LVTTL : : 4 : N +GND* : 107 : : : : 4 : +GND* : 108 : : : : 4 : +GND : 109 : gnd : : : : +VCCINT : 110 : power : : 1.5V : : +GND : 111 : gnd : : : : +VCCIO4 : 112 : power : : 3.3V : 4 : +RXD : 113 : input : LVTTL : : 4 : Y +TXD : 114 : output : LVTTL : : 4 : Y +GND* : 115 : : : : 4 : +GND* : 116 : : : : 4 : +GND* : 117 : : : : 4 : +GND* : 118 : : : : 4 : +GND* : 119 : : : : 4 : +GND* : 120 : : : : 4 : +GND* : 121 : : : : 3 : +GND* : 122 : : : : 3 : +GND* : 123 : : : : 3 : +GND* : 124 : : : : 3 : +GND* : 125 : : : : 3 : +GND* : 126 : : : : 3 : +GND* : 127 : : : : 3 : +GND* : 128 : : : : 3 : +GND : 129 : gnd : : : : +VCCIO3 : 130 : power : : 3.3V : 3 : +GND* : 131 : : : : 3 : +GND* : 132 : : : : 3 : +GND* : 133 : : : : 3 : +GND* : 134 : : : : 3 : +GND* : 135 : : : : 3 : +GND* : 136 : : : : 3 : +GND* : 137 : : : : 3 : +GND* : 138 : : : : 3 : +GND* : 139 : : : : 3 : +MWriteFF : 140 : output : LVTTL : : 3 : N +GND* : 141 : : : : 3 : +GND : 142 : gnd : : : : +data_port_address[3] : 143 : output : LVTTL : : 3 : N +data_port_address[4] : 144 : output : LVTTL : : 3 : N +CONF_DONE : 145 : : : : 3 : +nSTATUS : 146 : : : : 3 : +TCK : 147 : input : : : 3 : +TMS : 148 : input : : : 3 : +TDO : 149 : output : : : 3 : +GNDG_PLL2 : 150 : gnd : : : : +GNDA_PLL2 : 151 : gnd : : : : +GND+ : 152 : : : : 3 : +GND+ : 153 : : : : 3 : +VCCA_PLL2 : 154 : power : : 1.5V : : +TDI : 155 : input : : : 3 : +GND* : 156 : : : : 3 : +VCCIO3 : 157 : power : : 3.3V : 3 : +GND* : 158 : : : : 3 : +GND* : 159 : : : : 3 : +GND* : 160 : : : : 3 : +GND* : 161 : : : : 3 : +GND* : 162 : : : : 3 : +GND* : 163 : : : : 3 : +GND* : 164 : : : : 3 : +GND* : 165 : : : : 3 : +GND* : 166 : : : : 3 : +GND* : 167 : : : : 3 : +GND* : 168 : : : : 3 : +GND* : 169 : : : : 3 : +GND* : 170 : : : : 3 : +GND : 171 : gnd : : : : +VCCIO3 : 172 : power : : 3.3V : 3 : +GND* : 173 : : : : 3 : +GND* : 174 : : : : 3 : +GND* : 175 : : : : 3 : +GND* : 176 : : : : 3 : +GND* : 177 : : : : 3 : +GND* : 178 : : : : 3 : +GND* : 179 : : : : 3 : +GND* : 180 : : : : 3 : +GND* : 181 : : : : 2 : +GND* : 182 : : : : 2 : +GND* : 183 : : : : 2 : +GND* : 184 : : : : 2 : +GND* : 185 : : : : 2 : +GND* : 186 : : : : 2 : +GND* : 187 : : : : 2 : +GND* : 188 : : : : 2 : +VCCIO2 : 189 : power : : 3.3V : 2 : +GND : 190 : gnd : : : : +VCCINT : 191 : power : : 1.5V : : +GND : 192 : gnd : : : : +GND* : 193 : : : : 2 : +GND* : 194 : : : : 2 : +GND* : 195 : : : : 2 : +GND* : 196 : : : : 2 : +GND* : 197 : : : : 2 : +VCCINT : 198 : power : : 1.5V : : +GND : 199 : gnd : : : : +MemoryWData[30] : 200 : output : LVTTL : : 2 : N +MemoryWData[27] : 201 : output : LVTTL : : 2 : N +MemoryWData[28] : 202 : output : LVTTL : : 2 : N +data_port_address[13] : 203 : output : LVTTL : : 2 : N +VCCINT : 204 : power : : 1.5V : : +GND : 205 : gnd : : : : +data_port_address[0] : 206 : output : LVTTL : : 2 : N +data_port_address[1] : 207 : output : LVTTL : : 2 : N +MemoryWData[0] : 208 : output : LVTTL : : 2 : N +VCCIO2 : 209 : power : : 3.3V : 2 : +GND : 210 : gnd : : : : +VCCINT : 211 : power : : 1.5V : : +GND : 212 : gnd : : : : +MemoryWData[1] : 213 : output : LVTTL : : 2 : N +MemoryWData[5] : 214 : output : LVTTL : : 2 : N +MemoryWData[6] : 215 : output : LVTTL : : 2 : N +MemoryWData[18] : 216 : output : LVTTL : : 2 : N +MemoryWData[3] : 217 : output : LVTTL : : 2 : N +MemoryWData[4] : 218 : output : LVTTL : : 2 : N +MemoryWData[2] : 219 : output : LVTTL : : 2 : N +VCCINT : 220 : power : : 1.5V : : +GND : 221 : gnd : : : : +MemoryWData[15] : 222 : output : LVTTL : : 2 : N +MemoryWData[7] : 223 : output : LVTTL : : 2 : N +MemoryWData[21] : 224 : output : LVTTL : : 2 : N +MemoryWData[25] : 225 : output : LVTTL : : 2 : N +MemoryWData[23] : 226 : output : LVTTL : : 2 : N +MemoryWData[17] : 227 : output : LVTTL : : 2 : N +MemoryWData[29] : 228 : output : LVTTL : : 2 : N +VCCINT : 229 : power : : 1.5V : : +GND : 230 : gnd : : : : +VCCIO2 : 231 : power : : 3.3V : 2 : +GND : 232 : gnd : : : : +GND* : 233 : : : : 2 : +GND* : 234 : : : : 2 : +GND* : 235 : : : : 2 : +GND* : 236 : : : : 2 : +GND* : 237 : : : : 2 : +GND* : 238 : : : : 2 : +GND* : 239 : : : : 2 : +Async_Reset : 240 : input : LVTTL : : 2 : Y Index: yacc.qsf =================================================================== --- yacc.qsf (nonexistent) +++ yacc.qsf (revision 4) @@ -0,0 +1,100 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + +# The default values for assignments are stored in the file +# yacc_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.2 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:15:56 APRIL 09, 2005" +set_global_assignment -name LAST_QUARTUS_VERSION "4.2 SP1" +set_global_assignment -name VERILOG_FILE ram_regfile32xx32.v +set_global_assignment -name VERILOG_FILE fifo512_cyclone.v +set_global_assignment -name VERILOG_FILE ram4092x8_0.v +set_global_assignment -name VERILOG_FILE ram4092x8_1.v +set_global_assignment -name VERILOG_FILE ram4096x8_2.v +set_global_assignment -name VERILOG_FILE ram4096x8_3.v +set_global_assignment -name VERILOG_FILE ../../rtl/yacc2.v +set_global_assignment -name VERILOG_FILE ../../rtl/alu.v +set_global_assignment -name VERILOG_FILE ../../rtl/decoder.v +set_global_assignment -name VERILOG_FILE ../../rtl/mul_div_module5.v +set_global_assignment -name VERILOG_FILE ../../rtl/pc_module.v +set_global_assignment -name VERILOG_FILE ../../rtl/pipelined_rfile.v +set_global_assignment -name VERILOG_FILE ../../rtl/ram_module_altera.v +set_global_assignment -name VERILOG_FILE ../../rtl/shifter.v +set_global_assignment -name VERILOG_FILE ../../rtl/uart_read.v +set_global_assignment -name VERILOG_FILE ../../rtl/uart_write_cyclone.v + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_240 -to Async_Reset +set_location_assignment PIN_28 -to clock +set_location_assignment PIN_113 -to RXD +set_location_assignment PIN_114 -to TXD + +# Timing Assignments +# ================== +set_global_assignment -name IGNORE_CLOCK_SETTINGS ON +set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON +set_global_assignment -name TOP_LEVEL_ENTITY yacc +set_global_assignment -name USER_LIBRARIES "F:\\yacc\\syn\\altera" + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C6 +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name FITTER_EFFORT "FAST FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL" + +# --------------------------------------- +# start EDA_TOOL_SETTINGS(eda_simulation) + + # EDA Netlist Writer Assignments + # ============================== + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation + set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- Index: yacc_test2_for_gate.v =================================================================== --- yacc_test2_for_gate.v (nonexistent) +++ yacc_test2_for_gate.v (revision 4) @@ -0,0 +1,132 @@ +//YACC Test Bench +//Apr.5.2005 Tak.Sugawara + +`include "define.h" +`timescale 1ns/1ps +`define CYCLE (9.54/2) //104.76MHz +module yacc_test; + reg clock=0; + reg Reset=0; + reg int_req_usr=0; + reg RXD=1'b1; + wire TXD; + wire [31:0] mem_data_w; + wire mem_write; + wire [15:0] mem_address; + always #(`CYCLE) clock=~clock; + + + + initial begin + Reset=0; + #800 Reset=1; + end + +`ifdef RTL_SIMULATION + yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w), + .MWriteFF(mem_write), + .data_port_address(mem_address),.RXD(RXD),.TXD(TXD)); +`else + yacc cpu(.clock(clock),.Async_Reset(Reset), .RXD(RXD),.TXD(TXD)); + +`endif + + + + + + + + + task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified. + integer i; + begin :Block + i=0; + while (1) begin + if (char_buffer[i*8 +:8] ===8'h00 || char_buffer[i*8 +:8]===8'hxx) begin + disable Block; + end + $write("%c",char_buffer[i*8 +:8]); + i=i+1; + end + end + endtask + + reg [0:640*2-1] char_buffer; + integer counter=0; + always @ (posedge clock ) begin + if ((mem_write === 1'b1)) begin + if (mem_address==`Print_Port_Address) begin + if (mem_data_w[7:0]===8'h00) begin + char_buffer[counter*8 +:8]=mem_data_w[7:0]; + if (char_buffer[0 +:8*7]==="$finish") begin + $stop; + + end else if (char_buffer[0 +:8*5]==="$time") begin + $display("Current Time on Simulation=%d",$time); + + end else Cprint;//$write("%s",char_buffer); + + for (counter=0; counter< 80*2; counter=counter+1) begin + char_buffer[counter*8 +:8]=8'h00; + end + counter=0; + + end else begin + char_buffer[counter*8 +:8]=mem_data_w[7:0]; + counter=counter+1; + end + end + else if (mem_address==`Print_CAHR_Port_Address) begin + $write("%h ",mem_data_w[7:0]); + end else if (mem_address==`Print_INT_Port_Address) begin + $write("%h ",mem_data_w[15:0]);//Little Endian + end else if (mem_address==`Print_LONG_Port_Address) begin + $write("%h ",mem_data_w[31:0]);//Big Endian + end + end //if + end //always + + +//uart read port + wire [7:0] buffer_reg; + wire int_req; + reg sync_reset; + + localparam LF=8'h0a; + always @(posedge clock, negedge Reset) begin + if (!Reset) sync_reset <=1'b1; + else sync_reset<=1'b0; + end + + + + uart_read uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req)); + + always @(posedge int_req) begin + begin :local + + reg [7:0] local_mem [0:1000]; + integer i=0; + + if (i>=1000) $stop;//assert(0); + + if (buffer_reg==LF) begin :local2 //pop stack + integer j; + j=0; + while( j < i) begin + $write( "%c",local_mem[j]); + j=j+1; + end + $write(" : time=%t\n",$time); + i=0;//clear stack + end else begin//push stack + + local_mem[i]=buffer_reg; + i=i+1; + end + end + + end +endmodule + Index: ram4096x8_2_bb.v =================================================================== --- ram4096x8_2_bb.v (nonexistent) +++ ram4096x8_2_bb.v (revision 4) @@ -0,0 +1,169 @@ +// megafunction wizard: %RAM: 2-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram4096x8_2.v +// Megafunction Name(s): +// altsyncram +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module ram4096x8_2 ( + data_a, + wren_a, + address_a, + data_b, + address_b, + wren_b, + clock, + q_a, + q_b); + + input [7:0] data_a; + input wren_a; + input [11:0] address_a; + input [7:0] data_b; + input [11:0] address_b; + input wren_b; + input clock; + output [7:0] q_a; + output [7:0] q_b; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "code2.hex" +// Retrieval info: PRIVATE: UseLCs NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: INIT_FILE STRING "code2.hex" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] +// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0] +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] +// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0] +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_wave*.jpg FALSE Index: ram_regfile32xx32.v =================================================================== --- ram_regfile32xx32.v (nonexistent) +++ ram_regfile32xx32.v (revision 4) @@ -0,0 +1,188 @@ +// megafunction wizard: %RAM: 3-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: alt3pram + +// ============================================================ +// File Name: ram_regfile32xx32.v +// Megafunction Name(s): +// alt3pram +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2005 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram_regfile32xx32 ( + data, + wraddress, + rdaddress_a, + rdaddress_b, + wren, + clock, + qa, + qb); + + input [31:0] data; + input [4:0] wraddress; + input [4:0] rdaddress_a; + input [4:0] rdaddress_b; + input wren; + input clock; + output [31:0] qa; + output [31:0] qb; + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire [31:0] qa = sub_wire0[31:0]; + wire [31:0] qb = sub_wire1[31:0]; + + alt3pram alt3pram_component ( + .wren (wren), + .inclock (clock), + .data (data), + .rdaddress_a (rdaddress_a), + .wraddress (wraddress), + .rdaddress_b (rdaddress_b), + .qa (sub_wire0), + .qb (sub_wire1) + // synopsys translate_off + , + .aclr (), + .inclocken (), + .outclock (), + .outclocken (), + .rden_a (), + .rden_b () + // synopsys translate_on + ); + defparam + alt3pram_component.intended_device_family = "Cyclone", + alt3pram_component.width = 32, + alt3pram_component.widthad = 5, + alt3pram_component.indata_reg = "INCLOCK", + alt3pram_component.write_reg = "INCLOCK", + alt3pram_component.rdaddress_reg_a = "INCLOCK", + alt3pram_component.rdaddress_reg_b = "INCLOCK", + alt3pram_component.rdcontrol_reg_a = "UNREGISTERED", + alt3pram_component.rdcontrol_reg_b = "UNREGISTERED", + alt3pram_component.outdata_reg_a = "UNREGISTERED", + alt3pram_component.outdata_reg_b = "UNREGISTERED", + alt3pram_component.indata_aclr = "OFF", + alt3pram_component.write_aclr = "OFF", + alt3pram_component.rdaddress_aclr_a = "OFF", + alt3pram_component.rdaddress_aclr_b = "OFF", + alt3pram_component.rdcontrol_aclr_a = "OFF", + alt3pram_component.rdcontrol_aclr_b = "OFF", + alt3pram_component.outdata_aclr_a = "OFF", + alt3pram_component.outdata_aclr_b = "OFF", + alt3pram_component.lpm_type = "alt3pram", + alt3pram_component.lpm_hint = "USE_EAB=ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: WidthData NUMERIC "32" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "5" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: rden_a NUMERIC "0" +// Retrieval info: PRIVATE: rden_b NUMERIC "0" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGwrite NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1" +// Retrieval info: PRIVATE: REGrren_a NUMERIC "0" +// Retrieval info: PRIVATE: REGrren_b NUMERIC "0" +// Retrieval info: PRIVATE: REGqa NUMERIC "0" +// Retrieval info: PRIVATE: REGqb NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRwrite NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0" +// Retrieval info: PRIVATE: CLRqa NUMERIC "0" +// Retrieval info: PRIVATE: CLRqb NUMERIC "0" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: UseLCs NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: WIDTHAD NUMERIC "5" +// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK" +// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK" +// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK" +// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK" +// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF" +// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF" +// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF" +// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF" +// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF" +// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram" +// Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +// Retrieval info: USED_PORT: qa 0 0 32 0 OUTPUT NODEFVAL qa[31..0] +// Retrieval info: USED_PORT: qb 0 0 32 0 OUTPUT NODEFVAL qb[31..0] +// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0] +// Retrieval info: USED_PORT: rdaddress_a 0 0 5 0 INPUT NODEFVAL rdaddress_a[4..0] +// Retrieval info: USED_PORT: rdaddress_b 0 0 5 0 INPUT NODEFVAL rdaddress_b[4..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: qa 0 0 32 0 @qa 0 0 32 0 +// Retrieval info: CONNECT: qb 0 0 32 0 @qb 0 0 32 0 +// Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0 +// Retrieval info: CONNECT: @rdaddress_a 0 0 5 0 rdaddress_a 0 0 5 0 +// Retrieval info: CONNECT: @rdaddress_b 0 0 5 0 rdaddress_b 0 0 5 0 +// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_bb.v TRUE Index: yacc.eda.rpt =================================================================== --- yacc.eda.rpt (nonexistent) +++ yacc.eda.rpt (revision 4) @@ -0,0 +1,94 @@ +EDA Netlist Writer report for yacc +Thu Apr 14 21:02:27 2005 +Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Tool Settings + 4. Simulation Tool Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2005 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Apr 14 21:02:27 2005 ; +; Revision Name ; yacc ; +; Top-level Entity Name ; yacc ; +; Family ; Cyclone ; +; Simulation Tool Writer ; Successful ; ++---------------------------+---------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Simulation Tool Settings ; ++------------------------------------------------------+--------------------+ +; Option ; Setting ; ++------------------------------------------------------+--------------------+ +; Tool Name ; Custom Verilog HDL ; +; Generate Netlist for Functional Simulation Only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal Verilog HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Output Excalibur stripe as a single module or entity ; Off ; +; Enable glitch filtering ; Off ; ++------------------------------------------------------+--------------------+ + + ++-------------------------------------------------+ +; Simulation Tool Generated Files ; ++-------------------------------------------------+ +; Generated Files ; ++-------------------------------------------------+ +; F:/yacc/syn/altera/simulation/custom/yacc.vo ; +; F:/yacc/syn/altera/simulation/custom/yacc_v.sdo ; ++-------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II EDA Netlist Writer + Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition + Info: Processing started: Thu Apr 14 20:59:58 2005 +Info: Command: quartus_eda --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc +Info: Generated files "yacc.vo" and "yacc_v.sdo" in directory "F:/yacc/syn/altera/simulation/custom/" for EDA simulation tool +Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Processing ended: Thu Apr 14 21:02:27 2005 + Info: Elapsed time: 00:02:29 + + Index: ram_regfile32xx32_bb.v =================================================================== --- ram_regfile32xx32_bb.v (nonexistent) +++ ram_regfile32xx32_bb.v (revision 4) @@ -0,0 +1,135 @@ +// megafunction wizard: %RAM: 3-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: alt3pram + +// ============================================================ +// File Name: ram_regfile32xx32.v +// Megafunction Name(s): +// alt3pram +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module ram_regfile32xx32 ( + data, + wraddress, + rdaddress_a, + rdaddress_b, + wren, + clock, + qa, + qb); + + input [31:0] data; + input [4:0] wraddress; + input [4:0] rdaddress_a; + input [4:0] rdaddress_b; + input wren; + input clock; + output [31:0] qa; + output [31:0] qb; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: WidthData NUMERIC "32" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "5" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: rden_a NUMERIC "0" +// Retrieval info: PRIVATE: rden_b NUMERIC "0" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGwrite NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1" +// Retrieval info: PRIVATE: REGrren_a NUMERIC "0" +// Retrieval info: PRIVATE: REGrren_b NUMERIC "0" +// Retrieval info: PRIVATE: REGqa NUMERIC "0" +// Retrieval info: PRIVATE: REGqb NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRwrite NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0" +// Retrieval info: PRIVATE: CLRqa NUMERIC "0" +// Retrieval info: PRIVATE: CLRqb NUMERIC "0" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: UseLCs NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: WIDTHAD NUMERIC "5" +// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK" +// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK" +// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK" +// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK" +// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF" +// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF" +// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF" +// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF" +// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF" +// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram" +// Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +// Retrieval info: USED_PORT: qa 0 0 32 0 OUTPUT NODEFVAL qa[31..0] +// Retrieval info: USED_PORT: qb 0 0 32 0 OUTPUT NODEFVAL qb[31..0] +// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0] +// Retrieval info: USED_PORT: rdaddress_a 0 0 5 0 INPUT NODEFVAL rdaddress_a[4..0] +// Retrieval info: USED_PORT: rdaddress_b 0 0 5 0 INPUT NODEFVAL rdaddress_b[4..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: qa 0 0 32 0 @qa 0 0 32 0 +// Retrieval info: CONNECT: qb 0 0 32 0 @qb 0 0 32 0 +// Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0 +// Retrieval info: CONNECT: @rdaddress_a 0 0 5 0 rdaddress_a 0 0 5 0 +// Retrieval info: CONNECT: @rdaddress_b 0 0 5 0 rdaddress_b 0 0 5 0 +// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_bb.v TRUE

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