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URL https://opencores.org/ocsvn/yavga/yavga/trunk

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    /yavga/trunk/vhdl
    from Rev 25 to Rev 28
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Rev 25 → Rev 28

/chars_RAM.vhd
53,6 → 53,8
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
use work.yavga_pkg.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
62,7 → 64,7
port (
i_clock_rw : in std_logic; -- Write Clock
i_EN_rw : in std_logic; -- Write RAM Enable Input
i_WE_rw : in std_logic_vector(3 downto 0); -- Write Enable Input
i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0); -- Write Enable Input
i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input
i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input
o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input
162,7 → 164,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => i_EN_r, -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
260,7 → 262,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => i_EN_r, -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
358,7 → 360,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => i_EN_r, -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
456,7 → 458,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => i_EN_r, -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
/s3e_starter_1600k.vhd
60,12 → 60,12
--use UNISIM.VComponents.all;
 
entity s3e_starter_1600k is
port (i_clk : in std_logic;
o_hsync : out std_logic;
o_vsync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic);
port (i_clk : in std_logic;
o_hsync : out std_logic;
o_vsync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic);
end s3e_starter_1600k;
 
architecture Behavioral of s3e_starter_1600k is
72,26 → 72,26
 
component vga_ctrl
port(
i_clk : in std_logic;
i_reset : in std_logic;
i_h_sync_en : in std_logic;
i_v_sync_en : in std_logic;
i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_chr_clk : in std_logic;
i_chr_en : in std_logic;
i_chr_we : in std_logic_vector(3 downto 0);
i_chr_rst : in std_logic;
i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_wav_clk : in std_logic;
i_wav_we : in std_logic;
i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
o_h_sync : out std_logic;
o_v_sync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic;
o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0)
i_clk : in std_logic;
i_reset : in std_logic;
i_h_sync_en : in std_logic;
i_v_sync_en : in std_logic;
i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_chr_clk : in std_logic;
i_chr_en : in std_logic;
i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_chr_rst : in std_logic;
i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_wav_clk : in std_logic;
i_wav_we : in std_logic;
i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
o_h_sync : out std_logic;
o_v_sync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic;
o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0)
);
end component;
 
104,20 → 104,20
signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0');
signal s_vsync1 : std_logic;
 
signal s_chr_addr : std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);-- := (others => '0');
signal s_chr_data : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);-- := (others => '0');
signal s_rnd : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);-- := (others => '0');
signal s_chr_we : std_logic_vector(3 downto 0);
signal s_chr_addr : std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0); -- := (others => '0');
signal s_chr_data : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0); -- := (others => '0');
signal s_rnd : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0); -- := (others => '0');
signal s_chr_we : std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
 
signal s_wav_addr : std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
signal s_wav_d : std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
signal s_mul : std_logic_vector(7 downto 0);
signal s_wav_d : std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
signal s_mul : std_logic_vector(7 downto 0);
 
signal s_initialized : std_logic := '0';
 
attribute U_SET : string;
attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
attribute U_SET : string;
attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
begin
o_hsync <= s_hsync;
o_vsync <= s_vsync;
126,31 → 126,31
o_b <= s_b;
u1_vga_ctrl : vga_ctrl port map(
i_clk => i_clk,
i_reset => '0',
o_h_sync => s_hsync,
o_v_sync => s_vsync,
i_h_sync_en => '1',
i_v_sync_en => '1',
o_r => s_r,
o_g => s_g,
o_b => s_b,
i_chr_addr => s_chr_addr, --B"000_0000_0000",
i_chr_data => s_chr_data, --X"00000000",
o_chr_data => open,
i_chr_clk => i_clk,
i_chr_en => '1',
i_chr_we => s_chr_we,
i_chr_rst => '0',
i_wav_d => s_wav_d, --X"0000", --s_rnd(15 downto 0), --
i_wav_clk => i_clk,
i_wav_we => '0', --'0', -- '1',
i_wav_addr => s_wav_addr --B"00_0000_0000" --s_chr_addr(9 downto 0) --
i_clk => i_clk,
i_reset => '0',
o_h_sync => s_hsync,
o_v_sync => s_vsync,
i_h_sync_en => '1',
i_v_sync_en => '1',
o_r => s_r,
o_g => s_g,
o_b => s_b,
i_chr_addr => s_chr_addr, --B"000_0000_0000",
i_chr_data => s_chr_data, --X"00000000",
o_chr_data => open,
i_chr_clk => i_clk,
i_chr_en => '1',
i_chr_we => s_chr_we,
i_chr_rst => '0',
i_wav_d => s_wav_d, --X"0000", --s_rnd(15 downto 0), --
i_wav_clk => i_clk,
i_wav_we => '0', --'0', -- '1',
i_wav_addr => s_wav_addr --B"00_0000_0000" --s_chr_addr(9 downto 0) --
);
s_wav_addr <= s_rnd(1 downto 0) & s_vsync_count;
s_mul <= s_vsync_count(3 downto 0) * s_vsync_count(3 downto 0);
s_wav_d <= B"000" & s_rnd(2 downto 0) & B"00" & s_mul;
--s_wav_d <= B"000" & "100" & B"00" & s_mul;
s_wav_addr <= s_rnd(1 downto 0) & s_vsync_count;
s_mul <= s_vsync_count(3 downto 0) * s_vsync_count(3 downto 0);
s_wav_d <= B"000" & s_rnd(2 downto 0) & B"00" & s_mul;
--s_wav_d <= B"000" & "100" & B"00" & s_mul;
 
-- s_chr_data <= s_rnd;
-- p_write_chars : process(i_clk)
172,7 → 172,7
-- end if;
-- end if;
-- end process;
 
-- cols cols
-- 00_01_02_03 ... 96_97_98_99
-- row_00 "00000000000" ... "00000011000"
184,40 → 184,40
if rising_edge(i_clk) then
if s_initialized = '0' then
case s_vsync_count(2 downto 0) is
when "000" => -- write ABCD
when "000" => -- write ABCD
s_chr_we <= "1111";
s_chr_addr <= "00000000000";
s_chr_data <= "01000001" & "01000010" & "01000011" & "01000100";
when "001" => -- write EFGH
when "001" => -- write EFGH
s_chr_we <= "1111";
s_chr_addr <= "00000011000";
s_chr_data <= "01000101" & "01000110" & "01000111" & "01001000";
when "010" => -- write IJKL
when "010" => -- write IJKL
s_chr_we <= "1111";
s_chr_addr <= "00000100000";
s_chr_data <= "01001001" & "01001010" & "01001011" & "01001100";
when "011" => -- write MNOP
when "011" => -- write MNOP
s_chr_we <= "1111";
s_chr_addr <= "10010100000";
s_chr_data <= "01001101" & "01001110" & "01001111" & "01010000";
when "100" => -- write QRST
when "100" => -- write QRST
s_chr_we <= "1111";
s_chr_addr <= "10010111000";
s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
when "101" => -- write config grid and cursor color
s_chr_we <= "1111";
s_chr_addr <= c_BG_CUR_COLOR_ADDR(c_BG_CUR_COLOR_ADDR'left downto 2); -- c_BG_CUR_COLOR_ADDR >> 2
when "101" => -- write config grid and cursor color
s_chr_we <= "1111";
s_chr_addr <= c_CFG_BG_CUR_COLOR_ADDR(c_CFG_BG_CUR_COLOR_ADDR'left downto 2); -- c_CFG_BG_CUR_COLOR_ADDR >> 2
-- ND bgColor grid,cur ND curs_x curs_y
s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
-- |--------108-------|-------109-------|----110-----|--111--|
s_initialized <= '1';
when others =>
s_chr_we <= (others => '0');
s_chr_addr <= (others => '1');
s_chr_data <= "11111111" & "11111101" & "11111100" & "11111110";
s_chr_data <= "10111110" & "10111101" & "10111100" & "10111011";
end case;
else
s_chr_we <= (others => '0');
s_chr_we <= (others => '0');
end if;
end if;
end process;
/vga_ctrl.vhd
88,13 → 88,13
o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_chr_clk : in std_logic;
i_chr_en : in std_logic;
i_chr_we : in std_logic_vector(3 downto 0);
i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_chr_rst : in std_logic;
 
-- waveform RAM memory
i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_wav_we : in std_logic;
i_wav_clk : IN std_logic;
i_wav_clk : in std_logic;
i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0) --;
--o_DOA : OUT std_logic_vector(15 downto 0)
);
133,15 → 133,15
architecture rtl of vga_ctrl is
 
--
signal s_h_count : std_logic_vector(10 downto 0); -- horizontal pixel counter
signal s_v_count : std_logic_vector(9 downto 0); -- verticalal line counter
signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter
signal s_h_count : std_logic_vector(c_H_COUNT_W - 1 downto 0); -- horizontal pixel counter
signal s_v_count : std_logic_vector(c_V_COUNT_W - 1 downto 0); -- verticalal line counter
signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter mod 16 (char height)
signal s_h_sync : std_logic; -- horizontal sync trigger
signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
 
--
-- signals for the charmaps Block RAM component...
signal s_charmaps_en : std_logic;
signal s_charmaps_en : std_logic;
signal s_charmaps_ADDR : std_logic_vector (c_INTCHMAP_ADDR_BUS_W - 1 downto 0);
signal s_charmaps_DO : std_logic_vector (c_INTCHMAP_DATA_BUS_W - 1 downto 0);
 
154,7 → 154,7
-- to manage the chars ram address and the ram ascii
signal s_chars_ram_addr : std_logic_vector(c_INTCHR_ADDR_BUS_W - 1 downto 0);
signal s_chars_ascii : std_logic_vector(c_INTCHR_DATA_BUS_W - 1 downto 0);
signal s_chars_EN_r : std_logic;
signal s_chars_EN_r : std_logic;
 
-- to manage the waveform ram address and data
signal s_waveform_ADDRB : std_logic_vector (c_WAVFRM_ADDR_BUS_W - 1 downto 0);
172,10 → 172,10
--
component charmaps_rom
port(
i_EN : in std_logic;
i_EN : in std_logic;
i_clock : in std_logic;
i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 16 x ascii code (W=8 x H=16 pixel)
o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8 bit char pixel
o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8 bit char pixel
);
end component;
 
192,17 → 192,17
--
component waveform_ram
port(
i_DIA : in std_logic_vector(15 downto 0);
i_DIA : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_WEA : in std_logic;
i_clockA : in std_logic;
i_ADDRA : in std_logic_vector(9 downto 0);
i_ADDRA : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
--o_DOA : OUT std_logic_vector(15 downto 0);
--
i_DIB : in std_logic_vector(15 downto 0);
i_DIB : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_WEB : in std_logic;
i_clockB : in std_logic;
i_ADDRB : in std_logic_vector(9 downto 0);
o_DOB : out std_logic_vector(15 downto 0)
i_ADDRB : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
o_DOB : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0)
);
end component;
 
210,7 → 210,7
port(
i_clock_rw : in std_logic;
i_EN_rw : in std_logic;
i_WE_rw : in std_logic_vector(3 downto 0);
i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_ADDR_rw : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_DI_rw : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
o_DI_rw : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
229,15 → 229,15
attribute U_SET of "u2_waveform_ram" : label is "u2_waveform_ram_uset";
 
-- to read some configuration params from the char ram
signal s_config_time : std_logic;
signal s_config_time : std_logic;
--
-- to manage the background and cursor colors
signal s_cursor_color : std_logic_vector(2 downto 0):= "000";
signal s_bg_color : std_logic_vector(2 downto 0):= "000";
signal s_cursor_color : std_logic_vector(2 downto 0) := "000";
signal s_bg_color : std_logic_vector(2 downto 0) := "000";
--
-- to manage the cursor position
signal s_cursor_x : std_logic_vector(10 downto 0);
signal s_cursor_y : std_logic_vector(9 downto 0);
signal s_cursor_x : std_logic_vector(c_H_COUNT_W - 1 downto 0);
signal s_cursor_y : std_logic_vector(c_V_COUNT_W - 1 downto 0);
 
begin
-- read config params from ram...
244,24 → 244,24
p_config : process(i_clk)
begin
if rising_edge(i_clk) then
case s_chars_ram_addr is
when c_BG_CUR_COLOR_ADDR => -- bg and curs color are on the same byte byte
s_config_time <= '1';
s_cursor_color <= s_chars_ascii(2 downto 0);
s_bg_color <= s_chars_ascii(5 downto 3);
when c_CURS_XY1 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
when c_CURS_XY2 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
when c_CURS_XY3 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
when others =>
s_config_time <= '0';
end case;
case s_chars_ram_addr is
when c_CFG_BG_CUR_COLOR_ADDR => -- bg and curs color are on the same byte byte
s_config_time <= '1';
s_cursor_color <= s_chars_ascii(2 downto 0);
s_bg_color <= s_chars_ascii(5 downto 3);
when c_CFG_CURS_XY1 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
when c_CFG_CURS_XY2 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
when c_CFG_CURS_XY3 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
when others =>
s_config_time <= '0';
end case;
end if;
end process;
 
291,8 → 291,8
-- v----- ascii code ------v v-- vert px mod 16 --v (chars are 16 pixel tall)
--s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0));
s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count_d_4);
s_charmaps_en <=
'1' when s_h_count(2 downto 0) = "111" -- each 8 h_count (chars are 8 pixel wide)
s_charmaps_en <=
'1' when s_h_count(2 downto 0) = "111" -- each 8 h_count (chars are 8 pixel wide)
else '0';
 
u1_charmaps_rom : charmaps_rom port map(
349,11 → 349,11
begin
if rising_edge(i_clk) then
if i_reset = '1' or s_v_count = c_V_PERIODln then -- sync reset
s_v_count <= (others => '0');
s_v_count_d_4 <= s_v_count(3 downto 0);
s_v_count <= (others => '0');
s_v_count_d_4 <= s_v_count(3 downto 0);
elsif s_h_sync_pulse = '1' then
s_v_count <= s_v_count + 1;
s_v_count_d_4 <= s_v_count(3 downto 0);
s_v_count <= s_v_count + 1;
s_v_count_d_4 <= s_v_count(3 downto 0);
end if;
end if;
end process;
/waveform_RAM.vhd
52,6 → 52,8
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
use work.yavga_pkg.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
59,24 → 61,24
 
entity waveform_RAM is
port (
i_DIA : in std_logic_vector(15 downto 0); -- 16-bit Data Input
i_DIA : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Input
-- i_DIPA : in std_logic; -- 2-bit parity Input
-- i_ENA : in std_logic; -- RAM Enable Input
i_WEA : in std_logic; -- Write Enable Input
i_WEA : in std_logic; -- Write Enable Input
-- i_SSRA : in std_logic; -- Synchronous Set/Reset Input
i_clockA : in std_logic; -- Clock
i_ADDRA : in std_logic_vector(9 downto 0); -- 10-bit Address Input
--o_DOA : out std_logic_vector(15 downto 0); -- 16-bit Data Output
i_clockA : in std_logic; -- Clock
i_ADDRA : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0); -- 10-bit Address Input
--o_DOA : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Output
-- o_DOPA : out std_logic -- 2-bit parity Output
--
i_DIB : in std_logic_vector(15 downto 0); -- 16-bit Data Input
i_DIB : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Input
-- i_DIPB : in std_logic; -- 2-bit parity Input
-- i_ENB : in std_logic; -- RAM Enable Input
i_WEB : in std_logic; -- Write Enable Input
i_WEB : in std_logic; -- Write Enable Input
-- i_SSRB : in std_logic; -- Synchronous Set/Reset Input
i_clockB : in std_logic; -- Clock
i_ADDRB : in std_logic_vector(9 downto 0); -- 10-bit Address Input
o_DOB : out std_logic_vector(15 downto 0) -- 16-bit Data Output
i_clockB : in std_logic; -- Clock
i_ADDRB : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0); -- 10-bit Address Input
o_DOB : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0) -- 16-bit Data Output
-- o_DOPB : out std_logic -- 2-bit parity Output
);
end waveform_RAM;
/yavga_pkg.vhd
14,6 → 14,7
-- chars address and data bus size
constant c_CHR_ADDR_BUS_W : integer := 11;
constant c_CHR_DATA_BUS_W : integer := 32;
constant c_CHR_WE_BUS_W : integer := 4;
 
-- internal used chars address and data bus size
constant c_INTCHR_ADDR_BUS_W : integer := 13;
40,6 → 41,7
c_H_BACKPORCHpx +
c_H_SYNCTIMEpx +
c_H_FRONTPORCHpx;
constant c_H_COUNT_W : integer := 11; -- = ceil(ln2(c_H_PERIODpx))
 
--
-- vertical timing signals (in lines count)
51,7 → 53,10
c_V_BACKPORCHln +
c_V_SYNCTIMEln +
c_V_FRONTPORCHln;
constant c_V_COUNT_W : integer := 10; -- = ceil(ln2(c_V_PERIODln))
 
constant c_X_W : integer := c_H_COUNT_W;
constant c_Y_W : integer := c_V_COUNT_W;
 
-- constant c_CHARS_WIDTH: std_logic_vector(2 downto 0) := "111";
-- constant c_CHARS_HEIGHT: std_logic_vector(3 downto 0) := "1111";
59,12 → 64,12
-- constant c_CHARS_ROWS: std_logic_vector(5 downto 0) := "100100";
 
-- to manage the background and cursor colors
constant c_BG_CUR_COLOR_ADDR : std_logic_vector(12 downto 0) := "0000001101100"; -- 108 BG:5..3 CUR:2..0
constant c_CFG_BG_CUR_COLOR_ADDR : std_logic_vector(12 downto 0) := "0000001101100"; -- 108 BG:5..3 CUR:2..0
 
-- to manage the cursor position
constant c_CURS_XY1 : std_logic_vector(12 downto 0) := "0000001101101"; -- 109
constant c_CURS_XY2 : std_logic_vector(12 downto 0) := "0000001101110"; -- 110
constant c_CURS_XY3 : std_logic_vector(12 downto 0) := "0000001101111"; -- 111
constant c_CFG_CURS_XY1 : std_logic_vector(12 downto 0) := "0000001101101"; -- 109
constant c_CFG_CURS_XY2 : std_logic_vector(12 downto 0) := "0000001101110"; -- 110
constant c_CFG_CURS_XY3 : std_logic_vector(12 downto 0) := "0000001101111"; -- 111
end yavga_pkg;
 
/charmaps_ROM.vhd
53,6 → 53,8
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
use work.yavga_pkg.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
64,10 → 66,10
-- i_DIP : in std_logic; -- 1-bit parity Input
-- i_WE : in std_logic; -- Write Enable Input
-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
i_EN : in std_logic; -- RAM Enable Input
i_clock : in std_logic; -- Clock
i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
i_EN : in std_logic; -- RAM Enable Input
i_clock : in std_logic; -- Clock
i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 11-bit Address Input
o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8-bit Data Output
-- o_DOP : out std_logic -- 1-bit parity Output
);
end charmaps_ROM;
156,7 → 158,7
INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000",
INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000",
INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000",
-- STOP REPLACE
-- STOP REPLACE
--
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
170,7 → 172,7
port map(
DI => (others => '1'), -- 8-bit Data Input
DIP => (others => '1'), -- 1-bit parity Input
EN => s_EN, -- RAM Enable Input
EN => s_EN, -- RAM Enable Input
WE => '0', -- Write Enable Input
SSR => '0', -- Synchronous Set/Reset Input
CLK => i_clock, -- Clock

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