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URL https://opencores.org/ocsvn/yavga/yavga/trunk

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    /yavga/trunk
    from Rev 7 to Rev 23
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Rev 7 → Rev 23

/vhdl/chars_RAM.vhd
70,6 → 70,7
i_SSR : in std_logic; -- Synchronous Set/Reset Input
 
i_clock_r : in std_logic; -- Read Clock
i_EN_r : in std_logic;
i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input
o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output
);
161,7 → 162,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => '1', -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
259,7 → 260,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => '1', -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
357,7 → 358,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => '1', -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
455,7 → 456,7
-- read
DIA => (others => '0'), -- 2-bit Data Input
DIPA => (others => '0'),
ENA => '1', -- RAM Enable Input
ENA => i_EN_r, -- RAM Enable Input
WEA => '0', -- Write Enable Input
SSRA => i_SSR, -- Synchronous Set/Reset Input
CLKA => i_clock_r, -- Clock
/vhdl/s3e_starter_1600k.vhd
72,10 → 72,6
port(
i_clk : in std_logic;
i_reset : in std_logic;
i_background : in std_logic;
i_cursor_color : in std_logic_vector(2 downto 0);
i_cursor_x : in std_logic_vector(10 downto 0);
i_cursor_y : in std_logic_vector(9 downto 0);
i_h_sync_en : in std_logic;
i_v_sync_en : in std_logic;
i_chr_addr : in std_logic_vector(10 downto 0);
85,6 → 81,7
i_chr_we : in std_logic_vector(3 downto 0);
i_chr_rst : in std_logic;
i_wav_d : in std_logic_vector(15 downto 0);
i_wav_clk : in std_logic;
i_wav_we : in std_logic;
i_wav_addr : in std_logic_vector(9 downto 0);
o_h_sync : out std_logic;
105,10 → 102,17
signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0');
signal s_vsync1 : std_logic;
 
signal s_chr_addr : std_logic_vector(10 downto 0) := (others => '0');
signal s_rnd : std_logic_vector(31 downto 0) := (others => '0');
signal s_chr_addr : std_logic_vector(10 downto 0);-- := (others => '0');
signal s_chr_data : std_logic_vector(31 downto 0);-- := (others => '0');
signal s_rnd : std_logic_vector(31 downto 0);-- := (others => '0');
signal s_chr_we : std_logic_vector(3 downto 0);
signal s_wav_addr : std_logic_vector(9 downto 0);
signal s_wav_d : std_logic_vector(15 downto 0);
signal s_mul : std_logic_vector(7 downto 0);
signal s_initialized : std_logic := '0';
attribute U_SET : string;
attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
122,10 → 126,6
u1_vga_ctrl : vga_ctrl port map(
i_clk => i_clk,
i_reset => '0',
i_background => '0',
i_cursor_color => "001",
i_cursor_x => "00101000000",
i_cursor_y => "0011000000",
o_h_sync => s_hsync,
o_v_sync => s_vsync,
i_h_sync_en => '1',
134,37 → 134,92
o_g => s_g,
o_b => s_b,
i_chr_addr => s_chr_addr, --B"000_0000_0000",
i_chr_data => s_rnd, --X"00000000",
i_chr_data => s_chr_data, --X"00000000",
o_chr_data => open,
i_chr_clk => i_clk,
i_chr_en => '1',
i_chr_we => s_chr_we,
i_chr_rst => '0',
i_wav_d => X"0000", --s_rnd(15 downto 0), --
i_wav_we => '0', --s_chr_we(0), --
i_wav_addr => B"00_0000_0000" --s_chr_addr(9 downto 0) --
i_wav_d => s_wav_d, --X"0000", --s_rnd(15 downto 0), --
i_wav_clk => i_clk,
i_wav_we => '0', --'0', -- '1',
i_wav_addr => s_wav_addr --B"00_0000_0000" --s_chr_addr(9 downto 0) --
);
s_wav_addr <= s_rnd(1 downto 0) & s_vsync_count;
s_mul <= s_vsync_count(3 downto 0) * s_vsync_count(3 downto 0);
s_wav_d <= B"000" & s_rnd(2 downto 0) & B"00" & s_mul;
--s_wav_d <= B"000" & "100" & B"00" & s_mul;
 
-- s_chr_data <= s_rnd;
-- p_write_chars : process(i_clk)
-- begin
-- if rising_edge(i_clk) then
-- -- during the sync time in order to avoid flickering
-- -- and each 128 vsync in order to stop for a while
-- -- will write random chars...
-- if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then
-- -- generate a pseudo random 32 bit number
-- s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0));
-- -- increment the address and write enable...
-- s_chr_addr <= s_chr_addr + 1;
-- s_chr_we <= "1111";
-- else
-- s_chr_addr <= s_chr_addr;
-- s_chr_we <= "0000";
-- s_rnd <= s_rnd;
-- end if;
-- end if;
-- end process;
-- cols cols
-- 00_01_02_03 ... 96_97_98_99
-- row_00 "00000000000" ... "00000011000"
-- row_01 "00000100000" ... "00000111000"
-- ... ... ...
-- row_37 "10010100000" ... "10010111000"
p_write_chars : process(i_clk)
begin
if rising_edge(i_clk) then
-- during the sync time in order to avoid flickering
-- and each 128 vsync in order to stop for a while
-- will write random chars...
if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then
-- generate a pseudo random 32 bit number
s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0));
-- increment the address and write enable...
s_chr_addr <= s_chr_addr + 1;
s_chr_we <= "1111";
if s_initialized = '0' then
case s_vsync_count(2 downto 0) is
when "000" => -- write ABCD
s_chr_we <= "1111";
s_chr_addr <= "00000000000";
s_chr_data <= "01000001" & "01000010" & "01000011" & "01000100";
when "001" => -- write EFGH
s_chr_we <= "1111";
s_chr_addr <= "00000011000";
s_chr_data <= "01000101" & "01000110" & "01000111" & "01001000";
when "010" => -- write IJKL
s_chr_we <= "1111";
s_chr_addr <= "00000100000";
s_chr_data <= "01001001" & "01001010" & "01001011" & "01001100";
when "011" => -- write MNOP
s_chr_we <= "1111";
s_chr_addr <= "10010100000";
s_chr_data <= "01001101" & "01001110" & "01001111" & "01010000";
when "100" => -- write QRST
s_chr_we <= "1111";
s_chr_addr <= "10010111000";
s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
when "101" => -- write config grid and cursor color
s_chr_we <= "1111";
s_chr_addr <= "00000011011"; -- 108 >> 2
-- ND bgColor grid,cur ND curs_x curs_y
s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
-- |--------108-------|-------109-------|----110-----|--111--|
s_initialized <= '1';
when others =>
s_chr_we <= (others => '0');
s_chr_addr <= (others => '1');
s_chr_data <= "11111111" & "11111101" & "11111100" & "11111110";
end case;
else
s_chr_addr <= s_chr_addr;
s_chr_we <= "0000";
s_rnd <= s_rnd;
s_chr_we <= (others => '0');
end if;
end if;
end process;
 
-- p_rnd_bit : process(i_clk)
-- variable v_rnd_fb : std_logic;
-- variable v_rnd : std_logic_vector(31 downto 0);
/vhdl/vga_ctrl.vhd
67,14 → 67,6
i_clk : in std_logic; -- must be 50MHz
i_reset : in std_logic;
 
-- background color (b/w)
i_background : in std_logic;
 
-- cross cursor
i_cursor_color : in std_logic_vector(2 downto 0);
i_cursor_x : in std_logic_vector(10 downto 0);
i_cursor_y : in std_logic_vector(9 downto 0);
 
-- vga horizontal and vertical sync
o_h_sync : out std_logic;
o_v_sync : out std_logic;
100,7 → 92,7
-- waveform RAM memory
i_wav_d : in std_logic_vector(15 downto 0);
i_wav_we : in std_logic;
--i_clockA : IN std_logic;
i_wav_clk : IN std_logic;
i_wav_addr : in std_logic_vector(9 downto 0) --;
--o_DOA : OUT std_logic_vector(15 downto 0)
);
172,14 → 164,15
--
signal s_h_count : std_logic_vector(10 downto 0); -- horizontal pixel counter
signal s_v_count : std_logic_vector(9 downto 0); -- verticalal line counter
signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter
signal s_h_sync : std_logic; -- horizontal sync trigger
signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
 
--
-- signals for the charmaps Block RAM component...
signal s_charmaps_en : std_logic;
signal s_charmaps_ADDR : std_logic_vector (10 downto 0);
signal s_charmaps_DO : std_logic_vector (7 downto 0);
signal s_charmaps_DO_l : std_logic_vector (7 downto 0);
 
--
-- to manage the outside display region's blanking
187,18 → 180,15
--
 
--
-- to manage the cursor position
signal s_cursor_x : std_logic_vector(10 downto 0);
signal s_cursor_y : std_logic_vector(9 downto 0);
 
--
-- to manage the chars ram address and th ram ascii
-- to manage the chars ram address and the ram ascii
signal s_chars_ram_addr : std_logic_vector(12 downto 0);
signal s_chars_ascii : std_logic_vector(7 downto 0);
signal s_chars_EN_r : std_logic;
 
--
-- to manage the waveform ram address and data
signal s_waveform_ADDRB : std_logic_vector (9 downto 0);
signal s_waveform_DOB : std_logic_vector (15 downto 0);
signal s_waveform_DOB : std_logic_vector (15 downto 0);
 
 
-- charmaps
212,6 → 202,7
--
component charmaps_rom
port(
i_EN : in std_logic;
i_clock : in std_logic;
i_ADDR : in std_logic_vector(10 downto 0); -- 16 x ascii code (W=8 x H=16 pixel)
o_DO : out std_logic_vector(7 downto 0) -- 8 bit char pixel
255,6 → 246,7
o_DI_rw : out std_logic_vector(31 downto 0);
i_SSR : in std_logic;
i_clock_r : in std_logic;
i_EN_r : in std_logic;
i_ADDR_r : in std_logic_vector(12 downto 0);
o_DO_r : out std_logic_vector(7 downto 0)
);
266,10 → 258,54
attribute U_SET of "u1_charmaps_rom" : label is "u1_charmaps_rom_uset";
attribute U_SET of "u2_waveform_ram" : label is "u2_waveform_ram_uset";
 
-- to read some configuration params from the char ram
signal s_config_time : std_logic;
--
-- to manage the background and cursor colors
constant c_BG_CUR_COLOR_ADDR : std_logic_vector(12 downto 0) := "0000001101100"; -- 108 BG:5..3 CUR:2..0
signal s_cursor_color : std_logic_vector(2 downto 0):= "000";
signal s_bg_color : std_logic_vector(2 downto 0):= "000";
--
-- to manage the cursor position
constant c_CURS_XY1 : std_logic_vector(12 downto 0) := "0000001101101"; -- 109
constant c_CURS_XY2 : std_logic_vector(12 downto 0) := "0000001101110"; -- 110
constant c_CURS_XY3 : std_logic_vector(12 downto 0) := "0000001101111"; -- 111
signal s_cursor_x : std_logic_vector(10 downto 0);
signal s_cursor_y : std_logic_vector(9 downto 0);
 
begin
-- read config params from ram...
p_config : process(i_clk)
begin
if rising_edge(i_clk) then
case s_chars_ram_addr is
when c_BG_CUR_COLOR_ADDR =>
s_config_time <= '1';
s_cursor_color <= s_chars_ascii(2 downto 0);
s_bg_color <= s_chars_ascii(5 downto 3);
when c_CURS_XY1 =>
s_config_time <= '1';
s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
when c_CURS_XY2 =>
s_config_time <= '1';
s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
when c_CURS_XY3 =>
s_config_time <= '1';
s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
when others =>
s_config_time <= '0';
end case;
end if;
end process;
 
-- enable the ram both
-- - during the display time
-- - to read configuration params
s_chars_EN_r <= s_display or s_config_time;
 
-- modify the chars_ram address
s_chars_ram_addr <= s_v_count(9 downto 4) & s_h_count(9 downto 3);
 
u0_chars_RAM : chars_RAM port map(
i_clock_rw => i_chr_clk,
i_EN_rw => i_chr_en,
278,62 → 314,47
i_DI_rw => i_chr_data,
o_DI_rw => o_chr_data,
i_SSR => i_chr_rst,
i_clock_r => i_clk,
i_clock_r => not i_clk,
i_EN_r => s_chars_EN_r,
i_ADDR_r => s_chars_ram_addr,
o_DO_r => s_chars_ascii
);
 
 
-- modify the charmaps address (each 8 s_h_count - chars are 8 pixel tall)
-- v----- ascii code ------v v-- vert px mod 16 --v (chars are 8 pixel tall)
--s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0));
s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count_d_4);
s_charmaps_en <=
'1' when s_h_count(2 downto 0) = "111" -- each 8 h_count (chars are 8 pixel wide)
else '0';
 
u1_charmaps_rom : charmaps_rom port map(
i_clock => i_clk,
i_en => s_charmaps_en,
i_clock => not i_clk,
i_ADDR => s_charmaps_ADDR,
o_DO => s_charmaps_DO
);
 
-- modify the charmaps address
p_MGM_CHARMAPS_ADDR : process(i_clk) --, i_reset) --, s_v_count, i_cursor_color)
begin
if rising_edge(i_clk) then
if i_reset = '1' then -- sync reset
s_charmaps_ADDR <= "01000000000"; -- (others => '0');
else
if (s_h_count(2 downto 0) = "110") then -- each 8 h_count
s_charmaps_DO_l <= s_charmaps_DO;
end if;
-- here start char 'a' ---v v----- ascii code ------v v-- vert char row --v
--s_charmaps_ADDR <= "01000000000" + ( s_h_count(9 downto 3) & s_v_count(3 downto 0) );
s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0));
-- here start char 'a' ---^ ^----- ascii code ------^ ^-- vert char row --^
end if;
end if;
end process;
 
 
 
-- modify the waveform address
s_waveform_ADDRB <= s_h_count(9 downto 0);
u2_waveform_ram : waveform_ram port map(
i_DIA => i_wav_d,
i_WEA => i_wav_we,
--i_clockA => i_clockA,
i_clockA => i_clk,
i_clockA => i_wav_clk,
i_ADDRA => i_wav_addr,
--o_DOA => o_DOA,
--
i_DIB => "1111111111111111",
i_WEB => '0',
i_clockB => i_clk,
-- i_ADDRB => s_waveform_ADDRB,
i_ADDRB => s_waveform_ADDRB, --s_h_count(9 downto 0),
i_clockB => not i_clk,
i_ADDRB => s_waveform_ADDRB,
o_DOB => s_waveform_DOB
);
 
p_WaveFormAddr : process (i_clk)
begin
if rising_edge(i_clk) then
s_waveform_ADDRB <= s_h_count(9 downto 0);
end if;
end process;
 
-- generate a single clock pulse on hsync falling
p_pulse_on_hsync_falling : process(i_clk)
variable v_h_sync1 : std_logic;
begin
344,10 → 365,6
end process;
 
 
-- set the cursor position
s_cursor_x <= i_cursor_x; -- 400
s_cursor_y <= i_cursor_y; -- 300
 
-- control the reset, increment and overflow of the horizontal pixel count
p_H_PX_COUNT : process(i_clk) --, i_reset)
begin
361,14 → 378,16
end process;
 
 
 
-- control the reset, increment and overflow of the vertical pixel count
p_V_LN_COUNT : process(i_clk)
begin
if rising_edge(i_clk) then
if i_reset = '1' or s_v_count = c_V_PERIODln then -- sync reset
s_v_count <= (others => '0');
s_v_count_d_4 <= s_v_count(3 downto 0);
elsif s_h_sync_pulse = '1' then
s_v_count <= s_v_count + 1;
s_v_count_d_4 <= s_v_count(3 downto 0);
end if;
end if;
end process;
387,6 → 406,7
o_h_sync <= s_h_sync and i_h_sync_en;
 
 
-- set the vertical sync high time and low time according to the constants
p_MGM_V_SYNC : process(i_clk) --, i_reset)
begin
--if falling_edge(i_clk) then
400,6 → 420,7
end if;
end process;
 
 
-- asserts the blaking signal (active low)
p_MGM_BLANK : process (i_clk) --, i_reset)
begin
415,8 → 436,8
end process;
 
 
-- generates the r g b signals and show the green cursor
p_MGM_RGB : process (i_clk) --, i_reset) --, i_cursor_color, s_display)
-- generates the r g b signals showing chars, grid and "cross cursor"
p_MGM_RGB : process (i_clk)
variable v_previous_pixel : std_logic_vector(9 downto 0) := "0100101100";
begin
if rising_edge(i_clk) then -- not async reset
433,9 → 454,9
)
and (s_v_count(9) = '0') -- < 512
then -- draw the cursor and/or WaveForm Grid references
o_r <= i_cursor_color(2);
o_g <= i_cursor_color(1);
o_b <= i_cursor_color(0);
o_r <= s_cursor_color(2);
o_g <= s_cursor_color(1);
o_b <= s_cursor_color(0);
elsif
((s_v_count(9 downto 0) >= s_waveform_DOB(9 downto 0)) and
(s_v_count(9 downto 0) <= v_previous_pixel)
451,23 → 472,20
--if s_v_count > 512 then
--FULL_SCREEN if (s_v_count(9) = '1') then -- >= 512
case (s_h_count(2 downto 0)) is
when "000" => o_g <= s_charmaps_DO_l(7) xor i_background;
when "001" => o_g <= s_charmaps_DO_l(6) xor i_background;
when "010" => o_g <= s_charmaps_DO_l(5) xor i_background;
when "011" => o_g <= s_charmaps_DO_l(4) xor i_background;
when "100" => o_g <= s_charmaps_DO_l(3) xor i_background;
when "101" => o_g <= s_charmaps_DO_l(2) xor i_background;
when "110" => o_g <= s_charmaps_DO_l(1) xor i_background;
when "111" => o_g <= s_charmaps_DO_l(0) xor i_background;
when "000" => o_g <= s_charmaps_DO(7) xor s_bg_color(1);
when "001" => o_g <= s_charmaps_DO(6) xor s_bg_color(1);
when "010" => o_g <= s_charmaps_DO(5) xor s_bg_color(1);
when "011" => o_g <= s_charmaps_DO(4) xor s_bg_color(1);
when "100" => o_g <= s_charmaps_DO(3) xor s_bg_color(1);
when "101" => o_g <= s_charmaps_DO(2) xor s_bg_color(1);
when "110" => o_g <= s_charmaps_DO(1) xor s_bg_color(1);
when "111" => o_g <= s_charmaps_DO(0) xor s_bg_color(1);
when others => o_g <= 'X';
--when others => o_g <= i_background;
end case;
--FULL_SCREEN else
--FULL_SCREEN o_g <= i_background;
--FULL_SCREEN end if;
o_r <= i_background;
--o_g <= i_background;
o_b <= i_background;
 
o_r <= s_bg_color(2);
--o_g <= s_bg_color(1);
o_b <= s_bg_color(0);
end if;
else -- blank zone
-- the blanking zone
/vhdl/charmaps_ROM.vhd
62,9 → 62,9
port (
-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
-- i_DIP : in std_logic; -- 1-bit parity Input
-- i_EN : in std_logic; -- RAM Enable Input
-- i_WE : in std_logic; -- Write Enable Input
-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
i_EN : in std_logic; -- RAM Enable Input
i_clock : in std_logic; -- Clock
i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
73,8 → 73,9
end charmaps_ROM;
 
architecture rtl of charmaps_ROM is
 
signal s_EN : std_logic;
begin
s_EN <= i_EN;
-- charmaps
-- |------| |-----------------|
-- | P | | D D D D D D D D |
90,6 → 91,7
INIT => B"000000000", -- Value of output RAM registers at startup
SRVAL => B"000000000", -- Ouput value upon SSR assertion
--
-- START REPLACE HERE THE OUTPUT FROM convert.sh
INIT_00 => X"000000FF0000FF0000FF0000FF00000000000000000000000000000000000000",
INIT_01 => X"0000242424242424242424242424000000000000FF0000FF0000FF0000FF0000",
INIT_02 => X"0000929292929292929292929292000000004949494949494949494949490000",
154,6 → 156,7
INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000",
INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000",
INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000",
-- STOP REPLACE
--
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
167,7 → 170,7
port map(
DI => (others => '1'), -- 8-bit Data Input
DIP => (others => '1'), -- 1-bit parity Input
EN => '1', -- RAM Enable Input
EN => s_EN, -- RAM Enable Input
WE => '0', -- Write Enable Input
SSR => '0', -- Synchronous Set/Reset Input
CLK => i_clock, -- Clock
/charmaps/charmaps_ROM.vhd
62,9 → 62,9
port (
-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
-- i_DIP : in std_logic; -- 1-bit parity Input
-- i_EN : in std_logic; -- RAM Enable Input
-- i_WE : in std_logic; -- Write Enable Input
-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
i_EN : in std_logic; -- RAM Enable Input
i_clock : in std_logic; -- Clock
i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
73,8 → 73,9
end charmaps_ROM;
 
architecture rtl of charmaps_ROM is
 
signal s_EN : std_logic;
begin
s_EN <= i_EN;
-- charmaps
-- |------| |-----------------|
-- | P | | D D D D D D D D |
111,7 → 112,7
port map(
DI => (others => '1'), -- 8-bit Data Input
DIP => (others => '1'), -- 1-bit parity Input
EN => '1', -- RAM Enable Input
EN => s_EN, -- RAM Enable Input
WE => '0', -- Write Enable Input
SSR => '0', -- Synchronous Set/Reset Input
CLK => i_clock, -- Clock

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