Subversion Repositories yavga

/tags/yavga-0.8.2/trunk/charmaps/convert.sh

tags/yavga-0.8.2/trunk/charmaps/convert.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/yavga-0.8.2/trunk/charmaps/README.txt =================================================================== --- tags/yavga-0.8.2/trunk/charmaps/README.txt (nonexistent) +++ tags/yavga-0.8.2/trunk/charmaps/README.txt (revision 14) @@ -0,0 +1,17 @@ +######################################################## +#### This file is part of the yaVGA project #### +#### http://www.opencores.org/?do=project&who=yavga #### +######################################################## + +FIles: + +charmaps_ROM.vhd + chdl chunk to be completed with the output of convert.sh + +chars.map + the char maps (- = pixel off ; @ = pixel on) + +convert.sh + this file read the chars.map and write to to the standard output + a vhdl chunk to insert in the charmaps_ROM.vhd + Index: tags/yavga-0.8.2/trunk/charmaps/chars.map =================================================================== --- tags/yavga-0.8.2/trunk/charmaps/chars.map (nonexistent) +++ tags/yavga-0.8.2/trunk/charmaps/chars.map (revision 14) @@ -0,0 +1,2353 @@ +################################################################################ +#### #### +#### This file is part of the yaVGA project #### +#### http://www.opencores.org/?do=project&who=yavga #### +#### #### +#### Description #### +#### Implementation of yaVGA IP core #### +#### #### +#### To Do: #### +#### #### +#### #### +#### Author(s): #### +#### Sandro Amato, sdroamt@netscape.net #### +#### #### +################################################################################ +#### #### +#### Copyright (c) 2009, Sandro Amato #### +#### All rights reserved. #### +#### #### +#### Redistribution and use in source and binary forms, with or without #### +#### modification, are permitted provided that the following conditions #### +#### are met: #### +#### #### +#### * Redistributions of source code must retain the above #### +#### copyright notice, this list of conditions and the #### +#### following disclaimer. #### +#### * Redistributions in binary form must reproduce the above #### +#### copyright notice, this list of conditions and the #### +#### following disclaimer in the documentation and/or other #### +#### materials provided with the distribution. #### +#### * Neither the name of SANDRO AMATO nor the names of its #### +#### contributors may be used to endorse or promote products #### +#### derived from this software without specific prior written #### +#### permission. #### +#### #### +#### THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS #### +#### "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT #### +#### LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS #### +#### FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #### +#### COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, #### +#### INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, #### +#### BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; #### +#### LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER #### +#### CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT #### +#### LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN #### +#### ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE #### +#### POSSIBILITY OF SUCH DAMAGE. #### +################################################################################ +# +# +# qqq +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# qqq +-------- +-------- +-------- +@@@@@@@@ +-------- +-------- +@@@@@@@@ +-------- +-------- +@@@@@@@@ +-------- +-------- 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+-------- +-@@--@@- +-@@--@@- +-@@--@@- +-@@--@@- +-------- +-------- +-------- +# +# qqq +-------- +-------- +@@@@@@@@ +@--@@--@ +@--@@--@ +@--@@--@ +@--@@--@ +@@@@@@@@ +@@@@@@@@ +@--@@--@ +@--@@--@ +@--@@--@ +@--@@--@ +@@@@@@@@ +-------- +-------- +# +# qqq +-------- +-------- +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +-------- +-------- +# +# qqq +-------- +-------- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +-------- +-------- +# +# qqq +-------- +-------- +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# qqq +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +-------- +-------- +# +# qqq +-------- +-------- +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +----@@@@ +-------- +-------- +# +# qqq +-------- +-------- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +@@@@---- +-------- +-------- +# +# qqq +-------- +-------- +-------- +-@@@@@@- +-@----@- +-@----@- +-@----@- +-@----@- +-@----@- +-@----@- +-@----@- +-@----@- +-@@@@@@- +-------- +-------- +-------- +# +# qqq +-------- +-------- +@@@@@@@@ +@------@ +@------@ +@------@ +@------@ +@------@ +@------@ +@------@ +@------@ +@------@ +@------@ +@@@@@@@@ +-------- +-------- +# +# qqq +-------- +-------- +-@--@--@ +--@--@-- +-@--@--@ +--@--@-- +-@--@--@ +--@--@-- +-@--@--@ +--@--@-- +-@--@--@ +--@--@-- +-@--@--@ +--@--@-- +-------- +-------- +# +# qqq +-------- +-------- +@--@--@- +--@--@-- +@--@--@- +--@--@-- +@--@--@- +--@--@-- +@--@--@- +--@--@-- +@--@--@- +--@--@-- +@--@--@- +--@--@-- +-------- +-------- +# +# qqq +-------- +-------- +@--@--@- +-@--@--@ +@--@--@- +-@--@--@ +@--@--@- +-@--@--@ +@--@--@- +-@--@--@ +@--@--@- +-@--@--@ +@--@--@- +-@--@--@ +-------- +-------- +# +# qqq +-------- +-------- +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +-------- +-------- +# +# qqq +-------- +-------- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-@-@-@-@ +@-@-@-@- +-------- +-------- +# +# qqq +-------- +-------- +@-@@-@@- +@@-@@-@@ +@-@@-@@- +@@-@@-@@ +@-@@-@@- +@@-@@-@@ +@-@@-@@- +@@-@@-@@ +@-@@-@@- +@@-@@-@@ +@-@@-@@- +@@-@@-@@ +-------- +-------- +# +# qqq +-------- +-------- +-@@-@@-@ +@@-@@-@@ +-@@-@@-@ +@@-@@-@@ +-@@-@@-@ +@@-@@-@@ +-@@-@@-@ +@@-@@-@@ +-@@-@@-@ +@@-@@-@@ +-@@-@@-@ +@@-@@-@@ +-------- +-------- +# +# qqq +-------- +-------- +-@@-@@-@ +@-@@-@@- +-@@-@@-@ +@-@@-@@- +-@@-@@-@ +@-@@-@@- +-@@-@@-@ +@-@@-@@- +-@@-@@-@ +@-@@-@@- +-@@-@@-@ +@-@@-@@- +-------- +-------- +# +# qqq +-------- +-------- +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +@@@@@@@@ +-------- +-------- +# +# blank_map= 000000000000000000000000 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# !_map= 101010101010101000001000 +-------- +-------- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +-------- +-------- +---@---- +-------- +-------- +-------- +# +# "_map= 444444444400000000000000 +-------- +-------- +-@---@-- +-@---@-- +-@---@-- +-@---@-- +-@---@-- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# #_map= 4444FE4444444444FE444400 +-------- +-------- +-@---@-- +-@---@-- +@@@@@@@- +-@---@-- +-@---@-- +-@---@-- +-@---@-- +-@---@-- +@@@@@@@- +-@---@-- +-@---@-- +-------- +-------- +-------- +# +# $_map= 7C929090907C121212927C00 +-------- +-------- +-@@@@@-- +@--@--@- +@--@---- +@--@---- +@--@---- +-@@@@@-- +---@--@- +---@--@- +---@--@- +@--@--@- +-@@@@@-- +-------- +-------- +-------- +# +# %_map= 609092640810204C92120C00 +-------- +-------- +-@@----- +@--@---- +@--@--@- +-@@--@-- +----@--- +---@---- +--@----- +-@--@@-- +@--@--@- +---@--@- +----@@-- +-------- +-------- +-------- +# +# &_map= 304888889070508A84847A00 +-------- +-------- +--@@---- +-@--@--- +@---@--- +@---@--- +@--@---- +-@@@---- +-@-@---- +@---@-@- +@----@-- +@----@-- +-@@@@-@- +-------- +-------- +-------- +# +# '_map= 101010101000000000000000 +-------- +-------- +---@---- +---@---- +---@---- +---@---- +---@---- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# (_map= 102020404040404020201000 +-------- +-------- +---@---- +--@----- +--@----- +-@------ +-@------ +-@------ +-@------ +-@------ +--@----- +--@----- +---@---- +-------- +-------- +-------- +# +# )_map= 100808040404040408081000 +-------- +-------- +---@---- +----@--- +----@--- +-----@-- +-----@-- +-----@-- +-----@-- +-----@-- +----@--- +----@--- +---@---- +-------- +-------- +-------- +# +# *_map= 9292545438FE385454929200 +-------- +-------- +@--@--@- +@--@--@- +-@-@-@-- +-@-@-@-- +--@@@--- +@@@@@@@- +--@@@--- +-@-@-@-- +-@-@-@-- +@--@--@- +@--@--@- +-------- +-------- +-------- +# +# +_map= 0010101010FE101010100000 +-------- +-------- +-------- +---@---- +---@---- +---@---- +---@---- +@@@@@@@- +---@---- +---@---- +---@---- +---@---- +-------- +-------- +-------- +-------- +# +# ,_map= 000000000000000808102000 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +----@--- +----@--- +---@---- +--@----- +-------- +-------- +-------- +# +# -_map= 0000000000FE000000000000 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +@@@@@@@- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# ._map= 000000000000001818000000 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +---@@--- +---@@--- +-------- +-------- +-------- +-------- +-------- +# +# /_map= 000002040810204080000000 +-------- +-------- +-------- +-------- +------@- +-----@-- +----@--- +---@---- +--@----- +-@------ +@------- +-------- +-------- +-------- +-------- +-------- +# +# 0_map= 384482828A92A28282443800 +-------- +-------- +--@@@--- +-@---@-- +@-----@- +@-----@- +@---@-@- +@--@--@- +@-@---@- +@-----@- +@-----@- +-@---@-- +--@@@--- +-------- +-------- +-------- +# +# 1_map= 103050101010101010103800 +-------- +-------- +---@---- +--@@---- +-@-@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +--@@@--- +-------- +-------- +-------- +# +# 2_map= 7C820202027C80808080FE00 +-------- +-------- +-@@@@@-- +@-----@- +------@- +------@- +------@- +-@@@@@-- +@------- +@------- +@------- +@------- +@@@@@@@- +-------- +-------- +-------- +# +# 3_map= 7C820202027C020202827C00 +-------- +-------- +-@@@@@-- +@-----@- +------@- +------@- +------@- +-@@@@@-- +------@- +------@- +------@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# 4_map= 081828488888FE0808081C00 +-------- +-------- +----@--- +---@@--- +--@-@--- +-@--@--- +@---@--- +@---@--- +@@@@@@@- +----@--- +----@--- +----@--- +---@@@-- +-------- +-------- +-------- +# +# 5_map= FE808080807C020202827C00 +-------- +-------- +@@@@@@@- +@------- +@------- +@------- +@------- +-@@@@@-- +------@- +------@- +------@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# 6_map= 7E808080807C828282827C00 +-------- +-------- +-@@@@@@- +@------- +@------- +@------- +@------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# 7_map= FE0202040810101010103800 +-------- +-------- +@@@@@@@- +------@- +------@- +-----@-- +----@--- +---@---- +---@---- +---@---- +---@---- +---@---- +--@@@--- +-------- +-------- +-------- +# +# 8_map= 7C828282827C828282827C00 +-------- +-------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# 9_map= 7C828282827C02020202FC00 +-------- +-------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +------@- +------@- +------@- +------@- +@@@@@@-- +-------- +-------- +-------- +# +# :_map= 000018180000001818000000 +-------- +-------- +-------- +-------- +---@@--- +---@@--- +-------- +-------- +-------- +---@@--- +---@@--- +-------- +-------- +-------- +-------- +-------- +# +# ;_map= 000018180000000808102000 +-------- +-------- +-------- +-------- +---@@--- +---@@--- +-------- +-------- +-------- +----@--- +----@--- +---@---- +--@----- +-------- +-------- +-------- +# +# <_map= 0000020C30C0300C02000000 +-------- +-------- +-------- +-------- +------@- +----@@-- +--@@---- +@@------ +--@@---- +----@@-- +------@- +-------- +-------- +-------- +-------- +-------- +# +# =_map= 0000FE0000000000FE000000 +-------- +-------- +-------- +-------- +@@@@@@@- +-------- +-------- +-------- +-------- +-------- +@@@@@@@- +-------- +-------- +-------- +-------- +-------- +# +# >_map= 000080601806186080000000 +-------- +-------- +-------- +-------- +@------- +-@@----- +---@@--- +-----@@- +---@@--- +-@@----- +@------- +-------- +-------- +-------- +-------- +-------- +# +# ?_map= 384482820204081010001000 +-------- +-------- +--@@@--- +-@---@-- +@-----@- +@-----@- +------@- +-----@-- +----@--- +---@---- +---@---- +-------- +---@---- +-------- +-------- +-------- +# +# @_map= 384482829EA2A29E80423C00 +-------- +-------- +--@@@--- +-@---@-- +@-----@- +@-----@- +@--@@@@- +@-@---@- +@-@---@- +@--@@@@- +@------- +-@----@- +--@@@@-- +-------- +-------- +-------- +# +# A_map= 10282828447C444482828200 +-------- +-------- +---@---- +--@-@--- +--@-@--- +--@-@--- +-@---@-- +-@@@@@-- +-@---@-- +-@---@-- +@-----@- +@-----@- +@-----@- +-------- +-------- +-------- +# +# B_map= FC82828284F884828282FC00 +-------- +-------- +@@@@@@-- +@-----@- +@-----@- +@-----@- +@----@-- +@@@@@--- +@----@-- +@-----@- +@-----@- +@-----@- +@@@@@@-- +-------- +-------- +-------- +# +# C_map= 7C8280808080808080827C00 +-------- +-------- +-@@@@@-- +@-----@- +@------- +@------- +@------- +@------- +@------- +@------- +@------- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# D_map= F0888484828282828484F800 +-------- +-------- +@@@@---- +@---@--- +@----@-- +@----@-- +@-----@- +@-----@- +@-----@- +@-----@- +@----@-- +@----@-- +@@@@@--- +-------- +-------- +-------- +# +# E_map= FE80808080FC80808080FE00 +-------- +-------- +@@@@@@@- +@------- +@------- +@------- +@------- +@@@@@@-- +@------- +@------- +@------- +@------- +@@@@@@@- +-------- +-------- +-------- +# +# F_map= FE80808080FC808080808000 +-------- +-------- +@@@@@@@- +@------- +@------- +@------- +@------- +@@@@@@-- +@------- +@------- +@------- +@------- +@------- +-------- +-------- +-------- +# +# G_map= 7C828080809E828282827C00 +-------- +-------- +-@@@@@-- +@-----@- +@------- +@------- +@------- +@--@@@@- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# H_map= 82828282827C828282828200 +-------- +-------- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +-------- +-------- +-------- +# +# I_map= 381010101010101010103800 +-------- +-------- +--@@@--- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +--@@@--- +-------- +-------- +-------- +# +# J_map= 1C0808080808080888887000 +-------- +-------- +---@@@-- +----@--- +----@--- +----@--- +----@--- +----@--- +----@--- +----@--- +@---@--- +@---@--- +-@@@---- +-------- +-------- +-------- +# +# K_map= 8282838388F0888484828200 +-------- +-------- +@-----@- +@-----@- +@----@-- +@----@-- +@---@--- +@@@@---- +@---@--- +@----@-- +@----@-- +@-----@- +@-----@- +-------- +-------- +-------- +# +# L_map= 80808080808080808080FE00 +-------- +-------- +@------- +@------- +@------- +@------- +@------- +@------- +@------- +@------- +@------- +@------- +@@@@@@@- +-------- +-------- +-------- +# +# M_map= 82C6AAAAAA92928282828200 +-------- +-------- +@-----@- +@@---@@- +@-@-@-@- +@-@-@-@- +@-@-@-@- +@--@--@- +@--@--@- +@-----@- +@-----@- +@-----@- +@-----@- +-------- +-------- +-------- +# +# N_map= 82C2A2A2A2928A8A8A868200 +-------- +-------- +@-----@- +@@----@- +@-@---@- +@-@---@- +@-@---@- +@--@--@- +@---@-@- +@---@-@- +@---@-@- +@----@@- +@-----@- +-------- +-------- +-------- +# +# O_map= 7C8282828282828282827C00 +-------- +-------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# P_map= 7C82828282FC808080808000 +-------- +-------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +@@@@@@-- +@------- +@------- +@------- +@------- +@------- +-------- +-------- +-------- +# +# Q_map= 7C828282828282B28A847A00 +-------- +-------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-@@--@- +@---@-@- +@----@-- +-@@@@-@- +-------- +-------- +-------- +# +# R_map= 7C82828282FCA09088848200 +-------- +-------- +-@@@@@-- +@-----@- +@-----@- +@-----@- +@-----@- +@@@@@@-- +@-@----- +@--@---- +@---@--- +@----@-- +@-----@- +-------- +-------- +-------- +# +# S_map= 7C828080807C020202827C00 +-------- +-------- +-@@@@@-- +@-----@- +@------- +@------- +@------- +-@@@@@-- +------@- +------@- +------@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# T_map= FE9210101010101010101000 +-------- +-------- +@@@@@@@- +@--@--@- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +-------- +-------- +-------- +# +# U_map= 828282828282828282827C00 +-------- +-------- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# V_map= 828282444444282828191900 +-------- +-------- +@-----@- +@-----@- +@-----@- +-@---@-- +-@---@-- +-@---@-- +--@-@--- +--@-@--- +--@-@--- +---@---- +---@---- +-------- +-------- +-------- +# +# W_map= 828282829292AAAAAAC68200 +-------- +-------- +@-----@- +@-----@- +@-----@- +@-----@- +@--@--@- +@--@--@- +@-@-@-@- +@-@-@-@- +@-@-@-@- +@@---@@- +@-----@- +-------- +-------- +-------- +# +# X_map= 828244442838284444828200 +-------- +-------- +@-----@- +@-----@- +-@---@-- +-@---@-- +--@-@--- +--@@@--- +--@-@--- +-@---@-- +-@---@-- +@-----@- +@-----@- +-------- +-------- +-------- +# +# Y_map= 828244442828101010101000 +-------- +-------- +@-----@- +@-----@- +-@---@-- +-@---@-- +--@-@--- +--@-@--- +---@---- +---@---- +---@---- +---@---- +---@---- +-------- +-------- +-------- +# +# Z_map= FE820404083820404082FE00 +-------- +-------- +@@@@@@@- +@-----@- +-----@-- +-----@-- +----@--- +--@@@--- +--@----- +-@------ +-@------ +@-----@- +@@@@@@@- +-------- +-------- +-------- +# +# [_map= 382020202020202020203800 +-------- +-------- +--@@@--- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@@@--- +-------- +-------- +-------- +# +# _map= 000080402010080402000000 +-------- +-------- +-------- +-------- +@------- +-@------ +--@----- +---@---- +----@--- +-----@-- +------@- +-------- +-------- +-------- +-------- +-------- +# +# ]_map= 380808080808080808083800 +-------- +-------- +--@@@--- +----@--- +----@--- +----@--- +----@--- +----@--- +----@--- +----@--- +----@--- +----@--- +--@@@--- +-------- +-------- +-------- +# +# ^_map= 001028448200000000000000 +-------- +-------- +-------- +---@---- +--@-@--- +-@---@-- +@-----@- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# __map= 00000000000000000000FE00 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +@@@@@@@- +-------- +-------- +-------- +# +# `_map= 202010100800000000000000 +-------- +-------- +--@----- +--@----- +---@---- +---@---- +----@--- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# a_map= 000000003AC6828282C63A00 +-------- +-------- +-------- +-------- +-------- +-------- +--@@@-@- +@@---@@- +@-----@- +@-----@- +@-----@- +@@---@@- +--@@@-@- +-------- +-------- +-------- +# +# b_map= 80808080B8C6828282C6B800 +-------- +-------- +@------- +@------- +@------- +@------- +@-@@@--- +@@---@@- +@-----@- +@-----@- +@-----@- +@@---@@- +@-@@@--- +-------- +-------- +-------- +# +# c_map= 000000003CC2808080C23C00 +-------- +-------- +-------- +-------- +-------- +-------- +--@@@@-- +@@----@- +@------- +@------- +@------- +@@----@- +--@@@@-- +-------- +-------- +-------- +# +# d_map= 020202023AC6828282C63A00 +-------- +-------- +------@- +------@- +------@- +------@- +--@@@-@- +@@---@@- +@-----@- +@-----@- +@-----@- +@@---@@- +--@@@-@- +-------- +-------- +-------- +# +# e_map= 0000000038C682FC80C63800 +-------- +-------- +-------- +-------- +-------- +-------- +--@@@--- +@@---@@- +@-----@- +@@@@@@-- +@------- +@@---@@- +--@@@--- +-------- +-------- +-------- +# +# f_map= 3C428080F880808080808000 +-------- +-------- +--@@@@-- +-@----@- +@------- +@------- +@@@@@--- +@------- +@------- +@------- +@------- +@------- +@------- +-------- +-------- +-------- +# +# g_map= 0000000038C6827E02C63800 +-------- +-------- +-------- +-------- +-------- +-------- +--@@@--- +@@---@@- +@-----@- +-@@@@@@- +------@- +@@---@@- +--@@@--- +-------- +-------- +-------- +# +# h_map= 80808080B8C6828282828200 +-------- +-------- +@------- +@------- +@------- +@------- +@-@@@--- +@@---@@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +-------- +-------- +-------- +# +# i_map= 001000001010101010120C00 +-------- +-------- +-------- +---@---- +-------- +-------- +---@---- +---@---- +---@---- +---@---- +---@---- +---@--@- +----@@-- +-------- +-------- +-------- +# +# j_map= 000400000404040404887000 +-------- +-------- +-------- +-----@-- +-------- +-------- +-----@-- +-----@-- +-----@-- +-----@-- +-----@-- +@---@--- +-@@@---- +-------- +-------- +-------- +# +# k_map= 0080808086B8C0B088848200 +-------- +-------- +-------- +@------- +@------- +@------- +@----@@- +@-@@@--- +@@------ +@-@@---- +@---@--- +@----@-- +@-----@- +-------- +-------- +-------- +# +# l_map= 202020202020202020100E00 +-------- +-------- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +--@----- +---@---- +----@@@- +-------- +-------- +-------- +# +# m_map= 00000000ACD2929292929200 +-------- +-------- +-------- +-------- +-------- +-------- +@-@-@@-- +@@-@--@- +@--@--@- +@--@--@- +@--@--@- +@--@--@- +@--@--@- +-------- +-------- +-------- +# +# n_map= 00000000B8C6828282828200 +-------- +-------- +-------- +-------- +-------- +-------- +@-@@@--- +@@---@@- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +-------- +-------- +-------- +# +# o_map= 0000000038C6828282C63800 +-------- +-------- +-------- +-------- +-------- +-------- +--@@@--- +@@---@@- +@-----@- +@-----@- +@-----@- +@@---@@- +--@@@--- +-------- +-------- +-------- +# +# p_map= 00000000B8C682FC80808000 +-------- +-------- +-------- +-------- +-------- +-------- +@-@@@--- +@@---@@- +@-----@- +@@@@@@-- +@------- +@------- +@------- +-------- +-------- +-------- +# +# q_map= 000000003AC6827E02020200 +-------- +-------- +-------- +-------- +-------- +-------- +--@@@-@- +@@---@@- +@-----@- +-@@@@@@- +------@- +------@- +------@- +-------- +-------- +-------- +# +# r_map= 00000000B8C6808080808000 +-------- +-------- +-------- +-------- +-------- +-------- +@-@@@--- +@@---@@- +@------- +@------- +@------- +@------- +@------- +-------- +-------- +-------- +# +# s_map= 000000007C82807E02827C00 +-------- +-------- +-------- +-------- +-------- +-------- +-@@@@@-- +@-----@- +@------- +-@@@@@@- +------@- +@-----@- +-@@@@@-- +-------- +-------- +-------- +# +# t_map= 80808080F880808080423C00 +-------- +-------- +@------- +@------- +@------- +@------- +@@@@@--- +@------- +@------- +@------- +@------- +-@----@- +--@@@@-- +-------- +-------- +-------- +# +# u_map= 000000008282828282C63A00 +-------- +-------- +-------- +-------- +-------- +-------- +@-----@- +@-----@- +@-----@- +@-----@- +@-----@- +@@---@@- +--@@@-@- +-------- +-------- +-------- +# +# v_map= 000000008282828244281000 +-------- +-------- +-------- +-------- +-------- +-------- +@-----@- +@-----@- +@-----@- +@-----@- +-@---@-- +--@-@--- +---@---- +-------- +-------- +-------- +# +# w_map= 000000008292929292926C00 +-------- +-------- +-------- +-------- +-------- +-------- +@-----@- +@--@--@- +@--@--@- +@--@--@- +@--@--@- +@--@--@- +-@@-@@-- +-------- +-------- +-------- +# +# x_map= 000000000082442838448200 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +@-----@- +-@---@-- +--@-@--- +--@@@--- +-@---@-- +@-----@- +-------- +-------- +-------- +# +# y_map= 000000000082423C08083000 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +@-----@- +-@----@- +--@@@@-- +----@--- +----@--- +--@@---- +-------- +-------- +-------- +# +# z_map= 0000000000FE04083040FE00 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +@@@@@@@- +-----@-- +----@--- +--@@---- +-@------ +@@@@@@@- +-------- +-------- +-------- +# +# {_map= 102020404080404020201000 +-------- +-------- +---@---- +--@----- +--@----- +--@----- +-@------ +@------- +-@------ +--@----- +--@----- +--@----- +---@---- +-------- +-------- +-------- +# +# |_map= 101010101010101010101000 +-------- +-------- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +---@---- +-------- +-------- +-------- +# +# }_map= 100808040402040408081000 +-------- +-------- +---@---- +----@--- +----@--- +----@--- +-----@-- +------@- +-----@-- +----@--- +----@--- +----@--- +---@---- +-------- +-------- +-------- +# +# ~_map= 0000000060920C0000000000 +-------- +-------- +-------- +-------- +-------- +-------- +-@@----- +@--@--@- +----@@-- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +# +# No-Break Space 000000000000000000000000 +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- +-------- Index: tags/yavga-0.8.2/trunk/charmaps/charmaps_ROM.vhd =================================================================== --- tags/yavga-0.8.2/trunk/charmaps/charmaps_ROM.vhd (nonexistent) +++ tags/yavga-0.8.2/trunk/charmaps/charmaps_ROM.vhd (revision 14) @@ -0,0 +1,124 @@ +-------------------------------------------------------------------------------- +---- ---- +---- This file is part of the yaVGA project ---- +---- http://www.opencores.org/?do=project&who=yavga ---- +---- ---- +---- Description ---- +---- Implementation of yaVGA IP core ---- +---- ---- +---- To Do: ---- +---- ---- +---- ---- +---- Author(s): ---- +---- Sandro Amato, sdroamt@netscape.net ---- +---- ---- +-------------------------------------------------------------------------------- +---- ---- +---- Copyright (c) 2009, Sandro Amato ---- +---- All rights reserved. ---- +---- ---- +---- Redistribution and use in source and binary forms, with or without ---- +---- modification, are permitted provided that the following conditions ---- +---- are met: ---- +---- ---- +---- * Redistributions of source code must retain the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer. ---- +---- * Redistributions in binary form must reproduce the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer in the documentation and/or other ---- +---- materials provided with the distribution. ---- +---- * Neither the name of SANDRO AMATO nor the names of its ---- +---- contributors may be used to endorse or promote products ---- +---- derived from this software without specific prior written ---- +---- permission. ---- +---- ---- +---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ---- +---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ---- +---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ---- +---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ---- +---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ---- +---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ---- +---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ---- +---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ---- +---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +-------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +library UNISIM; +use UNISIM.VComponents.all; + +entity charmaps_ROM is + port ( + -- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input + -- i_DIP : in std_logic; -- 1-bit parity Input + -- i_EN : in std_logic; -- RAM Enable Input + -- i_WE : in std_logic; -- Write Enable Input + -- i_SSR : in std_logic; -- Synchronous Set/Reset Input + i_clock : in std_logic; -- Clock + i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input + o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output + -- o_DOP : out std_logic -- 1-bit parity Output + ); +end charmaps_ROM; + +architecture rtl of charmaps_ROM is + +begin + -- charmaps + -- |------| |-----------------| + -- | P | | D D D D D D D D | + -- |======| |=================| + -- | 8 | | 7 6 5 4 3 2 1 0 | + -- |======| |=================| + -- | Free | | Row char pixels | + -- |------| |-----------------| + + Inst_charmaps_rom : RAMB16_S9 + generic map ( + write_mode => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT => B"000000000", -- Value of output RAM registers at startup + SRVAL => B"000000000", -- Ouput value upon SSR assertion + -- + -- START REPLACE HERE THE OUTPUT FROM convert.sh + -- INIT_00 => ... + -- ... + -- ... + -- ... + -- INIT_3F => ... + -- STOP REPLACE + -- + -- + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + DI => (others => '1'), -- 8-bit Data Input + DIP => (others => '1'), -- 1-bit parity Input + EN => '1', -- RAM Enable Input + WE => '0', -- Write Enable Input + SSR => '0', -- Synchronous Set/Reset Input + CLK => i_clock, -- Clock + ADDR => i_ADDR, -- 11-bit Address Input + DO => o_DO, -- 8-bit Data Output + DOP => open -- 1-bit parity Output + ); + + +end rtl; Index: tags/yavga-0.8.2/trunk/LICENSE.txt =================================================================== --- tags/yavga-0.8.2/trunk/LICENSE.txt (nonexistent) +++ tags/yavga-0.8.2/trunk/LICENSE.txt (revision 14) @@ -0,0 +1,31 @@ +Copyright (c) 2009, Sandro Amato +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + + * Redistributions of source code must retain the above + copyright notice, this list of conditions and the + following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the + following disclaimer in the documentation and/or other + materials provided with the distribution. + * Neither the name of SANDRO AMATO nor the names of its + contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. Index: tags/yavga-0.8.2/trunk/README.txt =================================================================== --- tags/yavga-0.8.2/trunk/README.txt (nonexistent) +++ tags/yavga-0.8.2/trunk/README.txt (revision 14) @@ -0,0 +1,30 @@ +######################################################## +#### This file is part of the yaVGA project #### +#### http://www.opencores.org/?do=project&who=yavga #### +######################################################## + +This core is a semi semigraphic vga controller. + +It generate the signal to drive a vga monitor with an 800x600 resolution +and 72Hz vertical refresh rate + +It display monochromatic chars on the screen from a ram memory + +It can display a color "waveform" (a sort of function) from another ram memory + +It can display a color grid and "cross cursor" + +vhdl + this directory contains the hdl and constraint files + +charmaps + this directory contains some scripts useful to change the char maps + +LICENSE.txt + the license + +README.txt + this file + +xilinx + this directory contain xilinx ISE generated files Index: tags/yavga-0.8.2/trunk/vhdl/chars_RAM.vhd =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/chars_RAM.vhd (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/chars_RAM.vhd (revision 14) @@ -0,0 +1,484 @@ +-------------------------------------------------------------------------------- +---- ---- +---- This file is part of the yaVGA project ---- +---- http://www.opencores.org/?do=project&who=yavga ---- +---- ---- +---- Description ---- +---- Implementation of yaVGA IP core ---- +---- ---- +---- To Do: ---- +---- ---- +---- ---- +---- Author(s): ---- +---- Sandro Amato, sdroamt@netscape.net ---- +---- ---- +-------------------------------------------------------------------------------- +---- ---- +---- Copyright (c) 2009, Sandro Amato ---- +---- All rights reserved. ---- +---- ---- +---- Redistribution and use in source and binary forms, with or without ---- +---- modification, are permitted provided that the following conditions ---- +---- are met: ---- +---- ---- +---- * Redistributions of source code must retain the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer. ---- +---- * Redistributions in binary form must reproduce the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer in the documentation and/or other ---- +---- materials provided with the distribution. ---- +---- * Neither the name of SANDRO AMATO nor the names of its ---- +---- contributors may be used to endorse or promote products ---- +---- derived from this software without specific prior written ---- +---- permission. ---- +---- ---- +---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ---- +---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ---- +---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ---- +---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ---- +---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ---- +---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ---- +---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ---- +---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ---- +---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +-------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +library UNISIM; +use UNISIM.VComponents.all; + +entity chars_RAM is + port ( + i_clock_rw : in std_logic; -- Write Clock + i_EN_rw : in std_logic; -- Write RAM Enable Input + i_WE_rw : in std_logic_vector(3 downto 0); -- Write Enable Input + i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input + i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input + o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input + + i_SSR : in std_logic; -- Synchronous Set/Reset Input + + i_clock_r : in std_logic; -- Read Clock + i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input + o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output + ); +end chars_RAM; + +architecture rtl of chars_RAM is + signal s0_DO_r : std_logic_vector(7 downto 0); + signal s1_DO_r : std_logic_vector(7 downto 0); + signal s2_DO_r : std_logic_vector(7 downto 0); + signal s3_DO_r : std_logic_vector(7 downto 0); + +begin + + u0_chars_ram : RAMB16_S9_S9 + generic map ( + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_A => B"000000000", -- Value of output RAM registers at startup + SRVAL_A => B"000000000", -- Ouput value upon SSR assertion + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_B => B"000000000", -- Value of output RAM registers at startup + SRVAL_B => B"000000000", -- Ouput value upon SSR assertion + -- + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + -- read + DIA => (others => '0'), -- 2-bit Data Input + DIPA => (others => '0'), + ENA => '1', -- RAM Enable Input + WEA => '0', -- Write Enable Input + SSRA => i_SSR, -- Synchronous Set/Reset Input + CLKA => i_clock_r, -- Clock + ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input + DOA => s0_DO_r, -- 8-bit Data Output + DOPA => open, + + -- read/write + DIB => i_DI_rw(7 downto 0), -- 8-bit Data Input + DIPB => (others => '0'), + ENB => i_EN_rw, -- RAM Enable Input + WEB => i_WE_rw(0), -- Write Enable Input + SSRB => i_SSR, -- Synchronous Set/Reset Input + CLKB => i_clock_rw, -- Clock + ADDRB => i_ADDR_rw, -- 11-bit Address Input + DOB => o_DI_rw(7 downto 0), -- 8-bit Data Input + DOPB => open + ); + + u1_chars_ram : RAMB16_S9_S9 + generic map ( + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_A => B"000000000", -- Value of output RAM registers at startup + SRVAL_A => B"000000000", -- Ouput value upon SSR assertion + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_B => B"000000000", -- Value of output RAM registers at startup + SRVAL_B => B"000000000", -- Ouput value upon SSR assertion + -- + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + -- read + DIA => (others => '0'), -- 2-bit Data Input + DIPA => (others => '0'), + ENA => '1', -- RAM Enable Input + WEA => '0', -- Write Enable Input + SSRA => i_SSR, -- Synchronous Set/Reset Input + CLKA => i_clock_r, -- Clock + ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input + DOA => s1_DO_r, -- 8-bit Data Output + DOPA => open, + + -- read/write + DIB => i_DI_rw(15 downto 8), -- 8-bit Data Input + DIPB => (others => '0'), + ENB => i_EN_rw, -- RAM Enable Input + WEB => i_WE_rw(1), -- Write Enable Input + SSRB => i_SSR, -- Synchronous Set/Reset Input + CLKB => i_clock_rw, -- Clock + ADDRB => i_ADDR_rw, -- 11-bit Address Input + DOB => o_DI_rw(15 downto 8), -- 8-bit Data Input + DOPB => open + ); + + u2_chars_ram : RAMB16_S9_S9 + generic map ( + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_A => B"000000000", -- Value of output RAM registers at startup + SRVAL_A => B"000000000", -- Ouput value upon SSR assertion + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_B => B"000000000", -- Value of output RAM registers at startup + SRVAL_B => B"000000000", -- Ouput value upon SSR assertion + -- + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + -- read + DIA => (others => '0'), -- 2-bit Data Input + DIPA => (others => '0'), + ENA => '1', -- RAM Enable Input + WEA => '0', -- Write Enable Input + SSRA => i_SSR, -- Synchronous Set/Reset Input + CLKA => i_clock_r, -- Clock + ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input + DOA => s2_DO_r, -- 8-bit Data Output + DOPA => open, + + -- read/write + DIB => i_DI_rw(23 downto 16), -- 8-bit Data Input + DIPB => (others => '0'), + ENB => i_EN_rw, -- RAM Enable Input + WEB => i_WE_rw(2), -- Write Enable Input + SSRB => i_SSR, -- Synchronous Set/Reset Input + CLKB => i_clock_rw, -- Clock + ADDRB => i_ADDR_rw, -- 11-bit Address Input + DOB => o_DI_rw(23 downto 16), -- 8-bit Data Input + DOPB => open + ); + + u3_chars_ram : RAMB16_S9_S9 + generic map ( + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_A => B"000000000", -- Value of output RAM registers at startup + SRVAL_A => B"000000000", -- Ouput value upon SSR assertion + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT_B => B"000000000", -- Value of output RAM registers at startup + SRVAL_B => B"000000000", -- Ouput value upon SSR assertion + -- + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + -- read + DIA => (others => '0'), -- 2-bit Data Input + DIPA => (others => '0'), + ENA => '1', -- RAM Enable Input + WEA => '0', -- Write Enable Input + SSRA => i_SSR, -- Synchronous Set/Reset Input + CLKA => i_clock_r, -- Clock + ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input + DOA => s3_DO_r, -- 8-bit Data Output + DOPA => open, + + -- read/write + DIB => i_DI_rw(31 downto 24), -- 8-bit Data Input + DIPB => (others => '0'), + ENB => i_EN_rw, -- RAM Enable Input + WEB => i_WE_rw(3), -- Write Enable Input + SSRB => i_SSR, -- Synchronous Set/Reset Input + CLKB => i_clock_rw, -- Clock + ADDRB => i_ADDR_rw, -- 11-bit Address Input + DOB => o_DI_rw(31 downto 24), -- 8-bit Data Input + DOPB => open + ); + + o_DO_r <= s0_DO_r when i_ADDR_r(1 downto 0) = "11" else + s1_DO_r when i_ADDR_r(1 downto 0) = "10" else + s2_DO_r when i_ADDR_r(1 downto 0) = "01" else + s3_DO_r when i_ADDR_r(1 downto 0) = "00" else + (others => 'X'); + +end rtl; Index: tags/yavga-0.8.2/trunk/vhdl/s3e_starter_1600k.vhd =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/s3e_starter_1600k.vhd (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/s3e_starter_1600k.vhd (revision 14) @@ -0,0 +1,192 @@ +-------------------------------------------------------------------------------- +---- ---- +---- This file is part of the yaVGA project ---- +---- http://www.opencores.org/?do=project&who=yavga ---- +---- ---- +---- Description ---- +---- Implementation of yaVGA IP core ---- +---- ---- +---- To Do: ---- +---- ---- +---- ---- +---- Author(s): ---- +---- Sandro Amato, sdroamt@netscape.net ---- +---- ---- +-------------------------------------------------------------------------------- +---- ---- +---- Copyright (c) 2009, Sandro Amato ---- +---- All rights reserved. ---- +---- ---- +---- Redistribution and use in source and binary forms, with or without ---- +---- modification, are permitted provided that the following conditions ---- +---- are met: ---- +---- ---- +---- * Redistributions of source code must retain the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer. ---- +---- * Redistributions in binary form must reproduce the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer in the documentation and/or other ---- +---- materials provided with the distribution. ---- +---- * Neither the name of SANDRO AMATO nor the names of its ---- +---- contributors may be used to endorse or promote products ---- +---- derived from this software without specific prior written ---- +---- permission. ---- +---- ---- +---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ---- +---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ---- +---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ---- +---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ---- +---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ---- +---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ---- +---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ---- +---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ---- +---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity s3e_starter_1600k is + port (i_clk : in std_logic; + o_hsync : out std_logic; + o_vsync : out std_logic; + o_r : out std_logic; + o_g : out std_logic; + o_b : out std_logic); +end s3e_starter_1600k; + +architecture Behavioral of s3e_starter_1600k is + + component vga_ctrl + port( + i_clk : in std_logic; + i_reset : in std_logic; + i_background : in std_logic; + i_cursor_color : in std_logic_vector(2 downto 0); + i_cursor_x : in std_logic_vector(10 downto 0); + i_cursor_y : in std_logic_vector(9 downto 0); + i_h_sync_en : in std_logic; + i_v_sync_en : in std_logic; + i_chr_addr : in std_logic_vector(10 downto 0); + i_chr_data : in std_logic_vector(31 downto 0); + i_chr_clk : in std_logic; + i_chr_en : in std_logic; + i_chr_we : in std_logic_vector(3 downto 0); + i_chr_rst : in std_logic; + i_wav_d : in std_logic_vector(15 downto 0); + i_wav_we : in std_logic; + i_wav_addr : in std_logic_vector(9 downto 0); + o_h_sync : out std_logic; + o_v_sync : out std_logic; + o_r : out std_logic; + o_g : out std_logic; + o_b : out std_logic; + o_chr_data : out std_logic_vector(31 downto 0) + ); + end component; + + signal s_hsync : std_logic; + signal s_vsync : std_logic; + signal s_r : std_logic; + signal s_g : std_logic; + signal s_b : std_logic; + + signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0'); + signal s_vsync1 : std_logic; + + signal s_chr_addr : std_logic_vector(10 downto 0) := (others => '0'); + signal s_rnd : std_logic_vector(31 downto 0) := (others => '0'); + signal s_chr_we : std_logic_vector(3 downto 0); + + attribute U_SET : string; + attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset"; + +begin + o_hsync <= s_hsync; + o_vsync <= s_vsync; + o_r <= s_r; + o_g <= s_g; + o_b <= s_b; + + u1_vga_ctrl : vga_ctrl port map( + i_clk => i_clk, + i_reset => '0', + i_background => '0', + i_cursor_color => "001", + i_cursor_x => "00101000000", + i_cursor_y => "0011000000", + o_h_sync => s_hsync, + o_v_sync => s_vsync, + i_h_sync_en => '1', + i_v_sync_en => '1', + o_r => s_r, + o_g => s_g, + o_b => s_b, + i_chr_addr => s_chr_addr, --B"000_0000_0000", + i_chr_data => s_rnd, --X"00000000", + o_chr_data => open, + i_chr_clk => i_clk, + i_chr_en => '1', + i_chr_we => s_chr_we, + i_chr_rst => '0', + i_wav_d => X"0000", --s_rnd(15 downto 0), -- + i_wav_we => '0', --s_chr_we(0), -- + i_wav_addr => B"00_0000_0000" --s_chr_addr(9 downto 0) -- + ); + + p_write_chars : process(i_clk) + begin + if rising_edge(i_clk) then + -- during the sync time in order to avoid flickering + -- and each 128 vsync in order to stop for a while + -- will write random chars... + if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then + -- generate a pseudo random 32 bit number + s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0)); + -- increment the address and write enable... + s_chr_addr <= s_chr_addr + 1; + s_chr_we <= "1111"; + else + s_chr_addr <= s_chr_addr; + s_chr_we <= "0000"; + s_rnd <= s_rnd; + end if; + end if; + end process; + +-- p_rnd_bit : process(i_clk) +-- variable v_rnd_fb : std_logic; +-- variable v_rnd : std_logic_vector(31 downto 0); +-- begin +-- if rising_edge(i_clk) then +-- s_rnd_bit <= v_rnd_fb; +-- v_rnd_fb := v_rnd(31) xnor v_rnd(21) xnor v_rnd(1) xnor v_rnd(0); +-- v_rnd := v_rnd(30 downto 0) & v_rnd_fb; +-- end if; +-- end process; + + p_vsync_count : process(i_clk) + begin + if rising_edge(i_clk) then + s_vsync1 <= s_vsync; + if (not s_vsync and s_vsync1) = '1' then -- pulse on vsync falling + s_vsync_count <= s_vsync_count + 1; + end if; + end if; + end process; + + + +end Behavioral; + Index: tags/yavga-0.8.2/trunk/vhdl/vga_ctrl.vhd =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/vga_ctrl.vhd (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/vga_ctrl.vhd (revision 14) @@ -0,0 +1,483 @@ +-------------------------------------------------------------------------------- +---- ---- +---- This file is part of the yaVGA project ---- +---- http://www.opencores.org/?do=project&who=yavga ---- +---- ---- +---- Description ---- +---- Implementation of yaVGA IP core ---- +---- ---- +---- To Do: ---- +---- ---- +---- ---- +---- Author(s): ---- +---- Sandro Amato, sdroamt@netscape.net ---- +---- ---- +-------------------------------------------------------------------------------- +---- ---- +---- Copyright (c) 2009, Sandro Amato ---- +---- All rights reserved. ---- +---- ---- +---- Redistribution and use in source and binary forms, with or without ---- +---- modification, are permitted provided that the following conditions ---- +---- are met: ---- +---- ---- +---- * Redistributions of source code must retain the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer. ---- +---- * Redistributions in binary form must reproduce the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer in the documentation and/or other ---- +---- materials provided with the distribution. ---- +---- * Neither the name of SANDRO AMATO nor the names of its ---- +---- contributors may be used to endorse or promote products ---- +---- derived from this software without specific prior written ---- +---- permission. ---- +---- ---- +---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ---- +---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ---- +---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ---- +---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ---- +---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ---- +---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ---- +---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ---- +---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ---- +---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity vga_ctrl is +-- generic ( +-- g_H_SIZE : integer := 800; -- horizontal size of input image, MAX 800 +-- g_V_SIZE : integer := 600 -- vertical size of input image, MAX 600 +-- ); + + port ( + i_clk : in std_logic; -- must be 50MHz + i_reset : in std_logic; + + -- background color (b/w) + i_background : in std_logic; + + -- cross cursor + i_cursor_color : in std_logic_vector(2 downto 0); + i_cursor_x : in std_logic_vector(10 downto 0); + i_cursor_y : in std_logic_vector(9 downto 0); + + -- vga horizontal and vertical sync + o_h_sync : out std_logic; + o_v_sync : out std_logic; + + -- horizontal and vertical sync enable (allow power saving on ?VESA? Monitors) + i_h_sync_en : in std_logic; + i_v_sync_en : in std_logic; + + -- vga R G B signals (1 bit for each component (8 colors)) + o_r : out std_logic; + o_g : out std_logic; + o_b : out std_logic; + + -- chars RAM memory + i_chr_addr : in std_logic_vector(10 downto 0); + i_chr_data : in std_logic_vector(31 downto 0); + o_chr_data : out std_logic_vector(31 downto 0); + i_chr_clk : in std_logic; + i_chr_en : in std_logic; + i_chr_we : in std_logic_vector(3 downto 0); + i_chr_rst : in std_logic; + + -- waveform RAM memory + i_wav_d : in std_logic_vector(15 downto 0); + i_wav_we : in std_logic; + --i_clockA : IN std_logic; + i_wav_addr : in std_logic_vector(9 downto 0) --; + --o_DOA : OUT std_logic_vector(15 downto 0) + ); +end vga_ctrl; + +-- vga timings used +-- 0 TOT +-- ...-----------------|=============== PERIOD ==============|--... +-- | | +-- ...__ ___________________________ _______... +-- \_________/ \_________/ +-- +-- | | | | | | | +-- | | | | | | | +-- ...--|----S----|-F--|=======D=======|==B===|====S====|=F==|--... +-- Y R I A Y R +-- N O S C N O +-- C N P K C N +-- T T L P T T +-- I P T O I P +-- M O I R M O +-- E R M C E R +-- C E H C +-- H H +-- | | | | | | | +-- ...|---------|----|===============|======|=========|====|--... +-- HPx: 120 56 800 63 120 56 px (h PERIOD = 1039 px) +-- VLn: 6 37 600 23 6 37 ln (v PERIOD = 666 ln) +-- +-- and with 50Mhz dot clock (20ns dot time): +-- | | | | | | | +-- ...|---------|----|===============|======|=========|====|--... +--Htime: 2.4 1.12 16 1.26 2.4 1.12 usec (h PERIOD = 20.78 usec) Hfreq 48123.195 Hz +--Vtime: 124.68 768.86 12468 477.94 124.68 768.68 usec (v PERIOD = 13839.48 usec) Vfreq 72.257 Hz + +architecture rtl of vga_ctrl is + + constant c_GRID_SIZE : std_logic_vector(6 downto 0) := "1111111"; + constant c_GRID_BIT : integer := 6; + + -- + -- horizontal timing signals (in pixels count ) + constant c_H_DISPLAYpx : integer := 800; + constant c_H_BACKPORCHpx : integer := 63; -- also 60; + constant c_H_SYNCTIMEpx : integer := 120; + constant c_H_FRONTPORCHpx : integer := 56; --also 60; + constant c_H_PERIODpx : integer := c_H_DISPLAYpx + + c_H_BACKPORCHpx + + c_H_SYNCTIMEpx + + c_H_FRONTPORCHpx; + + -- + -- vertical timing signals (in lines count) + constant c_V_DISPLAYln : integer := 600; + constant c_V_BACKPORCHln : integer := 23; + constant c_V_SYNCTIMEln : integer := 6; + constant c_V_FRONTPORCHln : integer := 37; + constant c_V_PERIODln : integer := c_V_DISPLAYln + + c_V_BACKPORCHln + + c_V_SYNCTIMEln + + c_V_FRONTPORCHln; + + +-- constant c_CHARS_WIDTH: std_logic_vector(2 downto 0) := "111"; +-- constant c_CHARS_HEIGHT: std_logic_vector(3 downto 0) := "1111"; +-- constant c_CHARS_COLS: std_logic_vector(6 downto 0) := "1100011"; +-- constant c_CHARS_ROWS: std_logic_vector(5 downto 0) := "100100"; + + -- + signal s_h_count : std_logic_vector(10 downto 0); -- horizontal pixel counter + signal s_v_count : std_logic_vector(9 downto 0); -- verticalal line counter + signal s_h_sync : std_logic; -- horizontal sync trigger + signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger + + -- + -- signals for the charmaps Block RAM component... + signal s_charmaps_ADDR : std_logic_vector (10 downto 0); + signal s_charmaps_DO : std_logic_vector (7 downto 0); + signal s_charmaps_DO_l : std_logic_vector (7 downto 0); + + -- + -- to manage the outside display region's blanking + signal s_display : std_logic; + -- + + -- + -- to manage the cursor position + signal s_cursor_x : std_logic_vector(10 downto 0); + signal s_cursor_y : std_logic_vector(9 downto 0); + + -- + -- to manage the chars ram address and th ram ascii + signal s_chars_ram_addr : std_logic_vector(12 downto 0); + signal s_chars_ascii : std_logic_vector(7 downto 0); + + -- + signal s_waveform_ADDRB : std_logic_vector (9 downto 0); + signal s_waveform_DOB : std_logic_vector (15 downto 0); + + + -- charmaps + -- |------| |-----------------| + -- | P | | D D D D D D D D | + -- |======| |=================| + -- | 8 | | 7 6 5 4 3 2 1 0 | + -- |======| |=================| + -- | Free | | Row char pixels | + -- |------| |-----------------| + -- + component charmaps_rom + port( + i_clock : in std_logic; + i_ADDR : in std_logic_vector(10 downto 0); -- 16 x ascii code (W=8 x H=16 pixel) + o_DO : out std_logic_vector(7 downto 0) -- 8 bit char pixel + ); + end component; + + + + -- wave form or video-line memory + -- |------| |-------------------------------------------| + -- | P P | | D D D | D D D | D D D D D D D D D D | + -- |======| |===========================================| + -- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 | + -- |======| |===========================================| + -- | Free | | Reserv. | R G B | vert. pos. | + -- |------| |-------------------------------------------| + -- + component waveform_ram + port( + i_DIA : in std_logic_vector(15 downto 0); + i_WEA : in std_logic; + i_clockA : in std_logic; + i_ADDRA : in std_logic_vector(9 downto 0); + --o_DOA : OUT std_logic_vector(15 downto 0); + -- + i_DIB : in std_logic_vector(15 downto 0); + i_WEB : in std_logic; + i_clockB : in std_logic; + i_ADDRB : in std_logic_vector(9 downto 0); + o_DOB : out std_logic_vector(15 downto 0) + ); + end component; + + component chars_RAM + port( + i_clock_rw : in std_logic; + i_EN_rw : in std_logic; + i_WE_rw : in std_logic_vector(3 downto 0); + i_ADDR_rw : in std_logic_vector(10 downto 0); + i_DI_rw : in std_logic_vector(31 downto 0); + o_DI_rw : out std_logic_vector(31 downto 0); + i_SSR : in std_logic; + i_clock_r : in std_logic; + i_ADDR_r : in std_logic_vector(12 downto 0); + o_DO_r : out std_logic_vector(7 downto 0) + ); + end component; + + + attribute U_SET : string; + attribute U_SET of "u0_chars_RAM" : label is "u0_chars_RAM_uset"; + attribute U_SET of "u1_charmaps_rom" : label is "u1_charmaps_rom_uset"; + attribute U_SET of "u2_waveform_ram" : label is "u2_waveform_ram_uset"; + +begin + + s_chars_ram_addr <= s_v_count(9 downto 4) & s_h_count(9 downto 3); + + u0_chars_RAM : chars_RAM port map( + i_clock_rw => i_chr_clk, + i_EN_rw => i_chr_en, + i_WE_rw => i_chr_we, + i_ADDR_rw => i_chr_addr, + i_DI_rw => i_chr_data, + o_DI_rw => o_chr_data, + i_SSR => i_chr_rst, + i_clock_r => i_clk, + i_ADDR_r => s_chars_ram_addr, + o_DO_r => s_chars_ascii + ); + + + + u1_charmaps_rom : charmaps_rom port map( + i_clock => i_clk, + i_ADDR => s_charmaps_ADDR, + o_DO => s_charmaps_DO + ); + + -- modify the charmaps address + p_MGM_CHARMAPS_ADDR : process(i_clk) --, i_reset) --, s_v_count, i_cursor_color) + begin + if rising_edge(i_clk) then + if i_reset = '1' then -- sync reset + s_charmaps_ADDR <= "01000000000"; -- (others => '0'); + else + if (s_h_count(2 downto 0) = "110") then -- each 8 h_count + s_charmaps_DO_l <= s_charmaps_DO; + end if; + -- here start char 'a' ---v v----- ascii code ------v v-- vert char row --v + --s_charmaps_ADDR <= "01000000000" + ( s_h_count(9 downto 3) & s_v_count(3 downto 0) ); + s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0)); + -- here start char 'a' ---^ ^----- ascii code ------^ ^-- vert char row --^ + end if; + end if; + end process; + + + + u2_waveform_ram : waveform_ram port map( + i_DIA => i_wav_d, + i_WEA => i_wav_we, + --i_clockA => i_clockA, + i_clockA => i_clk, + i_ADDRA => i_wav_addr, + --o_DOA => o_DOA, + -- + i_DIB => "1111111111111111", + i_WEB => '0', + i_clockB => i_clk, + -- i_ADDRB => s_waveform_ADDRB, + i_ADDRB => s_waveform_ADDRB, --s_h_count(9 downto 0), + o_DOB => s_waveform_DOB + ); + + p_WaveFormAddr : process (i_clk) + begin + if rising_edge(i_clk) then + s_waveform_ADDRB <= s_h_count(9 downto 0); + end if; + end process; + + p_pulse_on_hsync_falling : process(i_clk) + variable v_h_sync1 : std_logic; + begin + if rising_edge(i_clk) then + s_h_sync_pulse <= not s_h_sync and v_h_sync1; + v_h_sync1 := s_h_sync; + end if; + end process; + + + -- set the cursor position + s_cursor_x <= i_cursor_x; -- 400 + s_cursor_y <= i_cursor_y; -- 300 + + -- control the reset, increment and overflow of the horizontal pixel count + p_H_PX_COUNT : process(i_clk) --, i_reset) + begin + if rising_edge(i_clk) then + if i_reset = '1' or s_h_count = c_H_PERIODpx then -- sync reset + s_h_count <= (others => '0'); + else + s_h_count <= s_h_count + 1; + end if; + end if; + end process; + + + + p_V_LN_COUNT : process(i_clk) + begin + if rising_edge(i_clk) then + if i_reset = '1' or s_v_count = c_V_PERIODln then -- sync reset + s_v_count <= (others => '0'); + elsif s_h_sync_pulse = '1' then + s_v_count <= s_v_count + 1; + end if; + end if; + end process; + + -- set the horizontal sync high time and low time according to the constants + p_MGM_H_SYNC : process(i_clk) --, i_reset) + begin + if rising_edge(i_clk) then + if (s_h_count = c_H_DISPLAYpx + c_H_BACKPORCHpx) then + s_h_sync <= '0'; + elsif (s_h_count = c_H_PERIODpx - c_H_FRONTPORCHpx) then + s_h_sync <= '1'; + end if; + end if; + end process; + o_h_sync <= s_h_sync and i_h_sync_en; + + + p_MGM_V_SYNC : process(i_clk) --, i_reset) + begin + --if falling_edge(i_clk) then + if rising_edge(i_clk) then + if i_v_sync_en = '0' or + (s_v_count = (c_V_DISPLAYln + c_V_BACKPORCHln)) then + o_v_sync <= '0'; + elsif (s_v_count = (c_V_PERIODln - c_V_FRONTPORCHln)) then --and (s_h_sync_pulse = '1') then + o_v_sync <= '1'; + end if; + end if; + end process; + + -- asserts the blaking signal (active low) + p_MGM_BLANK : process (i_clk) --, i_reset) + begin + if rising_edge(i_clk) then + -- if we are outside the visible range on the screen then tell the RAMDAC to blank + -- in this section by putting s_display low + if not (s_h_count < c_H_DISPLAYpx and s_v_count < c_V_DISPLAYln) then + s_display <= '0'; + else + s_display <= '1'; + end if; + end if; + end process; + + + -- generates the r g b signals and show the green cursor + p_MGM_RGB : process (i_clk) --, i_reset) --, i_cursor_color, s_display) + variable v_previous_pixel : std_logic_vector(9 downto 0) := "0100101100"; + begin + if rising_edge(i_clk) then -- not async reset + if i_reset = '1' then -- sync reset + o_r <= '0'; + o_g <= '0'; + o_b <= '0'; + else + if s_display = '1' then -- display zone + if ( + (s_h_count = s_cursor_x) or (s_v_count = s_cursor_y) or + (s_h_count(c_GRID_BIT downto 0) = c_GRID_SIZE(c_GRID_BIT downto 0)) or + (s_v_count(c_GRID_BIT downto 0) = c_GRID_SIZE(c_GRID_BIT downto 0)) + ) + and (s_v_count(9) = '0') -- < 512 + then -- draw the cursor and/or WaveForm Grid references + o_r <= i_cursor_color(2); + o_g <= i_cursor_color(1); + o_b <= i_cursor_color(0); + elsif + ((s_v_count(9 downto 0) >= s_waveform_DOB(9 downto 0)) and + (s_v_count(9 downto 0) <= v_previous_pixel) + ) or + ((s_v_count(9 downto 0) <= s_waveform_DOB(9 downto 0)) and + (s_v_count(9 downto 0) >= v_previous_pixel) + ) + then -- draw the waveform pixel... + o_r <= s_waveform_DOB(12) or s_waveform_DOB(15); -- the "or" is only + o_g <= s_waveform_DOB(11) or s_waveform_DOB(14); -- to not warning + o_b <= s_waveform_DOB(10) or s_waveform_DOB(13); -- unused signals + else -- draw the background and charmaps + --if s_v_count > 512 then + --FULL_SCREEN if (s_v_count(9) = '1') then -- >= 512 + case (s_h_count(2 downto 0)) is + when "000" => o_g <= s_charmaps_DO_l(7) xor i_background; + when "001" => o_g <= s_charmaps_DO_l(6) xor i_background; + when "010" => o_g <= s_charmaps_DO_l(5) xor i_background; + when "011" => o_g <= s_charmaps_DO_l(4) xor i_background; + when "100" => o_g <= s_charmaps_DO_l(3) xor i_background; + when "101" => o_g <= s_charmaps_DO_l(2) xor i_background; + when "110" => o_g <= s_charmaps_DO_l(1) xor i_background; + when "111" => o_g <= s_charmaps_DO_l(0) xor i_background; + when others => o_g <= 'X'; + --when others => o_g <= i_background; + end case; + --FULL_SCREEN else + --FULL_SCREEN o_g <= i_background; + --FULL_SCREEN end if; + o_r <= i_background; + --o_g <= i_background; + o_b <= i_background; + end if; + else -- blank zone + -- the blanking zone + o_r <= '0'; + o_g <= '0'; + o_b <= '0'; + end if; -- if s_display + v_previous_pixel := s_waveform_DOB(9 downto 0); + end if; -- if i_reset + end if; + end process; + +end rtl; Index: tags/yavga-0.8.2/trunk/vhdl/waveform_RAM.vhd =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/waveform_RAM.vhd (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/waveform_RAM.vhd (revision 14) @@ -0,0 +1,212 @@ +-------------------------------------------------------------------------------- +---- ---- +---- This file is part of the yaVGA project ---- +---- http://www.opencores.org/?do=project&who=yavga ---- +---- ---- +---- Description ---- +---- Implementation of yaVGA IP core ---- +---- ---- +---- To Do: ---- +---- ---- +---- ---- +---- Author(s): ---- +---- Sandro Amato, sdroamt@netscape.net ---- +---- ---- +-------------------------------------------------------------------------------- +---- ---- +---- Copyright (c) 2009, Sandro Amato ---- +---- All rights reserved. ---- +---- ---- +---- Redistribution and use in source and binary forms, with or without ---- +---- modification, are permitted provided that the following conditions ---- +---- are met: ---- +---- ---- +---- * Redistributions of source code must retain the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer. ---- +---- * Redistributions in binary form must reproduce the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer in the documentation and/or other ---- +---- materials provided with the distribution. ---- +---- * Neither the name of SANDRO AMATO nor the names of its ---- +---- contributors may be used to endorse or promote products ---- +---- derived from this software without specific prior written ---- +---- permission. ---- +---- ---- +---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ---- +---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ---- +---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ---- +---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ---- +---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ---- +---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ---- +---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ---- +---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ---- +---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +library UNISIM; +use UNISIM.VComponents.all; + +entity waveform_RAM is + port ( + i_DIA : in std_logic_vector(15 downto 0); -- 16-bit Data Input + -- i_DIPA : in std_logic; -- 2-bit parity Input + -- i_ENA : in std_logic; -- RAM Enable Input + i_WEA : in std_logic; -- Write Enable Input + -- i_SSRA : in std_logic; -- Synchronous Set/Reset Input + i_clockA : in std_logic; -- Clock + i_ADDRA : in std_logic_vector(9 downto 0); -- 10-bit Address Input + --o_DOA : out std_logic_vector(15 downto 0); -- 16-bit Data Output + -- o_DOPA : out std_logic -- 2-bit parity Output + -- + i_DIB : in std_logic_vector(15 downto 0); -- 16-bit Data Input + -- i_DIPB : in std_logic; -- 2-bit parity Input + -- i_ENB : in std_logic; -- RAM Enable Input + i_WEB : in std_logic; -- Write Enable Input + -- i_SSRB : in std_logic; -- Synchronous Set/Reset Input + i_clockB : in std_logic; -- Clock + i_ADDRB : in std_logic_vector(9 downto 0); -- 10-bit Address Input + o_DOB : out std_logic_vector(15 downto 0) -- 16-bit Data Output + -- o_DOPB : out std_logic -- 2-bit parity Output + ); +end waveform_RAM; + +architecture rtl of waveform_RAM is + +begin + -- wave form or video-line memory + -- |------| |-------------------------------------------| + -- | P P | | D D D | D D D | D D D D D D D D D D | + -- |======| |===========================================| + -- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 | + -- |======| |===========================================| + -- | Free | | Reserv. | R G B | vert. pos. | + -- |------| |-------------------------------------------| + -- + + Inst_waveform_RAM : RAMB16_S18_S18 + generic map ( + WRITE_MODE_A => "READ_FIRST", -- "WRITE_FIRST"; + INIT_A => B"000000000000000000", + SRVAL_A => B"000000000000000000", + -- + WRITE_MODE_B => "READ_FIRST", -- "WRITE_FIRST"; + INIT_B => B"000000000000000000", + SRVAL_B => B"000000000000000000", + -- + --INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + INIT_01 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_02 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_03 => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F", + INIT_04 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_05 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_06 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + INIT_07 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B", + + --INIT_08 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A", + INIT_08 => X"112A114011C211F4117C10FA110E112A112A112A112A112A112A112A112A192A", + + --INIT_09 => X"1129112911291129112911291129112911291129112911291129112911291129", + INIT_09 => X"1129112911291129112911291129112911291129112911291129112911291529", + + INIT_0A => X"1128112811281128112811281128112811281128112811281128112811281128", + INIT_0B => X"1127112711271127112711271127112711271127112711271127112711271127", + INIT_0C => X"1126112611261126112611261126112611261126112611261126112611261126", + INIT_0D => X"1125112511251125112511251125112511251125112511251125112511251125", + INIT_0E => X"1124112411241124112411241124112411241124112411241124112411241124", + INIT_0F => X"1123112311231123112311231123112311231123112311231123112311231123", + -- + INIT_10 => X"1123112311231123112311231123112311231123112311231123112311231123", + INIT_11 => X"1124112411241124112411241124112411241124112411241124112411241124", + INIT_12 => X"1125112511251125112511251125112511251125112511251125112511251125", + INIT_13 => X"1126112611261126112611261126112611261126112611261126112611261126", + INIT_14 => X"1127112711271127112711271127112711271127112711271127112711271127", + INIT_15 => X"1128112811281128112811281128112811281128112811281128112811281128", + INIT_16 => X"1129112911291129112911291129112911291129112911291129112911291129", + INIT_17 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A", + INIT_18 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B", + INIT_19 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + INIT_1A => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_1B => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_1C => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F", + INIT_1D => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_1E => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_1F => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + -- + INIT_20 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + INIT_21 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_22 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_23 => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F", + INIT_24 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_25 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_26 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + INIT_27 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B", + INIT_28 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A", + INIT_29 => X"1129112911291129112911291129112911291129112911291129112911291129", + INIT_2A => X"1128112811281128112811281128112811281128112811281128112811281128", + INIT_2B => X"1127112711271127112711271127112711271127112711271127112711271127", + INIT_2C => X"1126112611261126112611261126112611261126112611261126112611261126", + INIT_2D => X"1125112511251125112511251125112511251125112511251125112511251125", + INIT_2E => X"1124112411241124112411241124112411241124112411241124112411241124", + INIT_2F => X"1123112311231123112311231123112311231123112311231123112311231123", + -- + INIT_30 => X"1123112311231123112311231123112311231123112311231123112311231123", + INIT_31 => X"1124112411241124112411241124112411241124112411241124112411241124", + INIT_32 => X"1125112511251125112511251125112511251125112511251125112511251125", + INIT_33 => X"1126112611261126112611261126112611261126112611261126112611261126", + INIT_34 => X"1127112711271127112711271127112711271127112711271127112711271127", + INIT_35 => X"1128112811281128112811281128112811281128112811281128112811281128", + INIT_36 => X"1129112911291129112911291129112911291129112911291129112911291129", + INIT_37 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A", + INIT_38 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B", + INIT_39 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + INIT_3A => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_3B => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_3C => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F", + INIT_3D => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E", + INIT_3E => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D", + INIT_3F => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C", + -- + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + DIA => i_DIA, -- 16 bit data Input + DIPA => (others => '1'), -- 2 bit data parity Input + ENA => '1', -- 1-bit RAM enable Input + WEA => i_WEA, -- 1-bit Write Enable Input + SSRA => '0', -- 1-bit Synchronous Set/Reset Input + CLKA => i_clockA, -- 1-bit Clock Input + ADDRA => i_ADDRA, -- 10-bit Address Input + DOA => open, -- o_DOA, -- 16-bit Data Output + DOPA => open, -- 2-bit Data Parity Output + -- + DIB => i_DIB, -- 16 bit data Input + DIPB => (others => '1'), -- 2 bit data parity Input + ENB => '1', -- 1-bit RAM enable Input + WEB => i_WEB, -- 1-bit Write Enable Input + SSRB => '0', -- 1-bit Synchronous Set/Reset Input + CLKB => i_clockB, -- 1-bit Clock Input + ADDRB => i_ADDRB, -- 10-bit Address Input + DOB => o_DOB, -- 16-bit Data Output + DOPB => open -- 2-bit Data Parity Output + ); + +end rtl; Index: tags/yavga-0.8.2/trunk/vhdl/README.txt =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/README.txt (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/README.txt (revision 14) @@ -0,0 +1,30 @@ +######################################################## +#### This file is part of the yaVGA project #### +#### http://www.opencores.org/?do=project&who=yavga #### +######################################################## + +FIles: + +charmaps_ROM.vhd + This file is the char map rom initialization. If you like you can modify it using + ../charmaps/convert.sh (it read chars.map and write on the standard output a BRAM + vhdl initialization chunk to be completed...) + +chars_RAM.vhd + This file is the char ram + +README.txt + This file + +s3e_starter_1600k.ucf + The ucf constraint to be used with the DIGILENT s3e_starter_1600k kit + +s3e_starter_1600k.vhd + The top vhdl to use to test the vga controller with the DIGILENT s3e_starter_1600k kit. + The test write random chars to the screen each few seconds. + +vga_ctrl.vhd + The vga controller main file + +waveform_RAM.vhd + This file is the waveform ram Index: tags/yavga-0.8.2/trunk/vhdl/charmaps_ROM.vhd =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/charmaps_ROM.vhd (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/charmaps_ROM.vhd (revision 14) @@ -0,0 +1,180 @@ +-------------------------------------------------------------------------------- +---- ---- +---- This file is part of the yaVGA project ---- +---- http://www.opencores.org/?do=project&who=yavga ---- +---- ---- +---- Description ---- +---- Implementation of yaVGA IP core ---- +---- ---- +---- To Do: ---- +---- ---- +---- ---- +---- Author(s): ---- +---- Sandro Amato, sdroamt@netscape.net ---- +---- ---- +-------------------------------------------------------------------------------- +---- ---- +---- Copyright (c) 2009, Sandro Amato ---- +---- All rights reserved. ---- +---- ---- +---- Redistribution and use in source and binary forms, with or without ---- +---- modification, are permitted provided that the following conditions ---- +---- are met: ---- +---- ---- +---- * Redistributions of source code must retain the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer. ---- +---- * Redistributions in binary form must reproduce the above ---- +---- copyright notice, this list of conditions and the ---- +---- following disclaimer in the documentation and/or other ---- +---- materials provided with the distribution. ---- +---- * Neither the name of SANDRO AMATO nor the names of its ---- +---- contributors may be used to endorse or promote products ---- +---- derived from this software without specific prior written ---- +---- permission. ---- +---- ---- +---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ---- +---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ---- +---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ---- +---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ---- +---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ---- +---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ---- +---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ---- +---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ---- +---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +-------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +library UNISIM; +use UNISIM.VComponents.all; + +entity charmaps_ROM is + port ( + -- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input + -- i_DIP : in std_logic; -- 1-bit parity Input + -- i_EN : in std_logic; -- RAM Enable Input + -- i_WE : in std_logic; -- Write Enable Input + -- i_SSR : in std_logic; -- Synchronous Set/Reset Input + i_clock : in std_logic; -- Clock + i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input + o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output + -- o_DOP : out std_logic -- 1-bit parity Output + ); +end charmaps_ROM; + +architecture rtl of charmaps_ROM is + +begin + -- charmaps + -- |------| |-----------------| + -- | P | | D D D D D D D D | + -- |======| |=================| + -- | 8 | | 7 6 5 4 3 2 1 0 | + -- |======| |=================| + -- | Free | | Row char pixels | + -- |------| |-----------------| + + Inst_charmaps_rom : RAMB16_S9 + generic map ( + write_mode => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + INIT => B"000000000", -- Value of output RAM registers at startup + SRVAL => B"000000000", -- Ouput value upon SSR assertion + -- + INIT_00 => X"000000FF0000FF0000FF0000FF00000000000000000000000000000000000000", + INIT_01 => X"0000242424242424242424242424000000000000FF0000FF0000FF0000FF0000", + INIT_02 => X"0000929292929292929292929292000000004949494949494949494949490000", + INIT_03 => X"0000AAAAAAAAAAAAAAAAAAAAAAAA000000005555555555555555555555550000", + INIT_04 => X"0000F3FCF3FCF3FCF3FCF3FCF3FC00000000FF00FF00FF00FF00FF00FF000000", + INIT_05 => X"00000C030C030C030C030C030C0300000000CF3FCF3FCF3FCF3FCF3FCF3F0000", + INIT_06 => X"00000066666666000066666666000000000030C030C030C030C030C030C00000", + INIT_07 => X"00000F0F0F0F0F0F0F0F0F0F0F0F00000000FF99999999FFFF99999999FF0000", + INIT_08 => X"0000000000000000FFFFFFFFFFFF00000000F0F0F0F0F0F0F0F0F0F0F0F00000", + INIT_09 => X"00000F0F0F0F0F0F0F0F0F0F0F0F00000000FFFFFFFFFFFF0000000000000000", + INIT_0A => X"0000007E42424242424242427E0000000000F0F0F0F0F0F0F0F0F0F0F0F00000", + INIT_0B => X"000024492449244924492449244900000000FF81818181818181818181FF0000", + INIT_0C => X"0000499249924992499249924992000000002492249224922492249224920000", + INIT_0D => X"0000AA55AA55AA55AA55AA55AA550000000055AA55AA55AA55AA55AA55AA0000", + INIT_0E => X"0000DB6DDB6DDB6DDB6DDB6DDB6D00000000DBB6DBB6DBB6DBB6DBB6DBB60000", + INIT_0F => X"0000FFFFFFFFFFFFFFFFFFFFFFFF00000000B66DB66DB66DB66DB66DB66D0000", + INIT_10 => X"0000001000001010101010101010000000000000000000000000000000000000", + INIT_11 => X"0000004444FE4444444444FE4444000000000000000000000044444444440000", + INIT_12 => X"0000000C12924C2010086492906000000000007C921212127C909090927C0000", + INIT_13 => X"000000000000000000101010101000000000007A84848A507090888848300000", + INIT_14 => X"0000001008080404040404080810000000000010202040404040402020100000", + INIT_15 => X"0000000010101010FE101010100000000000009292545438FE38545492920000", + INIT_16 => X"0000000000000000FE0000000000000000000020100808000000000000000000", + INIT_17 => X"0000000000804020100804020000000000000000001818000000000000000000", + INIT_18 => X"0000003810101010101010503010000000000038448282A2928A828244380000", + INIT_19 => X"0000007C820202027C020202827C0000000000FE808080807C020202827C0000", + INIT_1A => X"0000007C820202027C80808080FE00000000001C080808FE8888482818080000", + INIT_1B => X"00000038101010101008040202FE00000000007C828282827C808080807E0000", + INIT_1C => X"000000FC020202027C828282827C00000000007C828282827C828282827C0000", + INIT_1D => X"0000002010080800000018180000000000000000001818000000181800000000", + INIT_1E => X"0000000000FE0000000000FE000000000000000000020C30C0300C0200000000", + INIT_1F => X"0000001000101008040282824438000000000000008060180618608000000000", + INIT_20 => X"00000082828244447C442828281000000000003C42809EA2A29E828244380000", + INIT_21 => X"0000007C8280808080808080827C0000000000FC82828284F884828282FC0000", + INIT_22 => X"000000FE80808080FC80808080FE0000000000F8848482828282848488F00000", + INIT_23 => X"0000007C828282829E808080827C00000000008080808080FC80808080FE0000", + INIT_24 => X"0000003810101010101010101038000000000082828282827C82828282820000", + INIT_25 => X"0000008282848488F088848482820000000000708888080808080808081C0000", + INIT_26 => X"000000828282829292AAAAAAC6820000000000FE808080808080808080800000", + INIT_27 => X"0000007C8282828282828282827C000000000082868A8A8A92A2A2A2C2820000", + INIT_28 => X"0000007A848AB28282828282827C00000000008080808080FC828282827C0000", + INIT_29 => X"0000007C820202027C808080827C000000000082848890A0FC828282827C0000", + INIT_2A => X"0000007C82828282828282828282000000000010101010101010101092FE0000", + INIT_2B => X"00000082C6AAAAAA929282828282000000000010102828284444448282820000", + INIT_2C => X"0000001010101010282844448282000000000082824444283828444482820000", + INIT_2D => X"00000038202020202020202020380000000000FE824040203808040482FE0000", + INIT_2E => X"0000003808080808080808080838000000000000000204081020408000000000", + INIT_2F => X"000000FE00000000000000000000000000000000000000000082442810000000", + INIT_30 => X"0000003AC6828282C63A00000000000000000000000000000008101020200000", + INIT_31 => X"0000003CC2808080C23C000000000000000000B8C6828282C6B8808080800000", + INIT_32 => X"00000038C680FC82C6380000000000000000003AC6828282C63A020202020000", + INIT_33 => X"00000038C6027E82C638000000000000000000808080808080F88080423C0000", + INIT_34 => X"0000000C1210101010100000100000000000008282828282C6B8808080800000", + INIT_35 => X"000000828488B0C0B88680808000000000000070880404040404000004000000", + INIT_36 => X"0000009292929292D2AC0000000000000000000E102020202020202020200000", + INIT_37 => X"00000038C6828282C6380000000000000000008282828282C6B8000000000000", + INIT_38 => X"0000000202027E82C63A000000000000000000808080FC82C6B8000000000000", + INIT_39 => X"0000007C82027E80827C0000000000000000008080808080C6B8000000000000", + INIT_3A => X"0000003AC682828282820000000000000000003C4280808080F8808080800000", + INIT_3B => X"0000006C92929292928200000000000000000010284482828282000000000000", + INIT_3C => X"0000003008083C42820000000000000000000082443828448200000000000000", + INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000", + INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000", + INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000", + -- + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map( + DI => (others => '1'), -- 8-bit Data Input + DIP => (others => '1'), -- 1-bit parity Input + EN => '1', -- RAM Enable Input + WE => '0', -- Write Enable Input + SSR => '0', -- Synchronous Set/Reset Input + CLK => i_clock, -- Clock + ADDR => i_ADDR, -- 11-bit Address Input + DO => o_DO, -- 8-bit Data Output + DOP => open -- 1-bit parity Output + ); + + +end rtl; Index: tags/yavga-0.8.2/trunk/vhdl/s3e_starter_1600k.ucf =================================================================== --- tags/yavga-0.8.2/trunk/vhdl/s3e_starter_1600k.ucf (nonexistent) +++ tags/yavga-0.8.2/trunk/vhdl/s3e_starter_1600k.ucf (revision 14) @@ -0,0 +1,66 @@ +################################################################################ +#### #### +#### This file is part of the yaVGA project #### +#### http://www.opencores.org/?do=project&who=yavga #### +#### #### +#### Description #### +#### Implementation of yaVGA IP core #### +#### #### +#### To Do: #### +#### #### +#### #### +#### Author(s): #### +#### Sandro Amato, sdroamt@netscape.net #### +#### #### +################################################################################ +#### #### +#### Copyright (c) 2009, Sandro Amato #### +#### All rights reserved. #### +#### #### +#### Redistribution and use in source and binary forms, with or without #### +#### modification, are permitted provided that the following conditions #### +#### are met: #### +#### #### +#### * Redistributions of source code must retain the above #### +#### copyright notice, this list of conditions and the #### +#### following disclaimer. #### +#### * Redistributions in binary form must reproduce the above #### +#### copyright notice, this list of conditions and the #### +#### following disclaimer in the documentation and/or other #### +#### materials provided with the distribution. #### +#### * Neither the name of SANDRO AMATO nor the names of its #### +#### contributors may be used to endorse or promote products #### +#### derived from this software without specific prior written #### +#### permission. #### +#### #### +#### THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS #### +#### "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT #### +#### LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS #### +#### FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #### +#### COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, #### +#### INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, #### +#### BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; #### +#### LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER #### +#### CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT #### +#### LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN #### +#### ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE #### +#### POSSIBILITY OF SUCH DAMAGE. #### +################################################################################ + +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "i_clk" LOC = "c9" | IOSTANDARD = LVCMOS33 ; +NET "o_b" LOC = "g15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "o_g" LOC = "h15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "o_hsync" LOC = "f15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "o_r" LOC = "h14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "o_vsync" LOC = "f14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; + +#PACE: Start of PACE Area Constraints +#AREA_GROUP "AG_u1_vga_ctrl" RANGE = SLICE_X84Y109:SLICE_X89Y100 ; +#INST "u1_vga_ctrl" AREA_GROUP = "AG_u1_vga_ctrl" ; + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE