URL
https://opencores.org/ocsvn/yifive/yifive/trunk
Subversion Repositories yifive
Compare Revisions
- This comparison shows the changes necessary to convert path
/yifive/trunk/caravel_yifive/openlane/syntacore
- from Rev 9 to Rev 18
- ↔ Reverse comparison
Rev 9 → Rev 18
/config.tcl
3,7 → 3,7
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set script_dir [file dirname [file normalize [info script]]] |
# Name |
set ::env(DESIGN_NAME) scr1_top_axi |
set ::env(DESIGN_NAME) scr1_top_wb |
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# This is macro |
set ::env(DESIGN_IS_CORE) 0 |
26,34 → 26,36
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# Local sources + no2usb sources |
set ::env(VERILOG_FILES) "\ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv \ |
$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv " |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv \ |
$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv \ |
$script_dir/../../verilog/rtl/lib/sync_fifo.sv " |
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set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore_scr1/src/includes ] |
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ] |
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#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ] |
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