Subversion Repositories yifive

/spi_master/config.tcl

spi_master/config.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: spi_master/pin_order.cfg =================================================================== --- spi_master/pin_order.cfg (nonexistent) +++ spi_master/pin_order.cfg (revision 18) @@ -0,0 +1,36 @@ +#BUS_SORT + +#E +mclk +rst_n +events_o.* + + +#N +spi_mode.* +spi_clk +spi_csn0 +spi_csn1 +spi_csn2 +spi_csn3 +spi_en_tx +spi_sdi0 +spi_sdi1 +spi_sdi2 +spi_sdi3 +spi_sdo0 +spi_sdo1 +spi_sdo2 +spi_sdo3 + + +#N +wbd_ack_o +wbd_err_o +wbd_stb_i +wbd_we_i +wbd_adr_i.* +wbd_dat_i.* +wbd_dat_o.* +wbd_sel_i.* + Index: syntacore/config.tcl =================================================================== --- syntacore/config.tcl (revision 9) +++ syntacore/config.tcl (revision 18) @@ -3,7 +3,7 @@ set script_dir [file dirname [file normalize [info script]]] # Name -set ::env(DESIGN_NAME) scr1_top_axi +set ::env(DESIGN_NAME) scr1_top_wb # This is macro set ::env(DESIGN_IS_CORE) 0 @@ -26,34 +26,36 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv \ - $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv " + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv \ + $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv \ + $script_dir/../../verilog/rtl/lib/sync_fifo.sv " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore_scr1/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ] #set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]