URL
https://opencores.org/ocsvn/yifive/yifive/trunk
Subversion Repositories yifive
Compare Revisions
- This comparison shows the changes necessary to convert path
/yifive/trunk/caravel_yifive/verilog/dv/wb_port
- from Rev 2 to Rev 22
- ↔ Reverse comparison
Rev 2 → Rev 22
/Makefile
26,6 → 26,8
UPRJ_VERILOG_PATH ?= ../../../verilog |
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl |
UPRJ_BEHAVIOURAL_MODELS = ../ |
UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes |
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs |
|
## RISCV GCC |
GCC_PATH?=/ef/apps/bin |
43,11 → 45,14
|
hex: ${PATTERN:=.hex} |
|
vvp: ${PATTERN:=.vvp} |
|
%.vvp: %_tb.v %.hex |
ifeq ($(SIM),RTL) |
iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ |
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ |
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ |
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ |
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ |
$< -o $@ |
else |
iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ |
/wb_port.c
19,6 → 19,27
#include "verilog/dv/caravel/defs.h" |
#include "verilog/dv/caravel/stub.c" |
|
// User Project Slaves (0x3000_0000) |
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000) |
|
#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000) |
#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004) |
#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008) |
#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C) |
#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010) |
#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014) |
#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018) |
#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C) |
#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020) |
#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024) |
#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028) |
#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C) |
#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030) |
#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034) |
#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038) |
#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C) |
|
|
/* |
Wishbone Test: |
- Configures MPRJ lower 8-IO pins as outputs |
30,6 → 51,7
void main() |
{ |
|
int bFail = 0; |
/* |
IO Control Registers |
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | |
80,8 → 102,34
// Flag start of the test |
reg_mprj_datal = 0xAB600000; |
|
reg_mprj_slave = 0x00002710; |
if (reg_mprj_slave == 0x2752) { |
if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1; |
if (reg_mprj_globl_reg2 != 0xAABBCCDD) bFail = 1; |
|
// Write software Write & Read Register |
reg_mprj_globl_reg6 = 0x11223344; |
reg_mprj_globl_reg7 = 0x22334455; |
reg_mprj_globl_reg8 = 0x33445566; |
reg_mprj_globl_reg9 = 0x44556677; |
reg_mprj_globl_reg10 = 0x55667788; |
reg_mprj_globl_reg11 = 0x66778899; |
reg_mprj_globl_reg12 = 0x778899AA; |
reg_mprj_globl_reg13 = 0x8899AABB; |
reg_mprj_globl_reg14 = 0x99AABBCC; |
reg_mprj_globl_reg15 = 0xAABBCCDD; |
|
|
if (reg_mprj_globl_reg6 != 0x11223344) bFail = 1; |
if (reg_mprj_globl_reg7 != 0x22334455) bFail = 1; |
if (reg_mprj_globl_reg8 != 0x33445566) bFail = 1; |
if (reg_mprj_globl_reg9 != 0x44556677) bFail = 1; |
if (reg_mprj_globl_reg10 != 0x55667788) bFail = 1; |
if (reg_mprj_globl_reg11 != 0x66778899) bFail = 1; |
if (reg_mprj_globl_reg12 != 0x778899AA) bFail = 1; |
if (reg_mprj_globl_reg13 != 0x8899AABB) bFail = 1; |
if (reg_mprj_globl_reg14 != 0x99AABBCC) bFail = 1; |
if (reg_mprj_globl_reg15 != 0xAABBCCDD) bFail = 1; |
|
if(bFail == 0) { |
reg_mprj_datal = 0xAB610000; |
} else { |
reg_mprj_datal = 0xAB600000; |
/wb_port_tb.v
47,10 → 47,15
clock = 0; |
end |
|
`ifdef WFDUMP |
initial begin |
$dumpfile("wb_port.vcd"); |
$dumpvars(0, wb_port_tb); |
$dumpvars(0, wb_port_tb.uut.mprj); |
end |
`endif |
|
initial begin |
|
// Repeat cycles of 1000 clock edges as needed to complete testbench |
repeat (30) begin |
repeat (1000) @(posedge clock); |
57,11 → 62,13
// $display("+1000 cycles"); |
end |
$display("%c[1;31m",27); |
$display ("##########################################################"); |
`ifdef GL |
$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed"); |
`else |
$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed"); |
`endif |
$display ("##########################################################"); |
$display("%c[0m",27); |
$finish; |
end |
70,11 → 77,13
wait(checkbits == 16'h AB60); |
$display("Monitor: MPRJ-Logic WB Started"); |
wait(checkbits == 16'h AB61); |
$display ("##########################################################"); |
`ifdef GL |
$display("Monitor: Mega-Project WB (GL) Passed"); |
`else |
$display("Monitor: Mega-Project WB (RTL) Passed"); |
`endif |
$display ("##########################################################"); |
$finish; |
end |
|
102,9 → 111,9
power4 <= 1'b1; |
end |
|
always @(mprj_io) begin |
#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); |
end |
//always @(mprj_io) begin |
// #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); |
//end |
|
wire flash_csb; |
wire flash_clk; |
154,4 → 163,4
); |
|
endmodule |
`default_nettype wire |
`default_nettype wire |