OpenCores
URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /yifive/trunk/caravel_yifive/verilog/rtl/lib
    from Rev 21 to Rev 22
    ↔ Reverse comparison
  •

Rev 21 → Rev 22

/clk_ctl.v
0,0 → 1,126
//////////////////////////////////////////////////////////////////////
//// ////
//// Tubo 8051 cores common library Module ////
//// ////
//// This file is part of the Turbo 8051 cores project ////
//// http://www.opencores.org/cores/turbo8051/ ////
//// ////
//// Description ////
//// Turbo 8051 definitions. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// #################################################################
// Module: clk_ctl
//
// Description: Generic clock control logic , clk-out = mclk/(2+clk_div_ratio)
//
//
// #################################################################
 
 
module clk_ctl (
// Outputs
clk_o,
// Inputs
mclk,
reset_n,
clk_div_ratio
);
 
//---------------------------------
// CLOCK Default Divider value.
// This value will be change from outside
//---------------------------------
parameter WD = 'h1;
 
//---------------------------------------------
// All the input to this block are declared here
// --------------------------------------------
input mclk ;//
input reset_n ;// primary reset signal
input [WD:0] clk_div_ratio ;// primary clock divide ratio
// output clock = selected clock / (div_ratio+1)
//---------------------------------------------
// All the output to this block are declared here
// --------------------------------------------
output clk_o ; // clock out
 
 
//------------------------------------
// Clock Divide func is done here
//------------------------------------
reg [WD-1:0] high_count ; // high level counter
reg [WD-1:0] low_count ; // low level counter
reg mclk_div ; // divided clock
 
 
assign clk_o = mclk_div;
 
always @ (posedge mclk or negedge reset_n)
begin // {
if(reset_n == 1'b0)
begin
high_count <= 'h0;
low_count <= 'h0;
mclk_div <= 'b0;
end
else
begin
if(high_count != 0)
begin // {
high_count <= high_count - 1;
mclk_div <= 1'b1;
end // }
else if(low_count != 0)
begin // {
low_count <= low_count - 1;
mclk_div <= 1'b0;
end // }
else
begin // {
high_count <= clk_div_ratio[WD:1] + clk_div_ratio[0];
low_count <= clk_div_ratio[WD:1] + 1;
mclk_div <= ~mclk_div;
end // }
end // }
end // }
 
 
endmodule
 
/registers.v
0,0 → 1,277
//////////////////////////////////////////////////////////////////////
//// ////
//// Tubo 8051 cores common library Module ////
//// ////
//// This file is part of the Turbo 8051 cores project ////
//// http://www.opencores.org/cores/turbo8051/ ////
//// ////
//// Description ////
//// Turbo 8051 definitions. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/*********************************************************************
** module: bit register
 
** description: infers a register, make it modular
***********************************************************************/
module bit_register (
//inputs
we,
clk,
reset_n,
data_in,
//outputs
data_out
);
 
//---------------------------------
// Reset Default value
//---------------------------------
parameter RESET_DEFAULT = 1'h0;
 
input we;
input clk;
input reset_n;
input data_in;
output data_out;
reg data_out;
//infer the register
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
data_out <= RESET_DEFAULT;
else if (we)
data_out <= data_in;
end // always @ (posedge clk or negedge reset_n)
endmodule // register
 
 
/*********************************************************************
** module: req register.
 
** description: This register is set by cpu writting 1 and reset by
harward req = 1
 
Note: When there is a clash between cpu and hardware, cpu is given higher
priority
 
***********************************************************************/
module req_register (
//inputs
clk,
reset_n,
cpu_we,
cpu_req,
hware_ack,
//outputs
data_out
);
 
//---------------------------------
// Reset Default value
//---------------------------------
parameter RESET_DEFAULT = 1'h0;
 
input clk ;
input reset_n ;
input cpu_we ; // cpu write enable
input cpu_req ; // CPU Request
input hware_ack; // Hardware Ack
output data_out ;
reg data_out;
//infer the register
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
data_out <= RESET_DEFAULT;
else if (cpu_we & cpu_req) // Set on CPU Request
data_out <= 1'b1;
else if (hware_ack) // Reset the flag on Hardware ack
data_out <= 1'b0;
end // always @ (posedge clk or negedge reset_n)
endmodule // register
 
 
/*********************************************************************
** module: req register.
 
** description: This register is cleared by cpu writting 1 and set by
harward req = 1
 
Note: When there is a clash between cpu and hardware,
hardware is given higher priority
 
***********************************************************************/
module stat_register (
//inputs
clk,
reset_n,
cpu_we,
cpu_ack,
hware_req,
//outputs
data_out
);
 
//---------------------------------
// Reset Default value
//---------------------------------
parameter RESET_DEFAULT = 1'h0;
 
input clk ;
input reset_n ;
input cpu_we ; // cpu write enable
input cpu_ack ; // CPU Ack
input hware_req; // Hardware Req
output data_out ;
reg data_out;
//infer the register
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
data_out <= RESET_DEFAULT;
else if (hware_req) // Set the flag on Hardware Req
data_out <= 1'b1;
else if (cpu_we & cpu_ack) // Clear on CPU Ack
data_out <= 1'b0;
end // always @ (posedge clk or negedge reset_n)
endmodule // register
 
 
 
 
 
/*********************************************************************
** copyright message here.
 
** module: generic register
 
***********************************************************************/
module generic_register (
//List of Inputs
we,
data_in,
reset_n,
clk,
//List of Outs
data_out
);
 
parameter WD = 1;
parameter RESET_DEFAULT = 0;
input [WD-1:0] we;
input [WD-1:0] data_in;
input reset_n;
input clk;
output [WD-1:0] data_out;
 
 
generate
genvar i;
for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg
bit_register #(RESET_DEFAULT[i]) u_bit_reg (
.we (we[i]),
.clk (clk),
.reset_n (reset_n),
.data_in (data_in[i]),
.data_out (data_out[i])
);
end
endgenerate
 
 
endmodule
 
 
/*********************************************************************
** copyright message here.
 
** module: generic register
 
***********************************************************************/
module generic_intr_stat_reg (
//inputs
clk,
reset_n,
reg_we,
reg_din,
hware_req,
//outputs
data_out
);
 
parameter WD = 1;
parameter RESET_DEFAULT = 0;
input [WD-1:0] reg_we;
input [WD-1:0] reg_din;
input [WD-1:0] hware_req;
input reset_n;
input clk;
output [WD-1:0] data_out;
 
 
generate
genvar i;
for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg
stat_register #(RESET_DEFAULT[i]) u_bit_reg (
//inputs
. clk (clk ),
. reset_n (reset_n ),
. cpu_we (reg_we[i] ),
. cpu_ack (reg_din[i] ),
. hware_req (hware_req[i] ),
//outputs
. data_out (data_out[i] )
);
 
end
endgenerate
 
 
endmodule
registers.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.