OpenCores
URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core
    from Rev 20 to Rev 21
    Reverse comparison

Rev 20 → Rev 21

/sdrc_core.v
200,6 → 200,30
// Internal Nets
// SDR_REQ_GEN
wire x2a_rdstart;
wire x2a_wrstart;
wire x2a_rdlast;
wire x2a_wrlast;
wire x2a_rdok;
wire x2a_wrnext;
wire x2b_ack;
wire x2b_refresh;
wire x2b_act_ok;
wire x2b_rdok;
wire x2b_wrok;
wire b2x_idle;
wire b2x_req;
wire b2x_start;
wire b2x_last;
wire b2x_wrap;
wire b2x_tras_ok;
wire b2r_ack;
wire b2r_arb_ok;
wire r2b_req;
wire r2b_start;
wire r2b_last;
wire r2b_wrap;
wire r2b_write;
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
wire [1:0] r2b_ba;
wire [12:0] r2b_raddr;
236,6 → 260,8
wire [APP_BW-1:0] app_wr_en_n;
wire [SDR_BW-1:0] a2x_wren_n;
 
wire r2x_idle;
 
//wire [31:0] app_rd_data;
wire [SDR_DW-1:0] x2a_rddt;
 
/sdrc_req_gen.v
267,7 → 267,7
r2b_req = 1'b0;
next_req_st = `REQ_IDLE;
 
case (req_st) // synopsys full_case parallel_case
case (req_st)
 
`REQ_IDLE : begin
r2x_idle = ~req;
/sdrc_xfr_ctl.v
638,7 → 638,7
cntr1_tc or trcar_delay or rfsh_row_cnt or ref_req or sdr_init_done
or precharge_ok or sdram_mode_reg) begin
 
case (mgmt_st) // synopsys full_case parallel_case
case (mgmt_st)
 
`MGM_POWERUP : begin
mgmt_idle = 1'b0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.