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URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

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  • This comparison shows the changes necessary to convert path
    /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src
    from Rev 18 to Rev 20
    Reverse comparison

Rev 18 → Rev 20

/spim_top.sv
53,14 → 53,14
input logic rst_n,
 
 
output logic wbd_stb_i, // strobe/request
output logic [WB_WIDTH-1:0] wbd_adr_i, // address
output logic wbd_we_i, // write
output logic [WB_WIDTH-1:0] wbd_dat_i, // data output
output logic [3:0] wbd_sel_i, // byte enable
input logic [WB_WIDTH-1:0] wbd_dat_o, // data input
input logic wbd_ack_o, // acknowlegement
input logic wbd_err_o, // error
input logic wbd_stb_i, // strobe/request
input logic [WB_WIDTH-1:0] wbd_adr_i, // address
input logic wbd_we_i, // write
input logic [WB_WIDTH-1:0] wbd_dat_i, // data output
input logic [3:0] wbd_sel_i, // byte enable
output logic [WB_WIDTH-1:0] wbd_dat_o, // data input
output logic wbd_ack_o, // acknowlegement
output logic wbd_err_o, // error
 
output logic [1:0] events_o,
 

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