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  • This comparison shows the changes necessary to convert path 
    /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline
    from Rev 11 to Rev 21
    ↔ Reverse comparison
  •

Rev 11 → Rev 21

/scr1_pipe_exu.sv
104,7 → 104,7
// EXU <-> DMEM interface
output logic exu2dmem_req_o, // Data memory request
output logic exu2dmem_cmd_o, // Data memory command - cp.7
output type_scr1_mem_width_e exu2dmem_width_o, // Data memory width
output logic [1:0] exu2dmem_width_o, // Data memory width
output logic [`SCR1_DMEM_AWIDTH-1:0] exu2dmem_addr_o, // Data memory address
output logic [`SCR1_DMEM_DWIDTH-1:0] exu2dmem_wdata_o, // Data memory write data
input logic dmem2exu_req_ack_i, // Data memory request acknowledge
167,10 → 167,10
// Local types declaration
//------------------------------------------------------------------------------
 
typedef enum logic {
SCR1_CSR_INIT,
SCR1_CSR_RDY
} scr1_csr_access_e;
//typedef enum logic {
parameter SCR1_CSR_INIT = 1'b0;
parameter SCR1_CSR_RDY = 1'b1;
//} scr1_csr_access_e;
 
//------------------------------------------------------------------------------
// Local signals declaration
280,8 → 280,8
// CSR signals
//------------------------------------------------------------------------------
// CSR access register
scr1_csr_access_e csr_access_ff;
scr1_csr_access_e csr_access_next;
logic csr_access_ff;
logic csr_access_next;
logic csr_access_init;
 
//------------------------------------------------------------------------------
/scr1_pipe_ialu.sv
80,17 → 80,17
} type_scr1_ialu_flags_s;
 
`ifdef SCR1_RVM_EXT
typedef enum logic [1:0] {
SCR1_IALU_MDU_FSM_IDLE,
SCR1_IALU_MDU_FSM_ITER,
SCR1_IALU_MDU_FSM_CORR
} type_scr1_ialu_fsm_state;
//typedef enum logic [1:0] {
parameter SCR1_IALU_MDU_FSM_IDLE = 2'b00;
parameter SCR1_IALU_MDU_FSM_ITER = 2'b01;
parameter SCR1_IALU_MDU_FSM_CORR = 2'b10;
//} type_scr1_ialu_fsm_state;
 
typedef enum logic [1:0] {
SCR1_IALU_MDU_NONE,
SCR1_IALU_MDU_MUL,
SCR1_IALU_MDU_DIV
} type_scr1_ialu_mdu_cmd;
//typedef enum logic [1:0] {
parameter SCR1_IALU_MDU_NONE = 2'b00;
parameter SCR1_IALU_MDU_MUL = 2'b01;
parameter SCR1_IALU_MDU_DIV = 2'b10;
//} type_scr1_ialu_mdu_cmd;
`endif // SCR1_RVM_EXT
 
//-------------------------------------------------------------------------------
123,8 → 123,8
logic rem_corr_req; // Correction request for REM(U) operations
 
// MUL/DIV FSM signals
type_scr1_ialu_fsm_state mdu_fsm_ff; // Current FSM state
type_scr1_ialu_fsm_state mdu_fsm_next; // Next FSM state
logic [1:0] mdu_fsm_ff; // Current FSM state
logic [1:0] mdu_fsm_next; // Next FSM state
logic mdu_fsm_idle; // MDU FSM is in IDLE state
`ifdef SCR1_TRGT_SIMULATION
logic mdu_fsm_iter; // MDU FSM is in ITER state
132,7 → 132,7
logic mdu_fsm_corr; // MDU FSM is in CORR state
 
// MDU command signals
type_scr1_ialu_mdu_cmd mdu_cmd; // MDU command: 00 - NONE, 01 - MUL, 10 - DIV
logic [1:0] mdu_cmd; // MDU command: 00 - NONE, 01 - MUL, 10 - DIV
logic mdu_cmd_mul; // MDU command is MUL(HSU)
logic mdu_cmd_div; // MDU command is DIV(U)/REM(U)
logic [1:0] mul_cmd; // MUL command: 00 - MUL, 01 - MULH, 10 - MULHSU, 11 - MULHU
/scr1_pipe_idu.sv
57,8 → 57,8
//-------------------------------------------------------------------------------
 
logic [`SCR1_IMEM_DWIDTH-1:0] instr;
type_scr1_instr_type_e instr_type;
type_scr1_rvi_opcode_e rvi_opcode;
logic [1:0] instr_type;
logic [6:2] rvi_opcode;
logic rvi_illegal;
logic [2:0] funct3;
logic [6:0] funct7;
80,19 → 80,10
assign instr = ifu2idu_instr_i;
 
// RVI / RVC
`ifdef YOSYS
assign instr_type = 2'(instr[1:0]);
`else
assign instr_type = instr[1:0];
 
assign instr_type = type_scr1_instr_type_e'(instr[1:0]);
`endif
 
// RVI / RVC fields
`ifdef YOSYS
assign rvi_opcode = 5'(instr[6:2]); // RVI
`else
assign rvi_opcode = type_scr1_rvi_opcode_e'(instr[6:2]); // RVI
`endif
assign rvi_opcode = instr[6:2]; // RVI
assign funct3 = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
assign funct7 = instr[31:25]; // RVI
assign funct12 = instr[31:20]; // RVI (SYSTEM)
/scr1_pipe_ifu.sv
40,10 → 40,10
// IFU <-> IMEM interface
input logic imem2ifu_req_ack_i, // Instruction memory request acknowledgement
output logic ifu2imem_req_o, // Instruction memory request
output type_scr1_mem_cmd_e ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
output logic ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
output logic [`SCR1_IMEM_AWIDTH-1:0] ifu2imem_addr_o, // Instruction memory address
input logic [`SCR1_IMEM_DWIDTH-1:0] imem2ifu_rdata_i, // Instruction memory read data
input type_scr1_mem_resp_e imem2ifu_resp_i, // Instruction memory response
input logic [1:0] imem2ifu_resp_i, // Instruction memory response
 
// IFU <-> EXU New PC interface
input logic exu2ifu_pc_new_req_i, // New PC request (jumps, branches, traps etc)
88,22 → 88,22
// Local types declaration
//------------------------------------------------------------------------------
 
typedef enum logic {
SCR1_IFU_FSM_IDLE,
SCR1_IFU_FSM_FETCH
} type_scr1_ifu_fsm_e;
//typedef enum logic {
parameter SCR1_IFU_FSM_IDLE = 1'b0;
parameter SCR1_IFU_FSM_FETCH = 1'b1;
//} type_scr1_ifu_fsm_e;
 
typedef enum logic[1:0] {
SCR1_IFU_QUEUE_WR_NONE, // No write to queue
SCR1_IFU_QUEUE_WR_FULL, // Write 32 rdata bits to queue
SCR1_IFU_QUEUE_WR_HI // Write 16 upper rdata bits to queue
} type_scr1_ifu_queue_wr_e;
//typedef enum logic[1:0] {
parameter SCR1_IFU_QUEUE_WR_NONE = 2'b00; // No write to queue
parameter SCR1_IFU_QUEUE_WR_FULL = 2'b01; // Write 32 rdata bits to queue
parameter SCR1_IFU_QUEUE_WR_HI = 2'b10; // Write 16 upper rdata bits to queue
//} type_scr1_ifu_queue_wr_e;
 
typedef enum logic[1:0] {
SCR1_IFU_QUEUE_RD_NONE, // No queue read
SCR1_IFU_QUEUE_RD_HWORD, // Read halfword
SCR1_IFU_QUEUE_RD_WORD // Read word
} type_scr1_ifu_queue_rd_e;
//typedef enum logic[1:0] {
parameter SCR1_IFU_QUEUE_RD_NONE = 2'b00; // No queue read
parameter SCR1_IFU_QUEUE_RD_HWORD = 2'b01; // Read halfword
parameter SCR1_IFU_QUEUE_RD_WORD = 2'b10; // Read word
//} type_scr1_ifu_queue_rd_e;
 
`ifdef SCR1_NO_DEC_STAGE
typedef enum logic[1:0] {
114,17 → 114,17
} type_scr1_bypass_e;
`endif // SCR1_NO_DEC_STAGE
 
typedef enum logic [2:0] {
//typedef enum logic [2:0] {
// SCR1_IFU_INSTR_<UPPER_16_BITS>_<LOWER_16_BITS>
SCR1_IFU_INSTR_NONE, // No valid instruction
SCR1_IFU_INSTR_RVI_HI_RVI_LO, // Full RV32I instruction
SCR1_IFU_INSTR_RVC_RVC,
SCR1_IFU_INSTR_RVI_LO_RVC,
SCR1_IFU_INSTR_RVC_RVI_HI,
SCR1_IFU_INSTR_RVI_LO_RVI_HI,
SCR1_IFU_INSTR_RVC_NV, // Instruction after unaligned new_pc
SCR1_IFU_INSTR_RVI_LO_NV // Instruction after unaligned new_pc
} type_scr1_ifu_instr_e;
parameter SCR1_IFU_INSTR_NONE = 3'b000 ; // No valid instruction
parameter SCR1_IFU_INSTR_RVI_HI_RVI_LO = 3'b001 ; // Full RV32I instruction
parameter SCR1_IFU_INSTR_RVC_RVC = 3'b010 ;
parameter SCR1_IFU_INSTR_RVI_LO_RVC = 3'b011 ;
parameter SCR1_IFU_INSTR_RVC_RVI_HI = 3'b100 ;
parameter SCR1_IFU_INSTR_RVI_LO_RVI_HI = 3'b101 ;
parameter SCR1_IFU_INSTR_RVC_NV = 3'b110 ; // Instruction after unaligned new_pc
parameter SCR1_IFU_INSTR_RVI_LO_NV = 3'b111 ; // Instruction after unaligned new_pc
//} type_scr1_ifu_instr_e;
 
//------------------------------------------------------------------------------
// Local signals declaration
141,7 → 141,7
// IMEM instruction type decoder
logic instr_hi_is_rvi;
logic instr_lo_is_rvi;
type_scr1_ifu_instr_e instr_type;
logic [2:0] instr_type;
 
// Register to store if the previous IMEM instruction had low part of RVI instruction
// in its high part
149,11 → 149,11
logic instr_hi_rvi_lo_next;
 
// Queue read/write size decoders
type_scr1_ifu_queue_rd_e q_rd_size;
logic [1:0] q_rd_size;
logic q_rd_vd;
logic q_rd_none;
logic q_rd_hword;
type_scr1_ifu_queue_wr_e q_wr_size;
logic [1:0] q_wr_size;
logic q_wr_none;
logic q_wr_full;
 
196,8 → 196,8
logic ifu_fetch_req;
logic ifu_stop_req;
 
type_scr1_ifu_fsm_e ifu_fsm_curr;
type_scr1_ifu_fsm_e ifu_fsm_next;
logic ifu_fsm_curr;
logic ifu_fsm_next;
logic ifu_fsm_fetch;
 
// IMEM signals
/scr1_pipe_lsu.sv
51,13 → 51,13
 
// LSU <-> DMEM interface
output logic lsu2dmem_req_o, // Data memory request
output type_scr1_mem_cmd_e lsu2dmem_cmd_o, // Data memory command (READ/WRITE)
output type_scr1_mem_width_e lsu2dmem_width_o, // Data memory data width
output logic lsu2dmem_cmd_o, // Data memory command (READ/WRITE)
output logic [1:0] lsu2dmem_width_o, // Data memory data width
output logic [`SCR1_DMEM_AWIDTH-1:0] lsu2dmem_addr_o, // Data memory address
output logic [`SCR1_DMEM_DWIDTH-1:0] lsu2dmem_wdata_o, // Data memory write data
input logic dmem2lsu_req_ack_i, // Data memory request acknowledge
input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2lsu_rdata_i, // Data memory read data
input type_scr1_mem_resp_e dmem2lsu_resp_i // Data memory response
input logic [1:0] dmem2lsu_resp_i // Data memory response
);
 
//------------------------------------------------------------------------------
64,10 → 64,10
// Local types declaration
//------------------------------------------------------------------------------
 
typedef enum logic {
SCR1_LSU_FSM_IDLE,
SCR1_LSU_FSM_BUSY
} type_scr1_lsu_fsm_e;
//typedef enum logic {
parameter SCR1_LSU_FSM_IDLE = 1'b0;
parameter SCR1_LSU_FSM_BUSY = 1'b1;
//} type_scr1_lsu_fsm_e;
 
//------------------------------------------------------------------------------
// Local signals declaration
74,8 → 74,8
//------------------------------------------------------------------------------
 
// LSU FSM signals
type_scr1_lsu_fsm_e lsu_fsm_curr; // LSU FSM current state
type_scr1_lsu_fsm_e lsu_fsm_next; // LSU FSM next state
logic lsu_fsm_curr; // LSU FSM current state
logic lsu_fsm_next; // LSU FSM next state
logic lsu_fsm_idle; // LSU FSM is in IDLE state
 
// LSU Command register signals
/scr1_pipe_mprf.sv
60,7 → 60,7
logic [`SCR1_XLEN-1:0] mprf_int2 [1:`SCR1_MPRF_SIZE-1];
`endif
`else // distributed logic implementation
type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf_int;
logic [`SCR1_XLEN-1:0] mprf_int [1:`SCR1_MPRF_SIZE-1];
`endif
 
//------------------------------------------------------------------------------
/scr1_pipe_top.sv
3,6 → 3,14
/// @brief SCR1 pipeline top
///
 
//----------------------------------------------------------------------------------
// project : YiFive
// Rev: June 10, 2021, Dinesh A
// Bugfix- reset correction for scr1_pipe_tdu when debug is not enabled
// Note: previously reset rst_n is floating at simulation is failing
// when SCR1_DBG_EN is disabled
//---------------------------------------------------------------------------------
 
`include "scr1_arch_description.svh"
`include "scr1_memif.svh"
`include "scr1_riscv_isa_decoding.svh"
31,21 → 39,21
 
// Instruction Memory Interface
output logic pipe2imem_req_o, // IMEM request
output type_scr1_mem_cmd_e pipe2imem_cmd_o, // IMEM command
output logic pipe2imem_cmd_o, // IMEM command
output logic [`SCR1_IMEM_AWIDTH-1:0] pipe2imem_addr_o, // IMEM address
input logic imem2pipe_req_ack_i, // IMEM request acknowledge
input logic [`SCR1_IMEM_DWIDTH-1:0] imem2pipe_rdata_i, // IMEM read data
input type_scr1_mem_resp_e imem2pipe_resp_i, // IMEM response
input logic [1:0] imem2pipe_resp_i, // IMEM response
 
// Data Memory Interface
output logic pipe2dmem_req_o, // DMEM request
output type_scr1_mem_cmd_e pipe2dmem_cmd_o, // DMEM command
output type_scr1_mem_width_e pipe2dmem_width_o, // DMEM data width
output logic pipe2dmem_cmd_o, // DMEM command
output logic [1:0] pipe2dmem_width_o, // DMEM data width
output logic [`SCR1_DMEM_AWIDTH-1:0] pipe2dmem_addr_o, // DMEM address
output logic [`SCR1_DMEM_DWIDTH-1:0] pipe2dmem_wdata_o, // DMEM write data
input logic dmem2pipe_req_ack_i, // DMEM request acknowledge
input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2pipe_rdata_i, // DMEM read data
input type_scr1_mem_resp_e dmem2pipe_resp_i, // DMEM response
input logic [1:0] dmem2pipe_resp_i, // DMEM response
 
`ifdef SCR1_DBG_EN
// Debug interface:
167,7 → 175,7
logic exu2csr_take_exc; // Take exception trap
logic exu2csr_mret_update; // MRET update CSR
logic exu2csr_mret_instr; // MRET instruction
type_scr1_exc_code_e exu2csr_exc_code; // Exception code (see scr1_arch_types.svh)
logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code; // Exception code (see scr1_arch_types.svh)
logic [`SCR1_XLEN-1:0] exu2csr_trap_val; // Trap value
logic [`SCR1_XLEN-1:0] csr2exu_new_pc; // Exception/IRQ/MRET new PC
logic csr2exu_irq; // IRQ request
589,7 → 597,7
`ifdef SCR1_DBG_EN
.rst_n (dbg_rst_n ),
`else
.rst_n (rst_n ),
.rst_n (pipe_rst_n ), // dinesh-a: Bugfix- reset correction when debug is not enabled
`endif // SCR1_DBG_EN
.clk (clk ),
.clk_en (1'b1 ),
/scr1_tracelog.sv
18,7 → 18,7
`ifdef SCR1_MPRF_RAM
input logic [`SCR1_XLEN-1:0] mprf2trace_int_i [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
`else // SCR1_MPRF_RAM
input type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf2trace_int_i, // MPRF registers content
logic [`SCR1_XLEN-1:0] mprf2trace_int_i[1:`SCR1_MPRF_SIZE-1], // MPRF registers content
`endif // SCR1_MPRF_RAM
input logic mprf2trace_wr_en_i, // MPRF write enable
input logic [`SCR1_MPRF_AWIDTH-1:0] mprf2trace_wr_addr_i, // MPRF write address
48,7 → 48,7
input logic [`SCR1_XLEN-1:2] csr2trace_mepc_i, // CSR MEPC register
`endif // SCR1_RVC_EXT
input logic csr2trace_mcause_irq_i, // CSR MCAUSE.interrupt bit
input type_scr1_exc_code_e csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit
input [SCR1_EXC_CODE_WIDTH_E-1:0] csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit
input logic [`SCR1_XLEN-1:0] csr2trace_mtval_i, // CSR MTVAL register
input logic csr2trace_mstatus_mie_up_i, // CSR MSTATUS.mie update flag
 
430,7 → 430,7
`else // SCR1_RVC_EXT
{csr2trace_mepc_i, 2'b00};
`endif // SCR1_RVC_EXT
csr_trace1.mcause = {csr2trace_mcause_irq_i, type_scr1_csr_mcause_ec_v'(csr2trace_mcause_ec_i)};
csr_trace1.mcause = {csr2trace_mcause_irq_i, csr2trace_mcause_ec_i};
csr_trace1.mtval = csr2trace_mtval_i;
 
csr_trace1.mstatus = '0;

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