URL
https://opencores.org/ocsvn/yifive/yifive/trunk
Subversion Repositories yifive
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- This comparison shows the changes necessary to convert path
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/scr1_dmem_wb.sv
337,6 → 337,7
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wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in}; |
wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_dout; |
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sync_fifo #( |
.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width |
363,6 → 364,7
wire [SCR1_WB_WIDTH-1:0] hwdata_out; |
wire [3:0] hbel_out; |
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assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout; |
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always_ff @(posedge clk) begin |