URL
https://opencores.org/ocsvn/yifive/yifive/trunk
Subversion Repositories yifive
Compare Revisions
- This comparison shows the changes necessary to convert path
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore
- from Rev 11 to Rev 19
- ↔ Reverse comparison
Rev 11 → Rev 19
/scr1/src/top/scr1_dmem_wb.sv
339,18 → 339,17
wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in}; |
|
sync_fifo #( |
.DATA_WIDTH(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width |
.ADDR_WIDTH(1), // Address Width |
.FIFO_DEPTH(2) // FIFO DEPTH |
.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width |
.D(2) // FIFO DEPTH |
) u_req_fifo( |
|
.dout (req_fifo_dout ), |
.rd_data (req_fifo_dout ), |
|
.rstn (rst_n ), |
.reset_n (rst_n ), |
.clk (clk ), |
.wr_en (req_fifo_wr ), // Write |
.rd_en (req_fifo_rd ), // Read |
.din (req_fifo_din ), |
.wr_data (req_fifo_din ), |
.full (req_fifo_full ), |
.empty (req_fifo_empty ) |
); |
/scr1/src/top/scr1_imem_wb.sv
168,18 → 168,17
|
|
sync_fifo #( |
.DATA_WIDTH(SCR1_WB_WIDTH), // Data Width |
.ADDR_WIDTH(1), // Address Width |
.FIFO_DEPTH(2) // FIFO DEPTH |
.W(SCR1_WB_WIDTH), // Data Width |
.D(2) // FIFO DEPTH |
) u_req_fifo( |
|
.dout (req_fifo_dout ), |
.rd_data (req_fifo_dout ), |
|
.rstn (rst_n ), |
.reset_n (rst_n ), |
.clk (clk ), |
.wr_en (req_fifo_wr ), // Write |
.rd_en (req_fifo_rd ), // Read |
.din (imem_addr ), |
.wr_data (imem_addr ), |
.full (req_fifo_full ), |
.empty (req_fifo_empty ) |
); |
/scr1/src/wb_top.files
1,5 → 1,4
top/scr1_dmem_router.sv |
top/scr1_imem_router.sv |
top/scr1_dp_memory.sv |
top/scr1_tcm.sv |
top/scr1_timer.sv |
6,4 → 5,4
top/scr1_dmem_wb.sv |
top/scr1_imem_wb.sv |
top/scr1_top_wb.sv |
../../lib/sync_fifo.sv |
../../../lib/sync_fifo.sv |