URL
https://opencores.org/ocsvn/yifive/yifive/trunk
Subversion Repositories yifive
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- This comparison shows the changes necessary to convert path
/yifive/trunk/caravel_yifive
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/verilog/rtl/syntacore_scr1/synth/Makefile
4,7 → 4,7
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# Paths |
export ROOT_DIR := $(shell pwd) |
export DESIGN_FILE := $(ROOT_DIR)/pyfive.sv |
export DESIGN_FILE := $(ROOT_DIR)/syntacore.sv |
export SYNTH_LOG := $(ROOT_DIR)/synth.log |
export REPORT_DIR := $(ROOT_DIR)/reports |
export NETLIST_DIR := $(ROOT_DIR)/netlist |
31,35 → 31,35
# to fix this issue, we have concatinated all the rtl file into single file before starting synthesis |
# only memory are exclded from this list |
# ################################################ |
cat ../src/core/pipeline/scr1_pipe_top.sv > pyfive.sv; |
cat ../src/core/scr1_core_top.sv >> pyfive.sv; |
cat ../src/core/scr1_dm.sv >> pyfive.sv; |
cat ../src/core/scr1_tapc_synchronizer.sv >> pyfive.sv; |
cat ../src/core/scr1_clk_ctrl.sv >> pyfive.sv; |
cat ../src/core/scr1_scu.sv >> pyfive.sv; |
cat ../src/core/scr1_tapc.sv >> pyfive.sv; |
cat ../src/core/scr1_tapc_shift_reg.sv >> pyfive.sv; |
cat ../src/core/scr1_dmi.sv >> pyfive.sv; |
cat ../src/core/primitives/scr1_reset_cells.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_ifu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_idu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_exu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_mprf.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_csr.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_ialu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_lsu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_hdu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_tdu.sv >> pyfive.sv; |
cat ../src/core/pipeline/scr1_ipic.sv >> pyfive.sv; |
cat ../src/top/scr1_dmem_router.sv >> pyfive.sv; |
cat ../src/top/scr1_imem_router.sv >> pyfive.sv; |
#cat ../src/top/scr1_dp_memory.sv >> pyfive.sv; |
cat ../src/top/scr1_tcm.sv >> pyfive.sv; |
cat ../src/top/scr1_timer.sv >> pyfive.sv; |
#cat ../src/top/scr1_dmem_ahb.sv >> pyfive.sv; |
#cat ../src/top/scr1_imem_ahb.sv >> pyfive.sv; |
cat ../src/top/scr1_top_axi.sv >> pyfive.sv; |
cat ../src/top/scr1_mem_axi.sv>> pyfive.sv; |
cat ../src/core/pipeline/scr1_pipe_top.sv > syntacore.sv; |
cat ../src/core/scr1_core_top.sv >> syntacore.sv; |
cat ../src/core/scr1_dm.sv >> syntacore.sv; |
cat ../src/core/scr1_tapc_synchronizer.sv >> syntacore.sv; |
cat ../src/core/scr1_clk_ctrl.sv >> syntacore.sv; |
cat ../src/core/scr1_scu.sv >> syntacore.sv; |
cat ../src/core/scr1_tapc.sv >> syntacore.sv; |
cat ../src/core/scr1_tapc_shift_reg.sv >> syntacore.sv; |
cat ../src/core/scr1_dmi.sv >> syntacore.sv; |
cat ../src/core/primitives/scr1_reset_cells.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_ifu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_idu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_exu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_mprf.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_csr.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_ialu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_lsu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_hdu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_pipe_tdu.sv >> syntacore.sv; |
cat ../src/core/pipeline/scr1_ipic.sv >> syntacore.sv; |
cat ../src/top/scr1_dmem_router.sv >> syntacore.sv; |
cat ../src/top/scr1_imem_router.sv >> syntacore.sv; |
#cat ../src/top/scr1_dp_memory.sv >> syntacore.sv; |
cat ../src/top/scr1_tcm.sv >> syntacore.sv; |
cat ../src/top/scr1_timer.sv >> syntacore.sv; |
#cat ../src/top/scr1_dmem_ahb.sv >> syntacore.sv; |
#cat ../src/top/scr1_imem_ahb.sv >> syntacore.sv; |
cat ../src/top/scr1_top_axi.sv >> syntacore.sv; |
cat ../src/top/scr1_mem_axi.sv>> syntacore.sv; |
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/verilog/rtl/syntacore_scr1/synth/synth.tcl
27,7 → 27,7
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# Change if needed |
set ::env(VERILOG_FILES) [glob \ |
$::env(DESIGN_DIR)/synth/pyfive.sv ] |
$::env(DESIGN_DIR)/synth/syntacore.sv ] |
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#set ::env(VERILOG_FILES_BLACKBOX) [glob \ |
# $::env(DESIGN_DIR)/src/top/scr1_dp_memory.sv ] |