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/trunk/src/testbench/External_IP/uart16550/doc/src/UART_spec.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/src/testbench/External_IP/uart16550/doc/src/UART_spec.doc

trunk/src/testbench/External_IP/uart16550/doc/src/UART_spec.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/src/testbench/External_IP/uart16550/doc/UART_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/src/testbench/External_IP/uart16550/doc/UART_spec.pdf =================================================================== --- trunk/src/testbench/External_IP/uart16550/doc/UART_spec.pdf (revision 57) +++ trunk/src/testbench/External_IP/uart16550/doc/UART_spec.pdf (nonexistent)

trunk/src/testbench/External_IP/uart16550/doc/UART_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/src/testbench/zap_tb.v =================================================================== --- trunk/src/testbench/zap_tb.v (revision 57) +++ trunk/src/testbench/zap_tb.v (nonexistent) @@ -1,183 +0,0 @@ -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- - - -`default_nettype none -`include "zap_defines.vh" - -module zap_test; - -// CPU config. -parameter RAM_SIZE = 32768; -parameter DATA_SECTION_TLB_ENTRIES = 4; -parameter DATA_LPAGE_TLB_ENTRIES = 8; -parameter DATA_SPAGE_TLB_ENTRIES = 16; -parameter DATA_CACHE_SIZE = 1024; -parameter CODE_SECTION_TLB_ENTRIES = 4; -parameter CODE_LPAGE_TLB_ENTRIES = 8; -parameter CODE_SPAGE_TLB_ENTRIES = 16; -parameter CODE_CACHE_SIZE = 1024; -parameter FIFO_DEPTH = 4; -parameter BP_ENTRIES = 1024; -parameter STORE_BUFFER_DEPTH = 32; - -// TB related. -parameter START = 1992; -parameter COUNT = 120; - -// Variables -reg i_clk = 1'd0; -reg i_reset = 1'd0; -wire [1:0] uart_in; -wire [1:0] uart_out; -integer i; -reg [3:0] clk_ctr = 4'd0; -integer seed = `SEED; -integer seed_new = `SEED + 1; - -// Clock generator. -always #10 i_clk = !i_clk; - -wire w_wb_stb; -wire w_wb_cyc; -wire [31:0] w_wb_dat_to_ram; -wire [31:0] w_wb_adr; -wire [3:0] w_wb_sel; -wire w_wb_we; -wire w_wb_ack; -wire [31:0] w_wb_dat_from_ram; - -// DUT -chip_top #( - .FIFO_DEPTH(FIFO_DEPTH), - .BP_ENTRIES(BP_ENTRIES), - .STORE_BUFFER_DEPTH(STORE_BUFFER_DEPTH), - .DATA_SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES), - .DATA_LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES), - .DATA_SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES), - .DATA_CACHE_SIZE(DATA_CACHE_SIZE), - .CODE_SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES), - .CODE_LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES), - .CODE_SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES), - .CODE_CACHE_SIZE(CODE_CACHE_SIZE) - -) u_chip_top ( - .SYS_CLK (i_clk), - .SYS_RST (i_reset), - .UART0_RXD(uart_in[0]), - .UART0_TXD(uart_out[0]), - .UART1_RXD(uart_in[1]), - .UART1_TXD(uart_out[1]), - .I_IRQ (28'd0), - .I_FIQ (1'd0), - .O_WB_STB (w_wb_stb), - .O_WB_CYC (w_wb_cyc), - .O_WB_DAT (w_wb_dat_to_ram), - .O_WB_ADR (w_wb_adr), - .O_WB_SEL (w_wb_sel), - .O_WB_WE (w_wb_we), - .I_WB_ACK (w_wb_ack), - .I_WB_DAT (w_wb_dat_from_ram) -); - -// RAM -ram #(.SIZE_IN_BYTES(RAM_SIZE)) u_ram ( - .i_clk(i_clk), - .i_wb_stb (w_wb_stb), - .i_wb_cyc (w_wb_cyc), - .i_wb_dat (w_wb_dat_to_ram), - .i_wb_adr (w_wb_adr), - .i_wb_sel (w_wb_sel), - .i_wb_we (w_wb_we), - .o_wb_ack (w_wb_ack), - .o_wb_dat (w_wb_dat_from_ram) -); - -// UART 0 dumper. -uart_tx_dumper #(.P(0)) UARTTX0 ( - .i_clk (i_clk), - .i_line (uart_out[0]) -); - -// UART 1 dumper. -uart_tx_dumper #(.P(1)) UARTTX1 ( - .i_clk (i_clk), - .i_line (uart_out[1]) -); - -// UART 0 logger. -uart_rx_logger #(.P(0)) UARTRX0 ( - .i_clk (i_clk), - .o_line (uart_in[0]) -); - -// UART 1 logger. -uart_rx_logger #(.P(1)) UARTRX1 ( - .i_clk (i_clk), - .o_line (uart_in[1]) -); - -// Run for MAX_CLOCK_CYCLES -initial -begin - $display("SEED in decimal = %d", `SEED ); - $display("parameter RAM_SIZE = %d", RAM_SIZE ); - $display("parameter START = %d", START ); - $display("parameter COUNT = %d", COUNT ); - $display("parameter FIFO_DEPTH = %d", u_chip_top.FIFO_DEPTH ); - $display("parameter DATA_SECTION_TLB_ENTRIES = %d", DATA_SECTION_TLB_ENTRIES ) ; - $display("parameter DATA_LPAGE_TLB_ENTRIES = %d", DATA_LPAGE_TLB_ENTRIES ) ; - $display("parameter DATA_SPAGE_TLB_ENTRIES = %d", DATA_SPAGE_TLB_ENTRIES ) ; - $display("parameter DATA_CACHE_SIZE = %d", DATA_CACHE_SIZE ) ; - $display("parameter CODE_SECTION_TLB_ENTRIES = %d", CODE_SECTION_TLB_ENTRIES ) ; - $display("parameter CODE_LPAGE_TLB_ENTRIES = %d", CODE_LPAGE_TLB_ENTRIES ) ; - $display("parameter CODE_SPAGE_TLB_ENTRIES = %d", CODE_SPAGE_TLB_ENTRIES ) ; - $display("parameter CODE_CACHE_SIZE = %d", CODE_CACHE_SIZE ) ; - $display("parameter STORE_BUFFER_DEPTH = %d", STORE_BUFFER_DEPTH ) ; - - `ifdef WAVES - $dumpfile(`VCD_FILE_PATH); - $dumpvars; - `endif - - @(posedge i_clk); - i_reset <= 1; - @(posedge i_clk); - i_reset <= 0; - - if (`MAX_CLOCK_CYCLES == 0 ) - begin - forever @(negedge i_clk); - end - else - begin - repeat(`MAX_CLOCK_CYCLES) - @(negedge i_clk); - end - - `include "zap_check.vh" -end - -endmodule // zap_tb - -`default_nettype wire Index: trunk/src/testbench/ram.v =================================================================== --- trunk/src/testbench/ram.v (revision 57) +++ trunk/src/testbench/ram.v (nonexistent) @@ -1,102 +0,0 @@ -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- - -`default_nettype none - -module ram #(parameter SIZE_IN_BYTES = 4096) ( - -input wire i_clk, -input wire i_wb_cyc, -input wire i_wb_stb, -input wire [31:0] i_wb_adr, -input wire [31:0] i_wb_dat, -input wire [3:0] i_wb_sel, -input wire i_wb_we, -output reg [31:0] o_wb_dat = 32'd0, -output reg o_wb_ack = 1'd0 - -); - -`include "zap_defines.vh" -`include "zap_localparams.vh" -`include "zap_functions.vh" - -integer seed = `SEED; -reg [31:0] ram [SIZE_IN_BYTES/4 -1:0]; - -// Initialize the RAM with the generated image. -initial -begin:blk1 - integer i; - integer j; - - reg [7:0] mem [SIZE_IN_BYTES-1:0]; - - j = 0; - - for ( i=0;i> 2 ]; - end - else if ( i_wb_we && i_wb_cyc && i_wb_stb && !stall ) - begin - o_wb_ack <= 1'd1; - o_wb_dat <= 'dx; - - if ( i_wb_sel[0] ) ram [ i_wb_adr >> 2 ][7:0] <= i_wb_dat[7:0]; - if ( i_wb_sel[1] ) ram [ i_wb_adr >> 2 ][15:8] <= i_wb_dat[15:8]; - if ( i_wb_sel[2] ) ram [ i_wb_adr >> 2 ][23:16] <= i_wb_dat[23:16]; - if ( i_wb_sel[3] ) ram [ i_wb_adr >> 2 ][31:24] <= i_wb_dat[31:24]; - end - else - begin - o_wb_ack <= 1'd0; - o_wb_dat <= 'dx; - end - end - -endmodule // ram - -`default_nettype wire Index: trunk/src/testbench/timer.v =================================================================== --- trunk/src/testbench/timer.v (revision 57) +++ trunk/src/testbench/timer.v (nonexistent) @@ -1,270 +0,0 @@ -`default_nettype none - -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- -// -- -// This is a Wishbone timer peripheral with simple controls. -- -// -- -// Registers: -// 0x0 (DEVEN) - 0x1 to enable the timer unit. 0x0 to disable the unit. -- -// 0x4 (DEVPR) - Timer length in number of Wishbone clocks. -- -// 0x8 (DEVAK) - Write: 0x1 to acknowledge interrupt. Read: 0x1 reveals timer -- -// interrupt occured. -- -// 0xC (DEVST) - 0x1 to start the timer. Write only. Always reads 0x0. -- -// -- -// ------------------------------------------------------------------------------ - -module timer #( - - // Register addresses. - parameter [31:0] TIMER_ENABLE_REGISTER = 32'h0, - parameter [31:0] TIMER_LIMIT_REGISTER = 32'h4, - parameter [31:0] TIMER_INTACK_REGISTER = 32'h8, - parameter [31:0] TIMER_START_REGISTER = 32'hC - -) ( - -// Clock and reset. -input wire i_clk, -input wire i_rst, - -// Wishbone interface. -input wire [31:0] i_wb_dat, -input wire [3:0] i_wb_adr, -input wire i_wb_stb, -input wire i_wb_cyc, -input wire i_wb_wen, -input wire [3:0] i_wb_sel, -output reg [31:0] o_wb_dat, -output reg o_wb_ack, - - -// Interrupt output. Level interrupt. -output reg o_irq - -); - -// Timer registers. -reg [31:0] DEVEN; -reg [31:0] DEVPR; -reg [31:0] DEVAK; -reg [31:0] DEVST; - -`ifndef ZAP_SOC_TIMER -`define ZAP_SOC_TIMER - `define DEVEN TIMER_ENABLE_REGISTER - `define DEVPR TIMER_LIMIT_REGISTER - `define DEVAK TIMER_INTACK_REGISTER - `define DEVST TIMER_START_REGISTER -`endif - -// Timer core. -reg [31:0] ctr; // Core counter. -reg start; // Pulse to start the timer. Done signal is cleared. -reg done; // Asserted when timer is done. -reg clr; // Clears the done signal. -reg [31:0] state; // State -reg enable; // 1 to enable the timer. -reg [31:0] finalval; // Final value to count. -reg [31:0] wbstate; - -localparam IDLE = 0; -localparam COUNTING = 1; -localparam DONE = 2; - -localparam WBIDLE = 0; -localparam WBREAD = 1; -localparam WBWRITE = 2; -localparam WBACK = 3; -localparam WBDONE = 4; - -always @ (*) - o_irq = done; - -always @ (*) -begin - start = DEVST[0]; - enable = DEVEN[0]; - finalval = DEVPR; - clr = DEVAK[0]; -end - -always @ ( posedge i_clk ) -begin - DEVST <= 0; - - if ( i_rst ) - begin - DEVEN <= 0; - DEVPR <= 0; - DEVAK <= 0; - DEVST <= 0; - wbstate <= WBIDLE; - o_wb_dat <= 0; - o_wb_ack <= 0; - end - else - begin - case(wbstate) - WBIDLE: - begin - o_wb_ack <= 1'd0; - - if ( i_wb_stb && i_wb_cyc ) - begin - if ( i_wb_wen ) - wbstate <= WBWRITE; - else - wbstate <= WBREAD; - end - end - - WBWRITE: - begin - case(i_wb_adr) - `DEVEN: // DEVEN - begin - $display($time, " - %m :: Writing register DEVEN..."); - if ( i_wb_sel[0] ) DEVEN[7:0] <= i_wb_dat >> 0; - if ( i_wb_sel[1] ) DEVEN[15:8] <= i_wb_dat >> 8; - if ( i_wb_sel[2] ) DEVEN[23:16] <= i_wb_dat >> 16; - if ( i_wb_sel[3] ) DEVEN[31:24] <= i_wb_dat >> 24; - end - - `DEVPR: // DEVPR - begin - $display($time, " - %m :: Writing register DEVPR..."); - if ( i_wb_sel[0] ) DEVPR[7:0] <= i_wb_dat >> 0; - if ( i_wb_sel[1] ) DEVPR[15:8] <= i_wb_dat >> 8; - if ( i_wb_sel[2] ) DEVPR[23:16] <= i_wb_dat >> 16; - if ( i_wb_sel[3] ) DEVPR[31:24] <= i_wb_dat >> 24; - - end - - `DEVAK: // DEVAK - begin - $display($time, " - %m :: Writing register DEVAK..."); - if ( i_wb_sel[0] ) DEVPR[7:0] <= i_wb_dat >> 0; - if ( i_wb_sel[1] ) DEVPR[15:8] <= i_wb_dat >> 8; - if ( i_wb_sel[2] ) DEVPR[23:16] <= i_wb_dat >> 16; - if ( i_wb_sel[3] ) DEVPR[31:24] <= i_wb_dat >> 24; - end - - `DEVST: // DEVST - begin - $display($time, " - %m :: Writing register DEVST..."); - if ( i_wb_sel[0] ) DEVST[7:0] <= i_wb_dat >> 0; - if ( i_wb_sel[1] ) DEVST[15:8] <= i_wb_dat >> 8; - if ( i_wb_sel[2] ) DEVST[23:16] <= i_wb_dat >> 16; - if ( i_wb_sel[3] ) DEVST[31:24] <= i_wb_dat >> 24; - end - - endcase - - wbstate <= WBACK; - end - - WBREAD: - begin - case(i_wb_adr) - `DEVEN: o_wb_dat <= DEVEN; - `DEVPR: o_wb_dat <= DEVPR; - `DEVAK: o_wb_dat <= done; - `DEVST: o_wb_dat <= 32'd0; - endcase - - wbstate <= WBACK; - end - - WBACK: - begin - o_wb_ack <= 1'd1; - wbstate <= WBDONE; - end - - WBDONE: - begin - o_wb_ack <= 1'd0; - wbstate <= IDLE; - end - endcase - end -end - -always @ (posedge i_clk) -begin - if ( i_rst || !enable ) - begin - ctr <= 0; - done <= 0; - state <= IDLE; - end - else // if enabled - begin - case(state) - IDLE: - begin - if ( start ) - begin - $display($time," - %m :: Timer started counting..."); - state <= COUNTING; - end - end - - COUNTING: - begin - ctr <= ctr + 1; - - if ( ctr == finalval ) - begin - $display($time, " - %m :: Timer done counting..."); - state <= DONE; - end - end - - DONE: - begin - done <= 1; - - if ( start ) - begin - $display($time, " - %m :: Timer got START from DONE state..."); - done <= 0; - state <= COUNTING; - ctr <= 0; - end - else if ( clr ) // Acknowledge. - begin - $display($time, " - %m :: Timer got done in ACK state..."); - done <= 0; - state <= IDLE; - ctr <= 0; - end - end - endcase - end -end - -endmodule - -`default_nettype wire Index: trunk/src/testbench/vic.v =================================================================== --- trunk/src/testbench/vic.v (revision 57) +++ trunk/src/testbench/vic.v (nonexistent) @@ -1,188 +0,0 @@ -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- -// -- -// A simple interrupt controller. -- -// -- -// Registers: -- -// 0x0 - INT_STATUS - Interrupt status as reported by peripherals (sticky). -- -// 0x4 - INT_MASK - Interrupt mask - setting a bit to 1 masks the interrupt -- -// 0x8 - INT_CLEAR - Write 1 to a particular bit to clear the interrupt -- -// status. -- -//------------------------------------------------------------------------------ - -`default_nettype none - -module vic #( - parameter [31:0] SOURCES = 32'd4, - parameter [31:0] INTERRUPT_PENDING_REGISTER = 32'h0, - parameter [31:0] INTERRUPT_MASK_REGISTER = 32'h4, - parameter [31:0] INTERRUPT_CLEAR_REGISTER = 32'h8 -) ( - -// Clock and reset. -input wire i_clk, -input wire i_rst, - -// Wishbone interface. -input wire [31:0] i_wb_dat, -input wire [3:0] i_wb_adr, -input wire i_wb_stb, -input wire i_wb_cyc, -input wire i_wb_wen, -input wire [3:0] i_wb_sel, -output reg [31:0] o_wb_dat, -output reg o_wb_ack, - -// Interrupt sources in. Concatenate all -// sources together. -input wire [SOURCES-1:0] i_irq, - -// Interrupt output. Level interrupt. -output reg o_irq - - -); - -`ifndef ZAP_SOC_VIC -`define ZAP_SOC_VIC - `define INT_STATUS INTERRUPT_PENDING_REGISTER - `define INT_MASK INTERRUPT_MASK_REGISTER - `define INT_CLEAR INTERRUPT_CLEAR_REGISTER -`endif - -reg [31:0] INT_STATUS; -reg [31:0] INT_MASK; -reg [31:0] wbstate; - -// Wishbone states. -localparam WBIDLE = 0; -localparam WBREAD = 1; -localparam WBWRITE = 2; -localparam WBACK = 3; -localparam WBDONE = 4; - -// Send out a global interrupt signal. -always @ (posedge i_clk) -begin - o_irq <= | ( INT_STATUS & ~INT_MASK ); -end - -// Wishbone access FSM -always @ ( posedge i_clk ) -begin - if ( i_rst ) - begin - wbstate <= WBIDLE; - o_wb_dat <= 0; - o_wb_ack <= 0; - INT_MASK <= 32'hffffffff; - INT_STATUS <= 32'h0; - end - else - begin:blk1 - integer i; - - // Normally record interrupts. These are sticky bits. - for(i=0;i> 0; - if ( i_wb_sel[1] ) INT_MASK[15:8] <= i_wb_dat >> 8; - if ( i_wb_sel[2] ) INT_MASK[23:16] <= i_wb_dat >> 16; - if ( i_wb_sel[3] ) INT_MASK[31:24] <= i_wb_dat >> 24; - - end - - `INT_CLEAR: // INT_CLEAR - begin: blk22 - integer i; - - $display($time, " - %m :: Writing to INT_CLEAR register..."); - if ( i_wb_sel[0] ) for(i=0; i <=7;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0; - if ( i_wb_sel[1] ) for(i=8; i<=15;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0; - if ( i_wb_sel[2] ) for(i=16;i<=23;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0; - if ( i_wb_sel[3] ) for(i=24;i<=31;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0; - end - - default: $display($time, " - %m :: Warning: Attemting to write to illgal register..."); - - endcase - - wbstate <= WBACK; - end - - WBREAD: - begin - case(i_wb_adr) - `INT_STATUS: o_wb_dat <= `INT_STATUS; - `INT_MASK: o_wb_dat <= `INT_MASK; - - default: - begin - $display($time, " - %m --> Warning: Attempting to read from illegal register. Will return 0..."); - o_wb_dat <= 0; - end - endcase - - wbstate <= WBACK; - end - - WBACK: - begin - o_wb_ack <= 1'd1; - wbstate <= WBDONE; - end - - WBDONE: - begin - o_wb_ack <= 1'd0; - wbstate <= WBIDLE; - end - endcase - end -end - -endmodule // vic - -`default_nettype wire Index: trunk/src/testbench/uart_tx_dumper.v =================================================================== --- trunk/src/testbench/uart_tx_dumper.v (revision 57) +++ trunk/src/testbench/uart_tx_dumper.v (nonexistent) @@ -1,143 +0,0 @@ -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- - -`default_nettype none - -// -// P = 0 UART0 P = 1 UART1 -// -// Assumes no parity, 8 bits per character and -// 1 stop bit. -// Writes UART output to a file. -// -// If UART0, output file is `UART0_FILE_PATH -// If UART1, output file is `UART1_FILE_PATH -// - -module uart_tx_dumper #(parameter [0:0] P = 0 ) ( input wire i_clk, input wire i_line ); - -localparam UART_WAIT_FOR_START = 0; -localparam UART_RX = 1; -localparam UART_STOP_BIT = 2; - -integer uart_state = UART_WAIT_FOR_START; -reg uart_sof = 1'd0; -reg uart_eof = 1'd0; -integer uart_ctr = 0; -integer uart_bit_ctr = 1'dx; -reg [7:0] uart_sr = 0; -reg [7:0] UART_SR = 0; -reg UART_SR_DAV = 0; -wire uart; -integer signed fh; - -assign uart = i_line; - -always @ ( posedge i_clk ) -begin - UART_SR_DAV = 1'd0; - uart_sof = 1'd0; - uart_eof = 1'd0; - - case ( uart_state ) - UART_WAIT_FOR_START: - begin - if ( !uart ) - begin - uart_ctr = uart_ctr + 1; - uart_sof = 1'd1; - end - - if ( !uart && uart_ctr == 16 ) - begin - uart_sof = 1'd0; - uart_state = UART_RX; - uart_ctr = 0; - uart_bit_ctr = 0; - end - end - - UART_RX: - begin - uart_ctr++; - - if ( uart_ctr == 2 ) - uart_sr = uart_sr >> 1 | uart << 7; - - if ( uart_ctr == 16 ) - begin - uart_bit_ctr++; - uart_ctr = 0; - - if ( uart_bit_ctr == 8 ) - begin - uart_state = UART_STOP_BIT; - UART_SR = uart_sr; - UART_SR_DAV = 1'd1; - uart_ctr = 0; - uart_bit_ctr = 0; - end - end - end - - UART_STOP_BIT: - begin - uart_ctr++; - - if ( uart && uart_ctr == 16 ) // Stop bit. - begin - uart_state = UART_WAIT_FOR_START; - uart_bit_ctr = 0; - uart_ctr = 0; - end - end - endcase -end - -initial -begin - if ( P == 0 ) - fh = $fopen(`UART0_FILE_PATH_TX, "w"); - else - fh = $fopen(`UART1_FILE_PATH_TX, "w"); - - if ( fh == -1 ) - begin - $display($time, " - %m :: Error: Failed to open UART output log."); - $finish; - end -end - -always @ (negedge i_clk) -begin - if ( UART_SR_DAV ) - begin - $display("UART Wrote %c", UART_SR); - $fwrite(fh, "%c", UART_SR); - $fflush(fh); - end -end - -endmodule // uart_tx_dumper - -`default_nettype wire Index: trunk/src/testbench/uart_rx_logger.v =================================================================== --- trunk/src/testbench/uart_rx_logger.v (revision 57) +++ trunk/src/testbench/uart_rx_logger.v (nonexistent) @@ -1,90 +0,0 @@ -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- - -`default_nettype none - -// -// P = 0 UART0 P = 1 UART1 -// -// Assumes no parity, 8 bits per character and -// 1 stop bit. -// -// Gets UART characters from file and serializes them. -// -// If UART0, output file is `UART0_FILE_PATH_RX -// If UART1, output file is `UART1_FILE_PATH_RX -// - -module uart_rx_logger #(parameter [0:0] P = 0 ) ( input wire i_clk, output reg o_line = 1'd1 ); - -integer signed fh; -reg feof; -integer signed wchar; - -initial -begin - if ( P == 0 ) - fh = $fopen(`UART0_FILE_PATH_RX, "r+"); - else - fh = $fopen(`UART1_FILE_PATH_RX, "r+"); - - if ( fh == 0 ) - begin - $display($time, " - %m :: Error: Failed to open UART input stream. Handle = %d", fh); - $finish; - end - - while ( 1 ) - begin - wchar = $fgetc(fh); - - if ( wchar != -1 ) - write_to_uart (wchar); - else - begin - @(posedge i_clk); - end - end -end - -task write_to_uart ( input integer signed wchar ); -begin - repeat(16) @(posedge i_clk) o_line <= 1'd0; - repeat(16) @(posedge i_clk) o_line <= wchar[0]; - repeat(16) @(posedge i_clk) o_line <= wchar[1]; - repeat(16) @(posedge i_clk) o_line <= wchar[2]; - repeat(16) @(posedge i_clk) o_line <= wchar[3]; - repeat(16) @(posedge i_clk) o_line <= wchar[4]; - repeat(16) @(posedge i_clk) o_line <= wchar[5]; - repeat(16) @(posedge i_clk) o_line <= wchar[6]; - repeat(16) @(posedge i_clk) o_line <= wchar[7]; - - // Wait 1K clocks between input bytes. - repeat(1024) @(posedge i_clk) o_line <= 1'd1; -end -endtask - -endmodule // uart_rx_logger - -`default_nettype wire - Index: trunk/src/testbench/chip_top.v =================================================================== --- trunk/src/testbench/chip_top.v (revision 57) +++ trunk/src/testbench/chip_top.v (nonexistent) @@ -1,326 +0,0 @@ -// ----------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- -------------------------------------------------------------------------- -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// ----------------------------------------------------------------------------- -// -// This is the chip top that contains the ZAP core along with -// 2 x UARTs -// 2 x Timers -// 1 x VIC -// -// UART0 address space FFFFFFE0 to FFFFFFFF -// Timer0 address space FFFFFFC0 to FFFFFFDF -// VIC0 address space FFFFFFA0 to FFFFFFBF -// UART1 address space FFFFFF80 to FFFFFF9F -// Timer1 address space FFFFFF60 to FFFFFF7F -// -// Accesses outside this go the the wishbone interface. -// -// An extenal Wishbone interface is provided to allow connection to an external -// Wishbone network for RAMs, ROMs etc. -// -// ----------------------------------------------------------------------------- - -module chip_top #( - -// CPU config. -parameter DATA_SECTION_TLB_ENTRIES = 4, -parameter DATA_LPAGE_TLB_ENTRIES = 8, -parameter DATA_SPAGE_TLB_ENTRIES = 16, -parameter DATA_CACHE_SIZE = 1024, -parameter CODE_SECTION_TLB_ENTRIES = 4, -parameter CODE_LPAGE_TLB_ENTRIES = 8, -parameter CODE_SPAGE_TLB_ENTRIES = 16, -parameter CODE_CACHE_SIZE = 1024, -parameter FIFO_DEPTH = 4, -parameter BP_ENTRIES = 1024, -parameter STORE_BUFFER_DEPTH = 32 - -)( - // Clk and rst - input wire SYS_CLK, - input wire SYS_RST, - - // UART 0 - input wire UART0_RXD, - output wire UART0_TXD, - - // UART 1 - input wire UART1_RXD, - output wire UART1_TXD, - - // Remaining IRQs to the interrupt controller. - input wire [27:0] I_IRQ, - - // Single FIQ input directly to ZAP CPU. - input wire I_FIQ, - - // External Wishbone Connection (for RAMs etc). - output wire O_WB_STB, - output wire O_WB_CYC, - output wire [31:0] O_WB_DAT, - output wire [31:0] O_WB_ADR, - output wire [3:0] O_WB_SEL, - output wire O_WB_WE, - input wire I_WB_ACK, - input wire [31:0] I_WB_DAT -); - -`include "zap_defines.vh" -`include "zap_localparams.vh" -`include "zap_functions.vh" - -// Peripheral addresses. -localparam UART0_LO = 32'hFFFFFFE0; -localparam UART0_HI = 32'hFFFFFFFF; -localparam TIMER0_LO = 32'hFFFFFFC0; -localparam TIMER0_HI = 32'hFFFFFFDF; -localparam VIC_LO = 32'hFFFFFFA0; -localparam VIC_HI = 32'hFFFFFFBF; -localparam UART1_LO = 32'hFFFFFF80; -localparam UART1_HI = 32'hFFFFFF9F; -localparam TIMER1_LO = 32'hFFFFFF60; -localparam TIMER1_HI = 32'hFFFFFF7F; - -// Internal signals. -wire i_clk = SYS_CLK; -wire i_reset = SYS_RST; -wire [1:0] uart_in = {UART1_RXD, UART0_RXD}; -wire [1:0] uart_out; -assign {UART1_TXD, UART0_TXD} = uart_out; -wire data_wb_cyc; -wire data_wb_stb; -reg [31:0] data_wb_din; -reg data_wb_ack; -reg data_wb_cyc_ram, data_wb_cyc_uart [1:0], data_wb_cyc_timer [1:0], data_wb_cyc_vic; -reg data_wb_stb_ram, data_wb_stb_uart [1:0], data_wb_stb_timer [1:0], data_wb_stb_vic; -wire [31:0] data_wb_din_ram, data_wb_din_uart [1:0], data_wb_din_timer [1:0], data_wb_din_vic; -wire data_wb_ack_ram, data_wb_ack_uart [1:0], data_wb_ack_timer [1:0], data_wb_ack_vic; -wire [3:0] data_wb_sel; -wire data_wb_we; -wire [31:0] data_wb_dout; -wire [31:0] data_wb_adr; -wire [2:0] data_wb_cti; // Cycle Type Indicator. -wire global_irq; -wire [1:0] uart_irq; -wire [1:0] timer_irq; -wire ext_stb; -wire ext_cyc; -wire [31:0] ext_adr; - -// Assigns. -assign O_WB_CYC = data_wb_cyc_ram; -assign O_WB_STB = data_wb_stb_ram; -assign O_WB_ADR = data_wb_adr; -assign O_WB_WE = data_wb_we; -assign O_WB_DAT = data_wb_dout; -assign O_WB_SEL = data_wb_sel; -assign data_wb_din_ram = I_WB_DAT; -assign data_wb_ack_ram = I_WB_ACK; - -// Wishbone selector. -always @* -begin:blk1 - integer ii; - - for(ii=0;ii<=1;ii=ii+1) - begin - data_wb_cyc_uart [ii] = 0; - data_wb_stb_uart [ii] = 0; - data_wb_cyc_timer[ii] = 0; - data_wb_stb_timer[ii] = 0; - end - - data_wb_cyc_vic = 0; - data_wb_stb_vic = 0; - - if ( data_wb_adr >= UART0_LO && data_wb_adr <= UART0_HI ) // UART0 access - begin - data_wb_cyc_uart[0] = data_wb_cyc; - data_wb_stb_uart[0] = data_wb_stb; - data_wb_ack = data_wb_ack_uart[0]; - data_wb_din = data_wb_din_uart[0]; - end - else if ( data_wb_adr >= TIMER0_LO && data_wb_adr <= TIMER0_HI ) // Timer0 access - begin - data_wb_cyc_timer[0] = data_wb_cyc; - data_wb_stb_timer[0] = data_wb_stb; - data_wb_ack = data_wb_ack_timer[0]; - data_wb_din = data_wb_din_timer[0]; - end - else if ( data_wb_adr >= VIC_LO && data_wb_adr <= VIC_HI ) // VIC access. - begin - data_wb_cyc_vic = data_wb_cyc; - data_wb_stb_vic = data_wb_stb; - data_wb_ack = data_wb_ack_vic; - data_wb_din = data_wb_din_vic; - end - else if ( data_wb_adr >= UART1_LO && data_wb_adr <= UART1_HI ) // UART1 access - begin - data_wb_cyc_uart[1] = data_wb_cyc; - data_wb_stb_uart[1] = data_wb_stb; - data_wb_ack = data_wb_ack_uart[1]; - data_wb_din = data_wb_din_uart[1]; - end - else if ( data_wb_adr >= TIMER1_LO && data_wb_adr <= TIMER1_HI ) // Timer1 access - begin - data_wb_cyc_timer[1] = data_wb_cyc; - data_wb_stb_timer[1] = data_wb_stb; - data_wb_ack = data_wb_ack_timer[1]; - data_wb_din = data_wb_din_timer[1]; - end - else // External WB access. - begin - data_wb_ack = data_wb_ack_ram; - data_wb_din = data_wb_din_ram; - end -end - -always @ (posedge i_clk) -begin - if ( ext_adr < TIMER1_LO ) - begin - data_wb_cyc_ram <= ext_cyc; - data_wb_stb_ram <= ext_stb; - end - else - begin - data_wb_cyc_ram <= 1'd0; - data_wb_stb_ram <= 1'd0; - end -end - -// ========================= -// Processor core. -// ========================= - -zap_top #( - .FIFO_DEPTH(FIFO_DEPTH), - .BP_ENTRIES(BP_ENTRIES), - .STORE_BUFFER_DEPTH(STORE_BUFFER_DEPTH), - .DATA_SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES), - .DATA_LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES), - .DATA_SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES), - .DATA_CACHE_SIZE(DATA_CACHE_SIZE), - .CODE_SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES), - .CODE_LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES), - .CODE_SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES), - .CODE_CACHE_SIZE(CODE_CACHE_SIZE) -) -u_zap_top -( - .i_clk(i_clk), - .i_reset(i_reset), - .i_irq(global_irq), - .i_fiq (I_FIQ), - .o_wb_cyc (data_wb_cyc), - .o_wb_stb (data_wb_stb), - .o_wb_adr (data_wb_adr), - .o_wb_we (data_wb_we), - .o_wb_cti (data_wb_cti), - .i_wb_dat (data_wb_din), - .o_wb_dat (data_wb_dout), - .i_wb_ack (data_wb_ack), - .o_wb_sel (data_wb_sel), - - // Strobe and CYC nxt pins. - .o_wb_stb_nxt (ext_stb), - .o_wb_cyc_nxt (ext_cyc), - .o_wb_adr_nxt (ext_adr), - - .o_wb_bte () // Always zero. - -); - -// =============================== -// 2 x UART + 2 x Timer -// =============================== - -genvar gi; -generate -begin - for(gi=0;gi<=1;gi=gi+1) - begin: uart_gen - uart_top u_uart_top ( - - // WISHBONE interface - .wb_clk_i(i_clk), - .wb_rst_i(i_reset), - .wb_adr_i(data_wb_adr), - .wb_dat_i(data_wb_dout), - .wb_dat_o(data_wb_din_uart[gi]), - .wb_we_i (data_wb_we), - .wb_stb_i(data_wb_stb_uart[gi]), - .wb_cyc_i(data_wb_cyc_uart[gi]), - .wb_sel_i(data_wb_sel), - .wb_ack_o(data_wb_ack_uart[gi]), - .int_o (uart_irq[gi]), // Interrupt. - - // UART signals. - .srx_pad_i (uart_in[gi]), - .stx_pad_o (uart_out[gi]), - - // Tied or open. - .rts_pad_o(), - .cts_pad_i(1'd0), - .dtr_pad_o(), - .dsr_pad_i(1'd0), - .ri_pad_i (1'd0), - .dcd_pad_i(1'd0) - ); - - timer u_timer ( - .i_clk(i_clk), - .i_rst(i_reset), - .i_wb_adr(data_wb_adr), - .i_wb_dat(data_wb_dout), - .i_wb_stb(data_wb_stb_timer[gi]), - .i_wb_cyc(data_wb_cyc_timer[gi]), // From core - .i_wb_wen(data_wb_we), - .i_wb_sel(data_wb_sel), - .o_wb_dat(data_wb_din_timer[gi]), // To core. - .o_wb_ack(data_wb_ack_timer[gi]), - .o_irq(timer_irq[gi]) // Interrupt - ); - end -end -endgenerate - -// =============================== -// VIC -// =============================== - -vic #(.SOURCES(32)) u_vic ( - .i_clk (i_clk), - .i_rst (i_reset), - .i_wb_adr(data_wb_adr), - .i_wb_dat(data_wb_dout), - .i_wb_stb(data_wb_stb_vic), - .i_wb_cyc(data_wb_cyc_vic), // From core - .i_wb_wen(data_wb_we), - .i_wb_sel(data_wb_sel), - .o_wb_dat(data_wb_din_vic), // To core. - .o_wb_ack(data_wb_ack_vic), - .i_irq({I_IRQ, timer_irq[1], uart_irq[1], timer_irq[0], uart_irq[0]}), // Concatenate 32 interrupt sources. - .o_irq(global_irq) // Interrupt out -); - -endmodule // chip_top Index: trunk/makefile =================================================================== --- trunk/makefile (revision 57) +++ trunk/makefile (nonexistent) @@ -1,9 +0,0 @@ -.PHONY: clean -.PHONY: error - -error: - @echo "To run a TC, go to src/ts and do a make there. Only target supported here is 'clean'." - -clean: - @echo "Removing object folder." - rm -rf obj/ Index: trunk/README.md =================================================================== --- trunk/README.md (revision 57) +++ trunk/README.md (revision 58) @@ -1,7 +1,7 @@ ## NOTE: This project was designed by me as a part of a student design contest. It is no longer actively supported. +## This project's files are hosted on GitHub. +## The ZAP ARM Processor (ARMv5T Compatible, FPGA Synthesizable Soft Processor) @ https://github.com/krevanth/ZAP.git -## The ZAP ARM Processor (ARMv5T Compatible, FPGA Synthesizable Soft Processor) - ### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com) ### Introduction @@ -18,12 +18,10 @@ #### Repos -This project is hosted on Github and Opencores. +This project is hosted on Github. GIT: https://github.com/krevanth/ZAP -SVN: https://opencores.org/projects/zap - #### Features ##### ZAP Processor (zap_top.v) @@ -100,10 +98,18 @@ | output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. | | output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. | -### Directory Structure +### Installation and Directory Structure (GIT) +To get the files of the ZAP processor, please execute: +```bash +git pull https://github.com/krevanth/ZAP.git +``` +This should provide the following file structure: + + + ├── LICENSE ├── makefile ├── README.md

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