URL
https://opencores.org/ocsvn/zet86/zet86/trunk
Subversion Repositories zet86
Compare Revisions
- This comparison shows the changes necessary to convert path
/zet86/tags/INITIAL/sim
- from Rev 3 to Rev 49
- ↔ Reverse comparison
Rev 3 → Rev 49
/testbench.v
0,0 → 1,40
`timescale 10ns/100ps |
|
module testbench; |
|
// Net declarations |
wire [15:0] rd_data; |
wire [15:0] wr_data, mem_data, io_data; |
wire [19:0] addr; |
wire we; |
wire m_io; |
wire byte_m; |
|
reg clk, rst; |
reg [15:0] io_reg; |
|
// Module instantiations |
memory mem0 (clk, addr, wr_data, mem_data, we & ~m_io, byte_m); |
cpu cpu0 (clk, rst, rd_data, wr_data, addr, we, m_io, byte_m,, 1'b1); |
|
// Assignments |
assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0; |
assign rd_data = m_io ? io_data : mem_data; |
|
// Behaviour |
// IO Stub |
always @(posedge clk) |
if (addr==20'hb7 & ~we & m_io) |
io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data; |
|
always #1 clk = ~clk; |
|
initial |
begin |
clk <= 1'b1; |
rst <= 1'b0; |
#5 rst <= 1'b1; |
#2 rst <= 1'b0; |
end |
|
endmodule |
/modelsim/tb.do
0,0 → 1,29
vdel -all -lib work |
vlib work |
vlog -work work +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v |
vlog -work work +incdir+.. ../memory.v ../testbench.v |
vsim -novopt -t ns work.testbench |
add wave /testbench/clk |
add wave /testbench/rst |
add wave -radix hexadecimal /testbench/cpu0/fetch0/pc |
add wave -radix hexadecimal /testbench/cpu0/fetch0/state |
add wave -radix hexadecimal /testbench/cpu0/fetch0/next_state |
add wave -radix hexadecimal /testbench/cpu0/fetch0/opcode |
add wave -radix hexadecimal /testbench/cpu0/fetch0/modrm |
add wave /testbench/cpu0/fetch0/end_seq |
add wave -radix hexadecimal sim:/testbench/rd_data |
add wave -radix hexadecimal sim:/testbench/wr_data |
add wave sim:/testbench/cpu0/fetch0/need_modrm |
add wave sim:/testbench/cpu0/fetch0/need_off |
add wave sim:/testbench/cpu0/fetch0/need_imm |
add wave sim:/testbench/cpu0/fetch0/ir |
add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/imm |
add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/off |
add wave -radix hexadecimal sim:/testbench/addr |
add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/r\[15\] |
add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/d |
add wave sim:/testbench/cpu0/exec0/reg0/addr_a |
add wave sim:/testbench/cpu0/exec0/reg0/addr_d |
add wave sim:/testbench/cpu0/exec0/reg0/wr |
add wave sim:/testbench/we |
add wave sim:/testbench/cpu0/fetch_or_exec |
/memory.v
0,0 → 1,28
`timescale 1ns/10ps |
|
module memory ( |
input clk, |
input [19:0] addr, |
input [15:0] wr_data, |
output [15:0] rd_data, |
input we, |
input byte_m |
); |
|
// Registers and nets |
wire [19:0] addr1; |
|
reg [7:0] ram[2**20-1:0]; |
|
// Assignments |
assign rd_data = byte_m ? { {8{ram[addr][7]}}, ram[addr]} |
: {ram[addr1], ram[addr]}; |
assign addr1 = addr + 20'd1; |
|
// Behaviour |
always @(posedge clk) |
if (~we) if (byte_m) ram[addr] <= wr_data[7:0]; |
else { ram[addr1], ram[addr] } <= wr_data; |
|
initial $readmemh("/home/zeus/zet/sim/09_vdu.rtlrom", ram, 20'hf0000); |
endmodule |