URL
https://opencores.org/ocsvn/zet86/zet86/trunk
Subversion Repositories zet86
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- This comparison shows the changes necessary to convert path
/zet86/trunk
- from Rev 52 to Rev 53
- ↔ Reverse comparison
Rev 52 → Rev 53
/rtl-model/cpu.v
224,6 → 224,7
|
// Register and nets declarations |
reg [ 1:0] cs; // current state |
reg [ 1:0] ns; // next state |
|
wire op; // in an operation |
wire odd_word; // unaligned word |
234,11 → 235,10
wire [ 1:0] sel_o; // bus byte select |
|
// Declare the symbolic names for states |
parameter [1:0] |
cyc0_lo = 3'd0, |
stb1_hi = 3'd1, |
stb1_lo = 3'd2, |
stb2_hi = 3'd3; |
localparam [1:0] |
IDLE = 2'd0, |
stb1_lo = 2'd1, |
stb2_hi = 2'd2; |
|
// Assignments |
assign op = (cpu_memop | cpu_m_io); |
257,7 → 257,7
// Behaviour |
// cpu_dat_i |
always @(posedge wb_clk_i) |
cpu_dat_i <= (cs == cyc0_lo) ? |
cpu_dat_i <= (cs == IDLE) ? |
(wb_ack_i ? |
(a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i)) |
: cpu_dat_i) |
276,14 → 276,6
wb_stb_o <= op; |
wb_cyc_o <= op; |
end |
stb1_hi: |
begin |
cpu_block <= odd_word | wb_ack_i; |
wb_adr_o <= cpu_adr_o[19:1]; |
wb_sel_o <= sel_o; |
wb_stb_o <= 1'b0; |
wb_cyc_o <= odd_word; |
end |
stb1_lo: |
begin |
cpu_block <= 1'b1; |
303,16 → 295,18
endcase |
|
// state machine |
// cs - current state |
always @(posedge wb_clk_i) |
if (wb_rst_i) cs <= cyc0_lo; |
else |
case (cs) |
default: cs <= wb_ack_i ? (op ? stb1_hi : cyc0_lo) |
: cyc0_lo; |
stb1_hi: cs <= wb_ack_i ? stb1_hi |
: (odd_word ? stb1_lo : cyc0_lo); |
stb1_lo: cs <= wb_ack_i ? stb2_hi : stb1_lo; |
stb2_hi: cs <= wb_ack_i ? stb2_hi : cyc0_lo; |
endcase |
cs <= wb_rst_i ? IDLE : ns; |
|
// ns - next state |
always @(*) |
case (cs) |
default: ns <= wb_ack_i ? |
(op ? (odd_word ? stb1_lo : stb2_hi) : IDLE) |
: IDLE; |
stb1_lo: ns <= wb_ack_i ? stb2_hi : stb1_lo; |
stb2_hi: ns <= wb_ack_i ? stb2_hi : IDLE; |
endcase |
|
endmodule |
/impl/virtex4-ml403ep/sim/t.do
2,7 → 2,7
vdel -all -lib work |
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims |
vlib work |
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../../../soc/aceusb/rtl/aceusb_access.v ../../../soc/aceusb/rtl/aceusb_sync.v ../../../soc/aceusb/rtl/aceusb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v |
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../../../soc/aceusb/rtl/aceusb_access.v ../../../soc/timer.v ../../../soc/simple_pic.v ../../../soc/aceusb/rtl/aceusb_sync.v ../../../soc/aceusb/rtl/aceusb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v |
vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v |
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl |
add wave -label clk100 /testbench/clk |
34,11 → 34,13
add wave -label wr -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/wr |
add wave -divider wb_master |
add wave -label cs -radix hexadecimal /testbench/kotku/zet_proc/wm0/cs |
add wave -label ns -radix hexadecimal /testbench/kotku/zet_proc/wm0/ns |
add wave -label op -radix hexadecimal /testbench/kotku/zet_proc/wm0/op |
add wave -label wb_block /testbench/kotku/zet_proc/wb_block |
add wave -label dat_o -radix hexadecimal sim:/testbench/kotku/dat_o |
add wave -label dat_i -radix hexadecimal sim:/testbench/kotku/dat_i |
add wave -label adr -radix hexadecimal /testbench/kotku/adr |
add wave -label odd_word -radix hexadecimal /testbench/kotku/zet_proc/wm0/odd_word |
add wave -label byte_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_byte_o |
add wave -label sel_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_sel_o |
add wave -label stb_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_stb_o |
65,6 → 67,6
add wave -label we /testbench/kotku/we |
add wave -label ack /testbench/kotku/ack |
add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec |
add wave -divider ace_cf |
add wave -radix hexadecimal -r /testbench/kotku/ace_cf/* |
run 1ms |
add wave -divider zbt |
add wave -radix hexadecimal -r /testbench/kotku/zbt0/* |
run 50us |
/impl/virtex4-ml403ep/sim/flash_stub.v
16,7 → 16,7
assign flash_data_ = flash_ce2_ ? dat_o : 32'hzzzzzzzz; |
|
// Behaviour |
initial $readmemh("22_sysace.ml403", rom, 21'h0); |
initial $readmemh("00_mov.ml403", rom, 21'h0); |
initial $readmemh("hd.ml403", rom, 21'h100000); |
|
always @(*) dat_o <= #110 |
/impl/virtex4-ml403ep/mem/flash_cntrl.v
63,7 → 63,8
// sft_cnt |
always @(posedge wb_clk_i) |
sft_cnt <= wb_rst_i ? 0 |
: (op ? { sft_cnt[timeout-2:0], op } : 0); |
: (op ? ((|sft_cnt) ? { sft_cnt[timeout-2:0], 1'b0 } |
: { sft_cnt[timeout-2:0], 1'b1 }) : 0); |
|
// base |
always @(posedge wb_clk_i) |
/impl/virtex4-ml403ep/mem/zbt_cntrl.v
34,7 → 34,7
input [ 1:0] wb_sel_i, |
input wb_stb_i, |
input wb_cyc_i, |
output reg wb_ack_o, |
output wb_ack_o, |
|
// Pad signals |
output sram_clk_, |
51,28 → 51,25
wire nload; |
|
`ifndef DEBUG |
reg [ 2:0] cnt; |
reg [ 3:0] cnt; |
wire op; |
`endif |
|
// Continuous assignments |
assign op = wb_stb_i & wb_cyc_i; |
assign nload = (|cnt || wb_ack_o); |
assign nload = |cnt; |
|
assign sram_clk_ = wb_clk_i; |
assign sram_adv_ld_n_ = 1'b0; |
assign sram_data_ = (op && wb_we_i) ? wr : 32'hzzzzzzzz; |
assign wb_ack_o = cnt[3]; |
|
// Behaviour |
// cnt |
always @(posedge wb_clk_i) |
cnt <= wb_rst_i ? 3'b0 |
: { cnt[1:0], nload ? 1'b0 : op }; |
cnt <= wb_rst_i ? 4'b0 |
: { cnt[2:0], nload ? 1'b0 : op }; |
|
// wb_ack_o |
always @(posedge wb_clk_i) |
wb_ack_o <= wb_rst_i ? 1'b0 : (wb_ack_o ? op : cnt[2]); |
|
// wb_dat_o |
always @(posedge wb_clk_i) |
wb_dat_o <= cnt[2] ? (wb_adr_i[1] ? sram_data_[31:16] |
/soc/aceusb/rtl/aceusb.v
111,13 → 111,12
|
/* Main FSM */ |
|
reg [1:0] state; |
reg [1:0] next_state; |
reg state; |
reg next_state; |
|
localparam |
IDLE = 2'd0, |
WAIT = 2'd1, |
ACK = 2'd2; |
IDLE = 1'd0, |
WAIT = 1'd1; |
|
assign op = wb_cyc_i & wb_stb_i; |
|
154,13 → 153,6
access_write = 1'b0; |
load_adr_dat = 1'b0; |
access_read = 1'b0; |
next_state = ACK; |
end |
end |
|
ACK: begin |
if(!op) begin |
wb_ack_o = 1'b0; |
next_state = IDLE; |
end |
end |
/soc/vga/rtl/vdu.v
30,7 → 30,7
input [ 1:0] wb_sel_i, |
input wb_stb_i, |
input wb_cyc_i, |
output reg wb_ack_o, |
output wb_ack_o, |
|
// VGA pad signals |
output reg [ 1:0] vga_red_o, |
106,7 → 106,7
reg [6:0] hor_addr; // 0 to 79 |
reg [6:0] ver_addr; // 0 to 124 |
reg vga0_we; |
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw; |
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw, vga5_rw; |
reg vga1_we; |
reg vga2_we; |
reg buff_we; |
193,9 → 193,9
assign v_retrace = !video_on_v; |
assign vh_retrace = v_retrace | !video_on_h; |
assign status_reg1 = { 11'b0, v_retrace, 3'b0, vh_retrace }; |
assign wb_ack_o = wb_tga_i ? stb : vga5_rw; |
|
// Behaviour |
|
// CPU write interface |
always @(posedge wb_clk_i) |
if (wb_rst_i) |
221,23 → 221,10
end |
|
// CPU read interface |
// wb_dat_o |
always @(posedge wb_clk_i) |
if (wb_rst_i) |
begin |
wb_dat_o <= 16'h0; |
wb_ack_o <= 16'h0; |
end |
else |
if (wb_tga_i) |
begin |
wb_dat_o <= status_reg1; |
wb_ack_o <= stb; |
end |
else |
begin |
wb_dat_o <= vga4_rw ? out_data : wb_dat_o; |
wb_ack_o <= vga4_rw ? 1'b1 : (wb_ack_o && stb); |
end |
wb_dat_o <= wb_rst_i ? 16'h0 : (wb_tga_i ? status_reg1 |
: (vga4_rw ? out_data : wb_dat_o)); |
|
// Control registers |
always @(posedge wb_clk_i) |
313,6 → 300,7
vga2_rw <= 1'b0; |
vga3_rw <= 1'b0; |
vga4_rw <= 1'b0; |
vga5_rw <= 1'b0; |
ver_addr <= 7'b0; |
hor_addr <= 7'b0; |
|
363,6 → 351,7
attr_we <= vga2_rw ? (attr0_we & vga2_we) : 1'b0; |
vga3_rw <= vga2_rw; |
vga4_rw <= vga3_rw; |
vga5_rw <= vga4_rw; |
end |
|
// Video shift register |